Hot carrier mechanisms in advanced NMOS transistors 7

Chapter Six Self-Heating Induced Spatial Spread of Interface State Generation by Hot-Electron Effect: Role of the High-Energy Tail Electrons Hot-electron induced degradation remains a critical reliability issue for the SOI [1]-[3], and strained-Si [4][5] N-MOSFETs, as well as for N-MOSFETs employed in the IO circuit. These devices have one feature in common, i.e. they suffer from significant self-heating due either to poor thermal conduction of the surrounding material [6]-[9] or high power dissipation in the case of the IO device. Consequently, the impact of self-heating on the hot-electron induced degradation in N-MOSFET remains secondary if the increase in channel temperature is not significant. Nevertheless, as the scaling of CMOS continues, this issue could not be ignored [10][2][3]. In view of a positive temperature coefficient of impact ionization [11][12], the excess hot-carrier currents induced by self-heating [1] has important implications on the hot-electron reliability of the device. In this chapter, an analysis via a resistance-based measurement method [13][14] indicated that the spatial distribution of hot-electron generated oxide and interface traps is significantly increased in devices such as strained-Si/Si1-xGex N- Chapter Spatial Interface Damage Due to Self-heating 161 MOSFET, which suffer from substantial self-heating. In these devices, trap generation occurs over a significant portion of the channel region even at very short stress time. The effect of self-heating on the interface state generation is further supported when these devices were stressed under ac conditions. As self-heating is becoming increasingly important in future technologies, the increased spatial spread of hotelectron induced oxide damage has a significant impact on the hot-electron reliability of scaled N-MOSFETs. This work provides important insights into the mechanism of hot-electron induced degradation in devices where high channel temperature is present. 6.1 Experimental The strained-Si/SiGe N-MOSFET was used as the test vehicle for demonstrating the effect of self-heating on the spatial distribution of hot-electron induced interface damage. Similar tests were also carried out on the conventional bulk-Si N-MOSFET for comparison. The strained-Si N-MOSFET was fabricated on a µm thick compositionally-graded and relaxed SiGe buffer having 20 at. % Ge concentration. The final thickness of the strained-Si layer was 15 nm. The gate oxide is a nm direct tunneling oxynitride achieved via rapid thermal oxidation and N2O annealing. To minimize strain relaxation and Ge out-diffusion during processing, the STI sidewall oxide and the implant screen oxide were replaced by a low temperature TEOS oxide. The bulk-Si device was fabricated using an identical processing sequence. The test devices had drawn channel length of 0.18 µm and width W = 20 and 0.5 µm. Channel hot-electron stress was carried out at equal gate (Vgs) and drain (Vds) voltages, i.e. Vgs = Vds = 2.7 V. This stress condition was shown to result in the worst-case degradation [13]. A delay was introduced after stopping the stress and before post-stress measurement to eliminate effect of die temperature increase (caused by self-heating) on the device I-V characteristic. Chapter Spatial Interface Damage Due to Self-heating 162 6.2 Non-Local Interface State Generation via Channel-Hot-Electron Stress A resistance-based measurement method [14][15] was adopted to delineate hotelectron induced interface damage at the drain from that in the channel. In this approach, linear drain current degradation, ∆Id/Ido was extracted at two gate measurement voltages, Vgm1 and Vgm2. Vgm1 was chosen to be slightly less than Vto (~0.3 V), the threshold voltage of the N-MOSFET before stress was applied. This gate voltage biases the N-MOSFET in weak inversion. The resistance of the channel, Rch is much greater than the parasitic source and drain series resistance (Rsd). The drain current Id is therefore determined by Rch. Negative interface trapped charge in the channel results in an increase in the threshold voltage and mobility degradation. This, in turn, increases Rch and decreases Id correspondingly. Interface damage above the drain extension though also increases the drain series resistance Rd, the effect on Id is relatively small since Rch >> Rd. On the other hand, Vgm2 was set to 1.8 V, which is much larger than Vto. A large gate overdrive reduces the effect of interface damage in the channel on Rch, making Rch comparable to Rsd. As a consequence, the relative influence of interface damage above the drain extension on Id degradation (via an increase in Rd) is enhanced. Thus, hot-electron induced interface damage in the channel (or above the drain extension) may be sensitively probed by ∆Id/Ido measured at Vgm1 (or Vgm2). Fig. 6.1 shows a comparison of the time-dependent shift in ∆Id/Ido of the strained-Si and bulk-Si devices (W = 20 µm). For the latter, ∆Id/Ido (@ Vgm1) < % in the initial stage and it increases progressively with stress time. This is a classical behavior, i.e. hot-electron induced interface damage is initially localized at the drain and it spread progressively into the channel at long stress time [14][15]. The marginally smaller ∆Id/Ido (@ Vgm2) in the initial Chapter Spatial Interface Damage Due to Self-heating 163 stage may be attributed to a relatively heavy implant dose of the drain extension. As a result, increase of drain series resistance due to interface damage at the gate edge is suppressed. Fractional Degradation of Linear Drain Current, ∆Id / Ido m1 10 Vg ~Vto 10 -1 10 -2 m2 Vg =1.8 V Bulk-Si 20% Ge L/W = 0.18/20 10 -1 10 10 10 Stress Time, t (s) Fig. 6.1 Time dependent fractional degradation of the linear drain current, ∆Id/Ido. The strained-Si N-MOSFET exhibits a very significant shift in ∆Id/Ido (@ Vgm1 ~Vto) at short stress time, indicating substantial generation of interface states in the channel. On the other hand, ∆Id/Ido (@Vgm1) ≈ 70% for the strained-Si N-MOSFET at stress time t = s. At t = 102 s, ∆Id/Ido (@ Vgm1) of the strained-Si device reaches nearly 100 %, as compared to the mere % of the bulk-Si device. A large shift in the ∆Id/Ido (@ Vgm1) of the strained-Si device at short stress time implies significant interface state generation in the channel, i.e. a considerably wider spread in the hot-electron induced interface damage as compared to the bulk-Si device. In order to validate this inference, the spatial distribution of stress induced interface state density is extracted using the charge pumping technique [16]. The distance x from the gate edge is expressed as x= LI cp (Vgt ) I cp ,max (6.1) Chapter Spatial Interface Damage Due to Self-heating 164 where L is the channel length, Icp(Vgt) is the measured charge pumping current at particular gate top voltage Vgt and Icp,max is defined as I cp ,max = qfN it WL (6.2) where q is the elementary charge, f is the gate pulse frequency, W is the device width, Nit is the interface trap density. Fig. 6.2 shows the result of (6.1). Note x = nm is defined as the gate edge. For a pulse period of µs, capture cross section for electron of 2x10-16 cm2, and thermal carrier velocity of 1x107 cm/s, the minimum electron concentration at the surface is 1x1014 cm-3 [17]. The local threshold voltage Vt is defined as the gate voltage to accumulate 1x1014 cm-3 electrons at the interface for a given x. The proximity of the doped drain junction Gate Edge 0.6 0.4 dVt/dx Local Threshold Voltage, Vt (V) causes the Vt to reduce gradually when x approaches the gate edge. 0.2 -1 -2 0.0 -20 20 40 60 80 100 Distance x (nm) Fig. 6.2 Local threshold voltage and the corresponding derivative as a function of distance x. Next, the incremental charge pumping current ∆Icp at a certain Vgt is proportional to the number of generated interface traps from the gate edge to the point x where Vt (x) = Vgt . This generated interface traps can be used to obtain the lateral profile of ∆Nit and is given as Chapter Spatial Interface Damage Due to Self-heating ∆Nit ( x ) = 165 d∆I cp dV gt dVgt dx qfW (6.3) where dVt ( x) dV gt = dx dx (6.4) Fig. 6.3 shows the derivative of ∆Icp with respect to gate top voltage Vgt. By taking the derivatives in Fig. 6.2 and 6.3, we have obtained the lateral ∆Nit profile in Fig. 6.4. 1200 600 800 400 400 d∆ Icp/dVgt Increase in Charge Pumping Current, ∆ Icp (pA) 800 200 -2 -1 Gate Top Voltage, Vgt (V) Fig. 6.3 Increase in charge pumping current ∆Icp and the corresponding derivative d∆Icp/dVgt as a function of gate top voltage Vgt. Fig. 6.4 shows the spatial distribution of stress induced interface state density after s of stress. As expected, interface damage in the bulk-Si device peaks at the drain end (filled symbols). On the contrary, interface damage in the strained-Si device increases from the drain end towards the middle of the channel. This significant spread of interface damage over the entire channel of the strained-Si device rules out the possibility that the larger drain current degradation is due to (i) more hot-electron damage within the same region and/or (ii) a shift in the peak hot-electron damage into the channel. Moreover, this non-local interface damage Chapter Spatial Interface Damage Due to Self-heating 166 could be the result of more inferior oxide interface quality or higher vertical field in strainedSi relative to bulk Si. This hypothesis can be verified when the transistors are subjected to Fowler-Nordheim injection stress. Fig. 6.5 shows the time dependence of linear current degradation and increase in charge pump current in strained-Si and bulk Si transistor. Indeed, the relatively high gate stress voltage did not cause the non-local nature of interface damage -2 Interface Trap Density, ∆Nit (cm ) in the strained-Si device. 14 10 13 10 Filled: Bulk-Si Open: 20% Ge 1s 3 10 s 12 10 gate edge (drain side) 11 10 25 50 75 Distance x (nm) Fig. 6.4 Spatial distributions of the stress induced interface state density, extracted from charge pumping current measurement. The result confirms that hot-electron induced interface damage in the strained-Si device spread over a significant part of the channel at very short stress time. It can be seen that the interface state generation and the linear current degradation in both devices are negligibly different. Moreover, the linear current degradation ∆Id/Ido (@Vgm1) in both devices are much lower than that subjected to channel hot-electron injection as illustrated in Fig. 6.1. This is attributed to the smaller influence of the vertical field on the degradation of transistor [28]. In general, both oxide bulk and interface degradation in the strained-Si and bulk-Si devices at a given oxide field are similar, thus, indicating that both Chapter Spatial Interface Damage Due to Self-heating 167 devices have similar oxide and interface quality. It is well known that the strained-Si NMOSFET suffers from significant self-heating due to poor thermal conduction of the underlying SiGe layer [8][9]. Self-heating has been shown to give rise to excess hot-carrier 10 10 -1 10 m1 Vg ~Vto 10 -2 10 -1 10 10 Shift in Charge Pump Current, ∆Icp (pA) Fractional Degradation of Linear Drain Current, ∆Id/Ido currents [1], as a consequence of an increase in the impact ionization efficiency. 10 Stress Time, t (s) Fig. 6.5 Fractional degradation of linear current ∆Id/Ido and shift in charge pump current ∆Icp as a function of stress time t. NMOSFET of 10 µm (W) x 0.5 µm (L) are subjected to Fowler-Nordheim injection stress of Vg = 2.7 V. Note that square symbol () and bold line denote the current degradation and increase in charge pump current in strained-Si respectively. Correspondingly, triangle symbol (∆) and full line denote that for bulk Si. Impact ionization efficiency is defined as the ratio of substrate current to drain current Ib/Id [11][12]. To investigate whether the increased spread in interface damage is a result of a larger Ib/Id of the strained-Si device, the degree of self-heating and increase in Ib/Id are first compared to the bulk-Si device. Fig. 6.6 shows the channel temperature Tch (in kelvin) normalized with respect to the Tch of the bulk-Si device (W = 20 µm), as a function of channel width W, at Vgs = Vds = 2.7 V. Tch was extracted based on a dc measurement method proposed for the LDMOSFET [18]. Significant self-heating in the wide-channel strained-Si device is apparent. Tch rises steeply for W > 0.5 µm and is ~2.4x higher than that of the bulk-Si device. Normalized Channel Temperature Tch / Tch,bulk(W = 20 µm) Chapter Spatial Interface Damage Due to Self-heating 168 (a) 20% Ge 1.4x 2.4x Bulk-Si Vg = Vd = 2.7 V L = 0.18 µm 10 20 30 Width,normalized W (µm) to the Tch of the bulk-Si NFig. 6.6 Channel temperatureChannel Tch (in kelvin), MOSFET of width W = 20 µm. Significant self-heating in the strained-Si device result in a Tch much larger than that of the bulk-Si device. Fig. 6.7 depicts increased Ib/Id for the strained-Si device, as compared to the bulk-Si device. But it should be mentioned that the entire difference may not be ascribed to selfheating; greater contributions from the reduced bandgap [19] and increased electron mobility in the strained-Si layer may be expected. The data for the narrow- and wide-channel strainedSi device suggest a rather weak dependence of Ib/Id on self-heating. Despite a greater (by ~40 %) self-heating in the wide-channel strained-Si device, Ib/Id is increased by only ~10 % relative to the narrow-channel counterpart. This implies that impact ionization in this case is mainly driven by the applied Vds. At Vds = 2.7 V, the average effective temperature of electrons at the drain ~2 x 104 K, much larger than the lattice temperature. Chapter Spatial Interface Damage Due to Self-heating -1 W = 20 µm Impact Ionization Rate, I /I b d 10 169 20% G e 10 -2 B u lk - S i (W = µ m ) .5 µ m V 10 -3 d = .7 V L = .1 µ m G a t e V o lt a g e V g (V ) Fig. 6.7 Impact ionization rate Ib/Id versus gate voltage Vg, showing excess hot-carrier current in the strained-Si device due to self-heating. The Ib/Id of the W = 20 µm and 0.5 µm strained-Si devices are comparable, while the Tch of the latter is ~1.4 x smaller than that of the former. Nevertheless, it remains relevant to examine the impact of the increased Ib/Id of the strained-Si device on the spatial distribution of the interface damage. The ∆Id/Ido characteristics of the narrow-channel strained-Si device in Fig. 6.8 indicates that the greater spread of interface damage observed in the wide-channel strained-Si device is not a direct consequence of an increased Ib/Id. ∆Id/Ido (@ Vgm1) of the narrow-channel strained-Si device though remains larger than that of the bulk-Si counterpart (implying a greater spread in interface damage), it is much smaller than that of the wide-channel counterpart. Given that the Ib/Id of the narrow- and wide-channel strained-Si device are comparable, this observation clearly indicates that the much wider spread of interface damage in the widechannel strained-Si device did not arise directly from an increased Ib/Id. Fractional Degradation of Linear Drain Current, ∆Id/Ido Chapter Spatial Interface Damage Due to Self-heating 170 10 m1 Vg ~ Vto -1 10 m2 Vg = 1.8 V -2 10 Bulk-Si 20% Ge -3 10 -1 10 10 10 Stress Time, t (s) 10 Fig. 6.8 Time dependent fractional degradation of the linear drain current, ∆Id/Ido. The NMOSFETs have drawn channel width of 0.5 µm. Trap generation in the channel of the narrow-width strained-Si devices is reduced as compared to the wide-channel counterpart shown in Fig. 6.1. A lack of direct correlation between Ib/Id and the spread of interface damage implies that the bulk of hot electrons responsible for impact ionization at the drain are not necessarily those that also determine the spatial distribution of the interface damage. The result suggests that the spatial distribution of interface damage is linked to a minor fraction of the hot electrons which are more affected by the actual level of self-heating in the device. Monte-Carlo (MC) simulation has shown that electrons could gain a substantial amount of additional energy through net phonon absorption (Fig. of [20]), extending the tail of the electron energy distribution (EED). Fig. 6.9 shows how an enhancement in the “high-energy tail” (by self-heating) of the EED [21]-[24] increases the spread of the interface damage into the channel. Chapter Spatial Interface Damage Due to Self-heating 171 Fig. 6.9 Schematic illustration of the impact of the high-energy “tail” on the spatial spread of the hot-electron induced oxide damage. Ecrit denotes the critical electron energy for trap generation. Solid lines and denote the respective electron energy distribution (EED) at x = m (middle of the channel) and x = L (drain) for a relatively low lattice temperature. At a relatively low lattice temperature, interface state generation is confined at the drain region (A), where the bulk of the electrons possess energy greater than Ecrit, the critical energy for trap generation. At a higher lattice temperature, the high-energy tail is enhanced as denoted by the dotted lines. In other words, electron population having energy greater than Ecrit is significantly increased at x = m (as well as for points x > m), leading to substantial trap generation in the channel region (B), i.e. trap generation has spread towards the middle of the channel. Based on MC simulation [20], the slope of the “thermal tail” may be expressed as 0.2 x (T/100) eV per 10 decade change in the electron distribution, where T is lattice temperature in kelvin. A 2-fold increase in lattice temperature substantially increases the relative distribution of hot electrons in the tail region having a given energy E. For instance, if the relative distribution of electrons having energy E is 10−10 at T, the corresponding relative Chapter Spatial Interface Damage Due to Self-heating 172 distribution at 2T is orders of magnitude higher. The relative increase is even greater at higher energy E. If Ecrit is the critical energy needed for a hot electron to dissociate a Si-H bond via a single vibrational excitation, a substantial increase in the population of electrons having energy greater than Ecrit at x = m implies a corresponding significant increase in trap generation rate in the channel. Non-localized degradation of the channel caused by selfheating is also apparent in the bulk-Si device at the later stage as shown in Fig. 6.4. Take for instance, the ratio of the peak interface trap density generated near the gate edge to that near the center of channel is smaller at longer stress time. In addition, ∆Id/Ido (@ Vgm1) becomes significantly larger than ∆Id/Ido (@ Vgm2) and reaches ~100% in the later prolonged-stressing stage as shown in Fig. 6.1 and 6.8. This implies a progressive dominance of a non-local degradation effect (due to self-heating) on MOSFET parametric shift, over that of the localized damage at the drain end (due to the conventional hot-electron effect). This is important especially for transistors that function at high ambient temperature, the classical explanation of localized degradation may no longer hold. In the next section, the temperature dependence in particular, the profile of interface state generation in bulk Si and strained-Si will be discussed. 6.3 AC Gate Stress Induced Degradation With the kinetics for channel heating induced interface damage established, it is desirable to maintain consistency of the proposed mechanism in actual circuit operation where the transistor switches between ON and OFF states. In reality, if the time constant for heating is longer than the switching period, there is minimal cooling between transitions. The corresponding rise in device temperature reaches a steady state value that is proportional to the average ON state power. In other words, the longer duration of ON Chapter Spatial Interface Damage Due to Self-heating 173 state with respective to OFF state (ie. duty cycle) for a given frequency, the higher the rise in device temperature as depicted in Fig. 6.10 [27]. Fig. 6.10 Increase in temperature as a function of time with the duty cycle as the parameter. This plot shows temperature reaches steady state if the thermal time constant is Degradation of Linear Current, ∆Id/Ido much greater than clock period. [27] 10 (a) 10 10 (b) m1 Vg ~ Vto m1 Vg ~ Vto -1 m2 Vg =1.8 V m2 Vg =1.8 V -3 -5 10 -4 10 -4 10 10 10 10 10 Effective Stress Time, Tstr(eff) (s) Fig. 6.11 Fractional degradation in linear Id, ∆Id/Ido of (a) bulk-Si and (b) strained-Si NMOSFETs subjected to dc and ac gate stress (varying stress duty cycles Dstr), as a function of effective stress time Tstr(eff) (= t x Dstr). Filled symbol denotes dc stress; unfilled symbol denotes 50% duty cycle stress; cross symbol denotes 10% duty cycle stress. Chapter Spatial Interface Damage Due to Self-heating 174 To verify that the channel heating induced spatial damage would be reduced if the increase in device temperature is smaller at lower duty cycle, a series of ac channel hotelectron stress experiment was subsequently conducted. Fig. 6.11 and 6.12 show the ∆Id/Ido and ∆Icp data obtained from ac gate stress, with the stress duty cycle Dstr as the parameter respectively. For the control device, “universal” degradation curves result when ∆Id/Ido is plotted against the effective stress time Tstr(eff), defined by the actual stress interval t x Dstr. The relatively low stress bias would not result in significant hot-hole injection associated with the pulse transient period [25], which is responsible for the increased ac degradation previously reported. With the selected pulse transition time of 50 ns being much smaller than the smallest stress duty cycle for the given frequency, the overall degradation is dominated by the ON cycle, i.e. Vgs = Vds. However, this is not the case for the strainedSi/SiGe devices. Reduced degradation is apparent with decrease in the stress duty cycle. The reduction is particularly significant for the ∆Id/Ido (@Vgm1 ≈ Vto) and ∆Icp parameters, Shift in Charge Pump Current, ∆Icp (A) confirming the role of device self-heating on the spatial damage. 10 -8 10 -9 10 -10 10 -11 10 -12 20% Ge Control 10 -4 10 -2 10 10 10 Effective Stress Time, Tstr(eff) (s) Fig. 6.12 The corresponding shift in charge pump current, ∆Icp for N-MOSFETs subjected to dc and ac gate stress (varying stress duty cycles Dstr), as a function of effective stress time Tstr(eff) (= t x Dstr). Filled symbol denotes dc stress; unfilled symbol denotes 50% duty cycle stress; cross symbol denotes 10% duty cycle stress. Chapter Spatial Interface Damage Due to Self-heating 175 6.4 Summary Significant generation of hot-electron induced interface states in the channel of the strained-Si N-MOSFET at very short stress interval is observed. An analysis involving the narrow-channel strained-Si device points to an enhancement of the high-energy tail electron population due to self-heating as the primary mechanism behind the severe non-local interface damage in the channel. This mechanism is further supported by the less severe induced damage when the strained-Si devices are subjected to ac stress with different duty cycles. With hindsight, chapter four revealed that the reduced high-energy tail electron injection in strained-Si/SiGe with shorter channel length is related to the dopant profile in the gate-to-drain region. It should, however, be highlighted that electron injection may not be the main reason for the interface state generation in NMOSFET. Instead, it is the process of disassociating Si-H bonds via multi-vibrational excitation of hot-electrons in the channel that caused the interface state generation [26]. Next, it is possible that the high-energy-tail electrons generated via e-e scattering are responsible for the interface damage. The process of e-e scattering occurs when the “hot” electron transfers all its energy to the neighboring “cold” electron. This phenomenon could only happened in area where abundance of “cold” electrons is located such as the heavily doped drain region [29]. Nevertheless, the damage signature observed in strained-Si is widely spread into the channel. Hence, the work of energetic electrons generated via e-e scattering on the oxide interface damage can be ruled out. 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Vg – Vt), increased doping of the drain extension (and hence suppressing the effect of hot- electron induced interface states at the drain on the MOSFET electrical characteristics), non-local degradation in the channel Chapter 6 Spatial Interface Damage Due to Self-heating 176 due to self-heating may ultimately limit the hot- carrier reliability of future scaled MOSFETs In cases when self-heating is very... self-limiting hot- carrier degradation in LDD NMOSFET's by charge pumping measurement,” IEEE Electron Device Lett., vol 18, pp 299-301, Jun 19 97 [15] D S Ang and C H Ling, “A unified model for the self-limiting hot- carrier degradation in LDD n-MOSFET’s,” IEEE Trans Electron Devices, vol 45, pp 149-159, Jan 1998 [16] C Chen and T P Ma, “Direct lateral profiling of hot- carrier- induced oxide charge and interface... Riccobene, “Assessing circuit level impact of self-heating in 0.13µm SOI CMOS,” in Proc SOI Conf., pp 101-102, 2001 [8] K A Jenkins, and K Rim, “Measurement of the self-heating in strained-silicon MOSFETs,” IEEE Electron Device Lett., vol 23, pp 360-362, Jun 2002 [9] S Polonsky, and K A Jenkins, “Time-resolved measurements of self-heating in SOI and strained-silicon MOSFETs using photon emission microscopy,”... heating effects and scaling of sub-0.18 micron CMOS devices,” in Proc Int Electron Devices Meeting Tech Digest, pp 677 -680, 2001 [11] N S Waldron, A J Pitera, M J Lee, E A Fitzgerald, and J A del Alamo, “Impact ionization in strained-Si/SiGe heterostructures,” in Proc Int Electron Devices Meeting Tech Digest, pp 813-816, 2003 [12] T Irisawa, T Numata, N Sugiyama, and S Takagi, “On the origin of increase... Summary Significant generation of hot- electron induced interface states in the channel of the strained-Si N-MOSFET at very short stress interval is observed An analysis involving the narrow-channel strained-Si device points to an enhancement of the high-energy tail electron population due to self-heating as the primary mechanism behind the severe non-local interface damage in the channel This mechanism... the electrical degradation In the next chapter, the impact of high channel temperature on the physical characteristics in strained-Si/SiGe will be discussed Chapter 6 Spatial Interface Damage Due to Self-heating 177 6.5 References [1] P Su, K.-I Goto, T Sugii, and C Hu, “Excess hot- carrier currents in SOI MOSFETs and its implications,” in Proc Int Rel Phys Sym., pp 93- 97, 2002 [2] E Zhao, A Salman,... via a single vibrational excitation, a substantial increase in the population of electrons having energy greater than Ecrit at x = m implies a corresponding significant increase in trap generation rate in the channel Non-localized degradation of the channel caused by selfheating is also apparent in the bulk-Si device at the later stage as shown in Fig 6.4 Take for instance, the ratio of the peak interface... consideration of strained silicon on relaxed silicon-germanium (SiGe) substrate,” in Proc Intl Reliab Phys Symp., pp 403408, 2005 [6] L T Su, J E Chung, D A Antoniadis, K E Goodson, and M I Flik, “Measurement and modeling of self-heating in SOI NMOSFET’s,” IEEE Trans Electron Devices, vol 41, pp 69 -75 , Jan 1994 Chapter 6 Spatial Interface Damage Due to Self-heating [7] 178 S P Sinha, M Pelella, C Tretz,... Takagi, “On the origin of increase in substrate current and impact ionization efficiency in strained-Si n- and pMOSFETs,” IEEE Trans Electron Dev., vol 52, pp 993-998, May 2005 [20] A Abramo, C Fiegna, and F Venturi, Hot carrier effects in short MOSFETs at low voltages,” in Proc Int Electron Devices Meeting Tech Digest, pp 301304, 1995 Chapter 6 Spatial Interface Damage Due to Self-heating [21] 180 D . and modeling of self-heating in SOI NMOSFET’s,” IEEE Trans. Electron Devices, vol. 41, pp. 69 -75 , Jan. 1994. Chapter 6 Spatial Interface Damage Due to Self-heating 178 [7] S. P. Sinha, M hot-electron induced interface states in the channel of the strained-Si N-MOSFET at very short stress interval is observed. An analysis involving the narrow-channel strained-Si device points to. Negative interface trapped charge in the channel results in an increase in the threshold voltage and mobility degradation. This, in turn, increases R ch and decreases I d correspondingly. Interface