Hot carrier mechanisms in advanced NMOS transistors 2

Chapter One Introduction 1.1 Impact of CMOS Technology Scaling on the Hot-Carrier Effect The complementary-metal-oxide-semiconductor (CMOS) technology has been widely accepted as the technology platform for nearly all integrated-circuit (IC) applications. It is the mainstream technology for a wide range of electronic products such as personal computers, mobile phones and home entertainment systems, etc. As a matter of fact, the dimension of the transistor used in this technology has been scaled down relentlessly to enhance the speed and the functionality of the circuit. Generally, transistor scaling could either be implemented by the constant-field or the constantvoltage approach. In the 1980s, the standard power supply voltage in almost all ICs was V. There is little or no market for IC chips using non-standard voltages. As a result, the constant-voltage approach gained popularity. This scaling method, however, posed a major challenge as the electric field increased rapidly resulting in hot-carrier (HC) and oxide reliability problems [1]-[12]. These reliability issues are the result of carriers having kinetic energy higher than the oxide potential barrier (typically > eV). They can get injected and trapped in the oxide, thus degrading the transistor Chapter Introduction performance. As scaling continues beyond 1990s, these concerns would become unmanageable if the power supply voltage had not reduced below the oxide potential barrier. Even though the problem was under control, evidence of the continued existence of HC effect for supply voltage below the oxide potential barrier have rendered strong interest in understanding the reliability physics of the deep submicrometer transistors. Moreover, methods used to strain the silicon (Si) lattice are rapidly gaining wide acceptance as one of the alternatives to extend the CMOS technology roadmap. The reliability physics of the strained-Si technology is, however, not well established. This chapter features some of the important changes in the scaling trend, for example, the reduction in the power supply voltage and the implementation of the new strained-Si technology. Besides a review on the relatively new technology, the associated HC effect in both bulk Si and strained-Si deep submicrometer NMOSFET are also highlighted. For instance, the shift in the worst-case HC degradation in the former and the bandgap induced degradation in the latter. 1.1.1 Bulk Si CMOS Technology Trend In the past decades, integrated circuits built on bulk Si substrates have gone through several major evolutions as illustrated in Fig. 1.1 [13]. Due to inferior gate oxide and poor electrical isolation, the CMOS technology did not take off until mid 1970s [14]. Since then, it has become the main platform for logic applications by virtue of its inherent characteristics such as low standby power dissipation and ease of scaling. The fact that the scaling of CMOS transistors is predictable, a phenomenological observation commonly known as the Moore’s law was introduced to forecast the trend for technology advancement. This law states that the number of transistors should double every 18 months or the gate length should reduce by ~30 % for every technology generation [15]. With the increasing level of integration and huge Chapter Introduction amount of investment, the commitment by the entire industry to maintain this trend is thus apparent. This continual scaling could eventually reap benefits such as speed enhancement, increased system functionality and eventually drives the global economy. ? CMOS BiCMOS NMOS/PMOS BIPOLAR 1950 1960 1970 1980 1990 2000 Fig. 1.1 Evolution of silicon logic device platform [13]. Indeed, the semiconductor industry has been consistently realizing its own projections. Of the numerous trend projections based on Moore’s law, the International Technology Roadmap for Semiconductors (ITRS), started by the Semiconductor Industry Association (SIA) in 1992 has gained wide acceptance as the industry guideline for ULSI technology advancement [16]. The primary objective of this initiative is to keep the semiconductor industry focused, forward-looking and identify potential roadblocks. In recent years, the industry driven by competitive pressure to gain market share has outperformed the technology pace set by this group of experts as exhibited in Fig. 1.2 [17]. For instance, at the technology node of 130 nm and 90 nm, the physical gate length is reduced to ~70 nm and ~50 nm respectively. At the end of this decade, the difference in the physical gate length and the technology node could reach as much as 50 %. It should also be noted that beyond the 0.18 µm node, the scale Chapter Introduction of the physical gate length has entered into the nanometer regime. The challenge of fabricating such gate length lies in a much higher level of integration. Key processes such as selective epitaxy of Si to achieve super steep retrograde channel [18], or preamorphization implantation to form ultra-shallow junction may be adopted to optimize transistor performance [19]. Mircon 10 10 0.5µm 0.35µm Technology 0.25 µm Node 0.18 µm 0.13 µm 90nm 130nm 65nm 45nm 70nm -1 -2 Transistor Physical Gate Length 10 1990 1995 50nm 30nm 15nm 2000 2005 2010 Year Fig. 1.2 Logic technology node and physical gate length as a function of year of introduction [17]. Despite the feasibility of sophisticated processes, there have been reports suggesting that the fundamental limit of scaling is at or near a gate length of 25 nm [20][21]. This may indicate the end of the roadmap for scaling of bulk Si CMOS technology. Again, this finding is being challenged and experimental evidence of transistors with a gate length of nm is being demonstrated recently [22][23]. From the device integration point of view, however, this extreme scaling of transistors might degrade performance, which is contradictory to the objective of the scaling theory. Fig. 1.3 shows the trend of drain current as a function of power supply Chapter Introduction voltage. For gate length larger than 100 nm, drain current improvement is expected according to the scaling theory. In contrast, when the gate length is reduced into the sub-100 nm range, drain current improvement is lost. It is postulated that the direct tunneling leakage between the gate and the source and drain is the cause of this degradation [24]. Hence, introduction of deep sub-100 nm bulk Si transistors into the market remains uncertain if the integration issues are unresolved. This drawback has, however, prompted work to explore other means to provide adequate performance enhancement in new CMOS technology generations. One such approach is to use the strained-Si technology for the next few generations and it will be highlighted in section 1.2. Fig. 1.3 Trend of drain current per unit gate width under the supply voltage specified. All the drive current values are published in [24]. 1.1.2 The Change in CMOS Scaling Approach According to the scaling theory, for every reduction in the transistor size, a corresponding decrease in the power supply voltage is required. This is, however, not apparent in earlier generation of CMOS technologies as depicted in Fig. 1.4 [25]. Due Chapter Introduction to interface compatibility issues between systems and problems associated with noise margin and signal-to-noise ratios, the power supply voltage did not scale at the same pace as the geometric parameters. This in turn led to an increase in the lateral channel field [13][14]. It was then in the early 1990s when this increased field became critical. Issues associated with excessive power dissipation and, in particular, the HC effect had caused the complexity of process integration to increase and therefore the time-tomarket for each new technology generation was lengthened [14]. In view of these limitations, the power supply voltage was subsequently reduced for gate length shorter than 0.35 µm, reverting partially towards the constant-field approach. However, it was cautioned that the lower limit of supply voltage scaling is governed by the value of threshold voltage [13]. The change in this scaling trend has, however, undermined prevalent models used to explain the HC effect in NMOSFETs. In sections 1.1.3 and 1.1.4, the existence of impact ionization and the associated HC mechanisms for supply 10 10 -1 10 2010 -3 10 1970 1980 1990 2000 Channel Length, L (µm) Power Supply Voltage, Vdd (V) voltages above and below the oxide potential barrier will be presented. Year Fig. 1.4 The scaling trend of the power supply voltage Vdd and the gate length L for the past decades [25]. Chapter Introduction 1.1.3 Hot-Carrier Effect in the Bulk Si NMOSFET During the time when the constant voltage scaling method was widely used by the industry, reliability issues such as HC induced device degradation, oxide breakdown, etc. were becoming important [1]-[3]. The general concept of HC effect is depicted in Fig. 1.5. Traditionally, the main driving force is the lateral channel field, which is affected by the various physical parameters and terminal biases. By monitoring the substrate current or the traps created at or near the silicon/silicon dioxide (Si/SiO2) interface, HC effect could be quantified [4][5]. Physical Parameters: L, W, Xox, Xj, Nsub Terminal Bias: Vd, Vg, Vb Channel Field, Em 8 8 Impact Ionization Light Emission Hot-Electron Emission Oxide and Interface Damage Ib Icoll Ig Not Nit Fig. 1.5 Conceptual view of the hot-electron problem [4][5]. Besides, it is known that the distance traveled by the carriers in the channel without any collision or the carriers’ mean free path is proportional to the impact ionization efficiency [5]. Compared to the NMOSFET, the mean free path of holes in the channel and the corresponding impact ionization efficiency are smaller in the Chapter Introduction PMOSFET. As a consequence, HC effect in the NMOSFET is more severe than that in the PMOSFET for deep submicrometer technology [5][6]. Hence, HC reliability of the NMOSFET is discussed in detail. Fig 1.6 is a schematic illustration of HC effect in an NMOSFET biased in the saturation mode [7]. The lateral field gradually increases along the channel, peaking in the pinchoff region near the drain. This maximum field creates two distinct effects: (1) carrier generation (2) and gate oxide damage. When the energy of the electrons is greater than the threshold energy for impact ionization (II), generation of electron-hole pairs occur. Consequently, a hole current Ib is created which, if unchecked, can overload the substrate bias generator. Furthermore, Ib is responsible for the snapback breakdown and CMOS latch-up in the device [8]. Photons emitted by bremsstrahlung radiation generate photocurrent Icoll that may degrade DRAM refresh time and interrupt the functionality of the nearby circuits [9][10]. Electrons which possess kinetic energy in excess of the oxide barrier, are injected into the gate terminal as a gate current Ig [1],[2],[5]. Oxide and interface traps are generated by the interaction of the energetic charge carriers and the gate dielectric, resulting in time-dependent drift of device parameters, and increased parasitic leakage currents [11]. If the trapping is excessive, localized oxide breakdown at the drain region could occur [12]. Chapter Introduction Vg Gate Ig Vd Source Drain N+ N+ Lateral field profile along the channel P-Substrate Isub Fig. 1.6 Schematic diagram for the hot-carrier effect in the NMOSFET. Also shown is the position of the peak lateral electric field within the channel [7]. 1.1.4 Worst Case Degradation In order to provide a realistic projection of transistor HC lifetime, it is crucial to identify the worst case degradation under nominal operating condition. Conventionally, stressing the transistor under maximum substrate current Ibmax (or Vg=0.5Vd) condition would result in the largest device parameters degradation and the shortest extrapolated lifetime under nominal condition. Fig. 1.7 shows transconductance degradation and interface state generation as a function of stress gate voltage [30]. An excellent correlation between substrate current and interface state generation is revealed. The peak in the substrate current also results in the maximum interface state generation. This experimental characteristic has led to different schools of thought in the mechanism of interface state generation by the injection of hot holes and hot electrons [26]-[29]. Chapter Introduction 10 Fig. 1.7 Fractional change in transconductance as a function of stress gate voltage for an NMOSFET. A close correspondence between the interface state generation and the substrate current is observed [30]. In spite of the different proposed kinetics, Heremans et al. had provided a unified explanation subsequently [31]. A critical analysis based on the substrate current model [5], and the use of the charge pumping measurement technique for direct measurement of interface state generation [31], a two distinct slope is obtained as illustrated in Fig. 1.8 [31]. A transition is observed from the steeper slope with a value of ~4.2 eV in the low gate voltage (or high Ib/Id) regime to a gentler slope with a value of ~3.25 V in the high gate voltage (or low Ib/Id) regime. These slopes could be associated with the threshold energies for interface state generation by holes and electrons. The discontinuity in the gradient was interpreted as the existence of a critical channel field, at which the generation of interface states by hot holes is equally Chapter Introduction 42 1.6 References [1] T. H. Ning, P. W. Cook, R. H. Dennard, C. M. Osburn, S. E. Schuster, and, H. N. Yu, “1µm MOSFET VLSI technology. Part IV: Hot-electron design constraints,” IEEE Trans. Electron Devices, vol. 26, pp. 346-353, Apr. 1979. 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[...]... incomplete confinement of electrons in the thin Si thickness and as well as due to increased defect scattering [73][74] Chapter 1 Introduction 24 (a) Ion is improved for a given Ioff (b) Fig 1.17 (a) Effective electron mobility enhancement in strained-Si (b) improvement of Ion-Ioff characteristics in the strained-Si [71] Chapter 1 Introduction 25 NMOS µ eff enhancement 2. 4 2. 2 2. 0 1.8 1.6 1.4 1 .2. .. electrons in the two-fold valley possess a larger effective mass mz = ml =0.916 mo As a result, the strained-Si exhibits a smaller Chapter 1 Introduction 23 effective width of the electron wave function in the inversion layer than that in the bulk Si In other words, a thinner inversion layer is formed in the former [69][70] Reduction in intervalley scattering in the strained-Si, leads to an increase in the... the scaled transistors for a given technology node [4] This performance booster principally works by increasing the lattice spacing or lateral strain in crystalline silicon The methods of straining the Si lattice may be divided into two categories namely global strain [48]-[51] and the process-induced strain [54][55] Global strain may be achieved by incorporating a layer of SiGe below a thin Si film... temperature in the strained-Si and this would be addressed in chapter 5 and 6 (a) (b) Fig 1 .21 Drain current as a function of drain voltage with gate voltage as the parameter for (a) bulk Si (b) strained-Si NMOSFET The apparent reduction of drain current at high drain voltage for strained-Si is attributed to the self-heating effect [ 82] Chapter 1 Introduction 29 1 .2. 4 Process Induced Strain Relaxation... lattice-mismatched interface [ 62] (a) (b) Fig 1.15 (a) schematic illustrating the extension of the threading dislocation towards the relaxed SiGe alloy and (b) the corresponding TEM image before the strained-Si growth [ 62] 1 .2. 2 Current Enhancement in Strained-Si NMOSFET Before embarking on the HC studies of strained-Si/SiGe NMOSFET, it is instructive to understand the reasons behind the improved electrical... the definition of activation energy of HC in strained-Si Lu et al defined the activation energy as the energy in excess of that provided by the supply and it is increased exponentially when the stress voltage is reduced as shown in Fig 1 .27 (a) [101] This finding could render the strained-Si devices operating at nominal operating condition failing in a significantly shorter time than the bulk Si In a... experimentally found to increase with biaxial tensile strain up to a strain level of ~0.8 %, which corresponds to the growth of strained-Si on a layer of SiGe having 20 at % Ge concentration [49][ 72] At the strain level of ~0.8 %, there is sufficient conduction band splitting to fully suppress intervalley scattering, thus any further increase in the strain would result in negligible enhancement in the mobility... energy did increase at lower stress voltage [103] However, the increase is much smaller than that in the earlier work by Lu et al as depicted in Fig 1 .27 (b) [1 02] In general, the lack of understanding in the HC effects in strained-Si is evident, despite the consistency in the enhanced impact ionization efficiency (a) (b) Fig 1 .27 (a) Activation energy as a function of drain stress voltage in strained-Si... strained-Si [91] 1.3 Hot- carrier Degradation in Strained-Si/SiGe NMOSFET Although it is alluring to adopt the strained-Si technology due to the significant drive current enhancement, it is also vital to maintain this improvement over time Besides, the change in the electronic band structure and the presence of an underlying Chapter 1 Introduction 31 SiGe could cause the HC mechanisms in strained-Si to differ... function of the Ge concentration The increase in Ge concentration results in an increase in strain level [96] The line denotes the calculation based on the model in [97] Chapter 1 Introduction 32 Based on a critical analysis of the lucky electron model, the reduction in the bandgap could result in the lowering of threshold energy for impact ionization, hence increasing the impact ionization efficiency . fundamental limit of scaling is at or near a gate length of 25 nm [20 ] [21 ]. This may indicate the end of the roadmap for scaling of bulk Si CMOS technology. Again, this finding is being challenged and. strain in crystalline silicon. The methods of straining the Si lattice may be divided into two categories namely global strain [48]-[51] and the process-induced strain [54][55]. Global strain. injection of carriers into the oxide [ 32] -[33]. Fig. 1.10 Time dependence of the interface trap increment for NMOSFET annealed at 450 ° C for 3 hrs in 100 % H 2 and 100 % D 2 .