Tài liệu tham khảo |
Loại |
Chi tiết |
[1] AbdelfattahMohamedS,AndrewBitar,andVaughnBetz(2015),"Takethehighway:DesignforembeddedNoCsonFPGAs",inProceedingsofthe2015ACM/SIGDAInternational Symposium on Field-Programmable Gate Arrays, pp.98–107 |
Sách, tạp chí |
Tiêu đề: |
Takethehighway:Designfor embeddedNoCs onFPGAs |
Tác giả: |
AbdelfattahMohamedS,AndrewBitar,andVaughnBetz |
Năm: |
2015 |
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[2] AgarwalAnant,JasonMiller,JonathanEastep,DavidWentziaff,andHarshadKasture(2009),"Self-awarecomputing",DTICDocument |
Sách, tạp chí |
Tiêu đề: |
Self-awarecomputing |
Tác giả: |
AgarwalAnant,JasonMiller,JonathanEastep,DavidWentziaff,andHarshadKasture |
Năm: |
2009 |
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[3] Altera"Software".[Online].Available:https://www.altera.com/products/design-software/overview.html |
Sách, tạp chí |
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[4] Attia Brahim, Wissem Chouchene, Abdelkrim Zitouni, Abid Nourdin, and RachedTourki (2010),"Design and implementation of low latency network interface fornetworkonchip",in20105thInternationalDesignandTestWorkshop,pp.37–42 |
Sách, tạp chí |
Tiêu đề: |
Design and implementation of low latency network interfacefornetworkonchip |
Tác giả: |
Attia Brahim, Wissem Chouchene, Abdelkrim Zitouni, Abid Nourdin, and RachedTourki |
Năm: |
2010 |
|
[5] Attia Brahim, Wissem Chouchene, Abdelkrim Zitouni, and Rached Tourki (2011),"Network interface sharing for SoCs based NoC", inCommunications, ComputingandControlApplications (CCCA),2011InternationalConferenceon,pp.1–6 |
Sách, tạp chí |
Tiêu đề: |
Network interface sharing for SoCs based NoC |
Tác giả: |
Attia Brahim, Wissem Chouchene, Abdelkrim Zitouni, and Rached Tourki |
Năm: |
2011 |
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[6] BakloutiMouna, PhMarquet,Jean-Luc Dekeyser,andMohamedAbid(2015),"FPGA-based many-core System-on-Chip design". Microprocess. Microsyst., vol.39,no.4,pp.302–312 |
Sách, tạp chí |
Tiêu đề: |
FPGA-based many-core System-on-Chip design |
Tác giả: |
BakloutiMouna, PhMarquet,Jean-Luc Dekeyser,andMohamedAbid |
Năm: |
2015 |
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[7] Becker Daniel U (2012),"Efficient microarchitecture for network-on-chip routers",2012.StanfordUniversity,2012 |
Sách, tạp chí |
Tiêu đề: |
Efficient microarchitecture for network-on-chiprouters |
Tác giả: |
Becker Daniel U |
Năm: |
2012 |
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[8] BeckerJrgen,MichaelHubner,GerhardHettich,RainerConstapel,JoachimEisenmann,and Jrgen Luka (2007),"Dynamic and partial FPGA exploitation".Proc.IEEE,vol.95,no.2,pp.438–452 |
Sách, tạp chí |
Tiêu đề: |
Dynamic and partial FPGAexploitation |
Tác giả: |
BeckerJrgen,MichaelHubner,GerhardHettich,RainerConstapel,JoachimEisenmann,and Jrgen Luka |
Năm: |
2007 |
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[9] Benini Luca and Giovanni De Micheli (2002),"Networks on chips: a new SoCparadigm".Computer(Long.Beach.Calif).,vol.35,no.1,pp.70–78 |
Sách, tạp chí |
Tiêu đề: |
Networks on chips: a newSoCparadigm |
Tác giả: |
Benini Luca and Giovanni De Micheli |
Năm: |
2002 |
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[10] Carvalho Ewerson, Ney Calazans, and Fernando Moraes (2007),"Heuristics fordynamic task mapping in NoC-based heterogeneous MPSoCs", in18th IEEE/IFIPInternationalWorkshoponRapidSystemPrototyping(RSP‟07),pp.34–40 |
Sách, tạp chí |
Tiêu đề: |
Heuristicsfordynamic task mapping in NoC-based heterogeneous MPSoCs |
Tác giả: |
Carvalho Ewerson, Ney Calazans, and Fernando Moraes |
Năm: |
2007 |
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[11] ChenXuningandLi-ShiuanPeh(2003),"Leakagepowermodelingandoptimization in interconnection networks", inProceedings of the 2003 internationalsymposiumonLowpowerelectronicsanddesign,pp.90–95 |
Sách, tạp chí |
Tiêu đề: |
Leakagepowermodelingandoptimization ininterconnection networks |
Tác giả: |
ChenXuningandLi-ShiuanPeh |
Năm: |
2003 |
|
[12] Chou Chen-Ling and Radu Marculescu (2007),"Incremental run-time applicationmapping for homogeneous NoCs with multiplev o l t a g e l e v e l s ", inProceedings ofthe 5th IEEE/ACM international conference on Hardware/software codesign andsystemsynthesis,pp.161–166 |
Sách, tạp chí |
Tiêu đề: |
Incremental run-timeapplicationmapping for homogeneous NoCs with multiplev o l t a g e l e v e l s |
Tác giả: |
Chou Chen-Ling and Radu Marculescu |
Năm: |
2007 |
|
[13] ChouChen-LingandRaduMarculescu(2008),"User-awaredynamictaskallocation in networks-on-chip", in2008 Design, Automation and Test in Europe,pp.1232–1237 |
Sách, tạp chí |
Tiêu đề: |
User-awaredynamictaskallocation innetworks-on-chip |
Tác giả: |
ChouChen-LingandRaduMarculescu |
Năm: |
2008 |
|
[14] Chou Chen Ling, Umit Y. Ogras, and Radu Marculescu (2008),"Energy- andperformance-awareincrementalmappingfornetworksonchipwithm u l t i p l e voltage levels".IEEE Trans. Comput. Des. Integr. Circuits Syst., vol. 27, no. 10, pp.1866–1879 |
Sách, tạp chí |
Tiêu đề: |
Energy-andperformance-awareincrementalmappingfornetworksonchipwithm u l t i p l e voltage levels |
Tác giả: |
Chou Chen Ling, Umit Y. Ogras, and Radu Marculescu |
Năm: |
2008 |
|
[17] Chu Pong P (2011),FPGA prototyping by Verilog examples: Xilinx Spartan- 3version.JohnWiley&Sons |
Sách, tạp chí |
Tiêu đề: |
FPGA prototyping by Verilog examples: Xilinx Spartan-3version |
Tác giả: |
Chu Pong P |
Năm: |
2011 |
|
[18] Compton Katherine and Scott Hauck (2002),"Reconfigurable computing: a surveyofsystemsandsoftware".ACMComput.Surv.,vol.34,no.2,pp.171–210 |
Sách, tạp chí |
Tiêu đề: |
Reconfigurable computing: asurveyofsystemsandsoftware |
Tác giả: |
Compton Katherine and Scott Hauck |
Năm: |
2002 |
|
[19] Dally William J (1990),"Performance analysis of k-ary n-cube interconnectionnetworks".IEEE Trans.Comput.,vol.39,no.6,pp.775–785 |
Sách, tạp chí |
Tiêu đề: |
Performance analysis of k-ary n-cubeinterconnectionnetworks |
Tác giả: |
Dally William J |
Năm: |
1990 |
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[20] DallyWilliamJ(1992),"Virtual-channelflowcontrol".IEEETrans.ParallelDistrib.Syst.,vol.3,no.2,pp.194–205 |
Sách, tạp chí |
Tiêu đề: |
Virtual-channelflowcontrol |
Tác giả: |
DallyWilliamJ |
Năm: |
1992 |
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[21] Dally William J and Charles L Seitz (1987),"Deadlock-free message routing inmultiprocessor interconnectionnetworks". IEEETrans. Comput.,vol.100, no.5 , pp.547–553 |
Sách, tạp chí |
Tiêu đề: |
Deadlock-free message routinginmultiprocessor interconnectionnetworks |
Tác giả: |
Dally William J and Charles L Seitz |
Năm: |
1987 |
|
[22] Dally William J and Brian Towles (2001),"Route packets, not wires: on- chipinterconnection networks", inDesign Automation Conference, 2001.Proceedings,pp.684–689 |
Sách, tạp chí |
Tiêu đề: |
Route packets, not wires: on-chipinterconnection networks |
Tác giả: |
Dally William J and Brian Towles |
Năm: |
2001 |
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