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International Journal of Research In Vocational Studies (IJRVOCAS) VOL 1, NO 4, April 2022, PP 66~70 Print ISSN 2777 0168| Online ISSN 2777 0141| DOI prefix 10 53893 https //journal gpp or id/index ph[.]
International Journal of Research In Vocational Studies (IJRVOCAS) VOL 1, NO 4, April 2022, PP 66~70 Print ISSN 2777-0168| Online ISSN 2777-0141| DOI prefix: 10.53893 https://journal.gpp.or.id/index.php/ijrvocas/index Design IIR Filter on FPGA Technology Combined with Matlab-Simulink Software Tools and Electronic Design Automation Software Hong Ngan Vo1, Xuan Toai Nguyen1, Thanh Lanh Le1, Nam Thoi Le1 1Dong Nai Technology University, Viet Nam Email address: vohongngan@dntu.edu.vn; nguyenxuantoai@dntu.edu.vn; lethanhlanh@dntu.edu.vn; lenamthoi09@gmail.com To cite this article: Author’s Name Paper Title International https://doi.org/10.53893/ijrvocas.v1iX.XX Journal of Research in Vocational Studies (IJRVOCAS), X(X), XX–XX Received: Dec 08, 2021; Accepted: Dec 16, 2021; Published: Feb 19, 2022 Abstract: This paper presents the design of an IIR filter on FPGA technology by combining modeling with automation of digital system design, in order to provide a solution to design and quickly implement the digital signal processing system The IIR filter is designed by the method of object modeling (Model Based Design) abbreviated as MBD with the help of Matlab and EDA, then experimentally implemented the IIR filter on FPGA technology for a specific problem and achieved quite good results Through this method, it has helped designers reduce design effort and time, improve economic efficiency, and more importantly, the design is highly flexible, ready to response the new technical requirements of the technology Keywords: IIR Filter, EDA, FPGA, Matlab, MBD Introduction Currently Altera is known for its FPGA, CPLD and ASIC their software to convert from hard designs into VHDL architectures that allow programming on it With a growing languages applied to FPGA and CPLD technologies including number of customers, Altera's 2006 sales were 1.29 billion Matlab, Multiplex sim, Altium Designer, Modelsim, [1-4] USD Altera's headquarters is located in San Jonse, California with a staff of approximately 2,600 employees in companies in 19 countries In the early 2000s, in technical journals, articles about a new design idea for FPGAs and CPLDs began to appear, which were later called "Model Based Design" as the article An FPGA consists of an array of discrete elements that by Professor: Uwe Meyer_Baese, Ph.D by the University of can be interconnected in a common way, and like a PLD, the Florida or by Stranneby and William Walker etc This design connections between the elements are programmable That method brings high economic efficiency Up to now, almost all leads designers to write programs in functional blocks application designs have followed this method [5-8] Because of this idea, software vendors have begun to allow Quartus is Altera's software development tool that provides a comprehensive design environment for SOPC and after The IIR filter has low amplitude attenuation, the (system on a programmable chip) designs [9] This is a fully structure is much simpler than the FIR filter integrated package software for logic design with Altera's PLD In this paper, the Chebyshev-type2 IIR filter [15] will be programmable logic components, including APEX, Cyclone, designed with the structure shown in Figure with selected FLEX, MAX, Stratix Quartus helps designers almost all the parameters most necessary tools to be able to complete a design project in the fastest and most efficient way Quartus integrates the most advanced technologies with flexibility, user-friendly GUI interface During this period, FPGA and CPLD played a very important role in digital system processing, which was the basis for digital electronic devices It has a strong impact on fields from Electronics and Telecommunications to Information Technology, National Security and Defense, etc and it will certainly contribute significantly to the industrialization and modernization of our country This paper presents an IIR filter design with the desire to provide a product designed on FPGA technology for Figure Schematic diagram of the Chebyshev-type2 filter First, we will create a filter block Filter_Cheb2 with the following input parameters for the filter: multiplier, input and output data parameters, register structure, and arithmetic algorithm for the filter convenience, with the shortest time and the highest economic efficiency A modeled and measured audio noise filter gives good results Objects and Methods We know that the spectrum of human voice has energy concentrated in the frequency range from 0.8Khz to 1.7Khz to be able to clearly recognize each person's voice, then the standard telephone bandwidth is from 0.3Khz to 3.4 Khz Suppose for some reason that the audio frequency signal (human voice) during this recording process is penetrated by high-frequency noise, reducing the sound quality, causing the terminal device (of the communication system to) no longer recognizes the original signal form And the noise energy is scattered in the frequency range from 10Khz to 100Khz The task is to design a filter to remove the above noise from the signal source to ensure the best output signal quality In order to reduce or enhance a certain frequency range of the signal, we often use a filter Digital filtering is classified into two types FIR (Finite Impulse Response) and IIR (Infinite Impulse Response) [10-12] The IIR filter works recursively, using past values of the output [13-14] That way, we can implement a filter that needs only low order but the passband has the same slopes before Figure Input and output data for the filter and Simulink simulation block for the filter after creation In Simulink's environment, we set up the simulation Figure Waveform of the test points in the system block as follows: Sin signal and noise generator block, filter Waveform 1: Sine signal; Waveform 2: Noise signal; block as well as display block as shown in the following Waveform 3: Sum of the Sin signal + noise; Waveform 4: figure: Sine signal after filter Thus, we see that the waveform after passing the filter meets the necessary requirements such as less signal attenuation, the signal after filtering compared to the signal before filtering is equivalent Although the Chebyshev_2 filter Figure Setting up the simulation system in Simulink The specifications of the Sin generator and the noise generator are shown in the following figure: is phase-delayed, it is still acceptable Looking at the output signal form compared to the input signal form of the filter, we see that the output signal completely responses the technical requirements that have been set out for the filter Thus, this filter can be introduced to realize in FPGA At this point, you can load it directly on the DE2 board for testing or use the simulation program available on Quartus II Looking at the test results, we can see that the filter can be realized by the diagram of the FPGA just created Switching from the VHDL language to the principle circuit from the Figure Setting the sine wave and noise block parameters In the Simulink environment we run the simulation Altium Designer Winter 09 software tool, we get the schematic diagram of the filter principle as follows: Simulation results are displayed in Scope, the waveform is shown from the bottom up as follows: Figure Principle circuit diagram created from Altium software tool Below is a block diagram of the process of measuring and checking IIR filters on FPGA technology Audio and noise signals are generated at the transmitter It is then converted to Figure Generatosaur software interface a digital signal by an ADC converter At the output filter_out Use a circuit to combine signals and noise Then put (FPGA) we connect to the DAC converter, the signal after the it into the 12bit ADC of the dsPIC33FJ128GP802 microcontroller, then output the port to the FPGA, the FPGA DAC is checked by an oscilloscope filters the output signal with the IIR filter designed above, then give the port of the FPGA From here, put into another port of the PIC, use the DAC (16bit) to generate analog signals The actual experimental circuit has the following Figure Digital filter implementation block diagram parameters: 12-bit ADC with a maximum sampling frequency of 500Khz equal to times the frequency of the signal The Results and Discussion signal wave to be filtered is limited to about 100Khz or less The IIR filter on FPGA technology is modeled as shown in Figure Using the computer output to generate a sine wave (fluctuates in the range of 100Khz or less), then using Generatosaur software to generate white noise as shown in Figure Input selection Output white noise (White noise) is left (LEFT), output right (RIGHT) is sine wave (Sinus) by selecting Active frequency f(Hz) change according to requirements The 16-bit output DAC has a maximum output sample rate of 100Khz, just enough for the input 100Khz signal Mixed waves with amplitudes from to 3V3 The signal obtained after passing through the Chebyshev-type2 IIR filter as shown in Figure 10 has eliminated noise quite well However, the signal is not smooth and has a small bump Figure 10 Waveform at filter output Figure Filter test model Conclusion An IIR filter design on FPGA technology was modeled with the help of Matlab and EDA for a specific problem and achieved quite good results With the desire to offer a product designed on FPGA technology so that it is convenient, with the shortest time and the highest economic efficiency A problem of IIR filters in general as well as digital filters in particular is that the better the quality of the signal filter, the more signal degradation will be However, the signal quality of the digital filter is much better than that of the analog filter In order to have good digital filter quality and the least signal loss, we can use an amplifier, in addition, both signal and noise implementation of FIR and IIR digital filters with must be accurately determined in terms of amplitude and variable frequency characteristics." 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Bell System Technical Journal 53.2 (1974): 305-331 [12] Pun, Carson KS, et al "On the design and [15] Filter, Low-Pass "Analog Filters." Signals and Systems (2018): 227 ... at filter output Figure Filter test model Conclusion An IIR filter design on FPGA technology was modeled with the help of Matlab and EDA for a specific problem and achieved quite good results With. .. electronic devices It has a strong impact on fields from Electronics and Telecommunications to Information Technology, National Security and Defense, etc and it will certainly contribute significantly... implement a filter that needs only low order but the passband has the same slopes before Figure Input and output data for the filter and Simulink simulation block for the filter after creation In Simulink'' s