5 JE40 HR DIS/UMA/Muxless Schematics Document Sandy Bridge Intel PCH D D C C ANNIE: ONLY FOR ANNIE solution PSL: KBC795 PSL circuit for 10mW solution installed 10mW: External circuit for 10mW solution installed 65W: for 65W adaptor installed 90W: for 90W adaptor installed B DY :None Installed DIS:DIS installed DIS_Muxless :BOTH DIS or Muxless installed DIS_PX:BOTH DIS or PX installed DIS_PX_Muxless:DIS or PX or Muxless installed Muxless: Muxless installed.(PX4.0) PX:MUX installed.(PX3.0) PX_Muxless:BOTH PX or Muxless installed UMA:UMA installed UMA_Muxless:BOTH UMA or Muxless installed UMA_PX_Muxless:UMA or PX or Muxless installed B HR UMA A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Cover Page Size A3 Date: Document Number JE40-HR Thursday, December 02, 2010 Rev -1 Sheet 1 of 102 A JE40 HR Block Diagram (Discrete/UMA/co-lay) ##OnMainBoard VRAM 2GB/1GB/512MB D Intel CPU DDRIII 1066/1333 Channel B (Discrete only) OUTPUTS INPUTS OUTPUTS 1D05V_PWR 0D85V_S0 DCBATOUT VCC_CORE SYSTEM DC/DC 45 UP6128PQDD INPUTS OUTPUTS DCBATOUT 1D05V_VTT D SYSTEM DC/DC 41 UP6183PQAG OUTPUTS DCBATOUT DDRIII Slot 15 1066/1333 5V_AUX_S5 3D3V_AUX_S5 5V_S5 3D3V_S5 SYSTEM DC/DC 46 UP6165BQKF INPUTS USB3.0 PCIE x USB x 4,5,6,7,8,9,10,11,12,13 83.84,85,86,87 42~43 INPUTS DDRIII Slot 14 1066/1333 Sandy Bridge FSB: 1066 MHz PCIe x 16 NCP6131S52MNR INPUTS DDRIII 1066/1333 Channel A Nvidia N12P CPU DC/DC 48 APL5916KAI Project code : 91.4IQ01.001 PCB P/N : 48.4IQ01.0SA Revision : 10267-1 88,89,90,91 DDR3 800MHz SYSTEM DC/DC OUTPUTS DCBATOUT uPD720200 1D5V_S3 0D75V_S0 DDR_VREF_S3 75 Discreet/UMA/PX Co-lay SYSTEM DC/DC FDIx4x2 (UMA only) C PCIE x USB x DMIx4 INPUTS HDMI 51 Level 57 shifter LVDS(Dual Channel) LCD 49 RGB CRT 1000 NIC PCH Cougar Point INPUTS 26 WWAN 66 3D3V_S0 1D8V_S0 B Flash ROM 4MB 60 ALC271X SATA x LPC Bus Azalia CODEC 56 LPC debug port ODD 71 INPUTS OUTPUTS 1D5V_S3 1V_VGA_S0 3D3V_S5 1D8V_VGA_S0 OUTPUTS 1D5V_S3 1D5V_VGA_S0 3D3V_S0 3D3V_VGA_S0 PCB LAYER 56 L1:Top L4:Signal L2:VCC L5:GND L3:Signal L6:Bottom SMBus 29 26 INPUTS HDD KBC NUVOTON A 93 RT9025-25PSP Right Side: USB x Switches SPI AZALIA 64 MIC IN SIM 49 Internal Analog MIC 47 OUTPUTS SYSTEM DC/DC USB 2.0 x HP1 66 USB2.0 x 17,18,19,20,21,22,23,24,25,26 CAMERA SYSTEM DC/DC INPUTS Mini-Card PCIE x 1,USB x LPC I/F 63 BT+ RT9025 PCIE ports (8) ACPI 1.1 Bluetooth OUTPUTS DCBATOUT SATA ports (6) B 40 BQ24745RHDR INPUTS High Definition Audio Left Side: USB x VGA_CORE TI CHARGER ETHERNET (10/100/1000Mb) 50 OUTPUTS DCBATOUT SD/MMC+/MS/ MS Pro/xD 14 USB 2.0/1.1 ports CRT 92 RT8208BGQW BCM57780A1 31 VCC_GFXCORE_PWR VGA RJ45 CONN 59 PCIE x Intel C OUTPUTS DCBATOUT HDMI 44 NCP5911MNTBG Mini-Card 802.11a/b/g 65 HR UMA NPCE795P A 27 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C 2CH SPEAKER Touch PAD 69 Title Thermal Int KB ENE P2800 ENE P2793 69 Block Diagram Fan Size A3 28 2528 Document Number Rev -1 JE40-HR Date: Thursday, December 02, 2010 Sheet of 102 A PCH Strapping Name SPKR B C Processor Strapping Huron River Schematic Checklist Rev.0_7 Schematics Notes Reboot option at power-up Default Mode: Internal weak Pull-down No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-kȍ - 10-kȍ weak pull-up resistor INIT3_3V# Weak internal pull-up Leave as "No Connect" GNT3#/GPIO55 GNT2#/GPIO53 GNT1#/GPIO51 GNT[3:0]# functionality is not available on Mobile Mobile: Used as GPIO only Pull-up resistors are not required on these signals If pull-ups are used, they should be tied to the Vcc3_3power rail Strap Description Configuration (Default value for each bit is unless specified otherwise) CFG[2] PCI-Express Static Lane Reversal 1: 0: CFG[6:5] CFG[7] PEG DEFER TRAINING 1: PEG Train immediately following xxRESETB de assertion1 0: PEG Wait for BIOS for training POWER PLANE VOLTAGE 5V_S0 3D3V_S0 1D8V_S0 1D5V_S0 1D05V_VTT 0D85V_S0 0D75V_S0 VCC_CORE VCC_GFXCORE 1D8V_VGA_S0 3D3V_VGA_S0 1V_VGA_S0 5V 3.3V 1.8V 1.5V 1.05V 0.95 - 0.85V 0.75V 0.35V to 1.5V 0.4 to 1.25V 1.8V 3.3V 1V 5V_USBX_S3 1D5V_S3 DDR_VREF_S3 5V 1.5V 0.75V BT+ DCBATOUT 5V_S5 5V_AUX_S5 3D3V_S5 3D3V_AUX_S5 6V-14.1V 6V-14.1V 5V 5V 3.3V 3.3V 3D3V_LAN_S5 3.3V WOL_EN Legacy WOL 3D3V_AUX_KBC 3.3V DSW, Sx ON for supporting Deep Sleep states 3D3V_AUX_S5 3.3V G3, Sx Powered by Li Coin Cell in G3 and +V3ALW in Sx Disable Danbury:Leave floating (internal pull-down) Low (0) - Flash Descriptor Security will be overridden Also, when this signals is sampled on the rising edge of PWROK then it will also disable Intel ME and its features High (1) - Security measure defined in the Flash Descriptor will be enabled Platform design should provide appropriate pull-up or pull-down depending on the desired settings If a jumper option is used to tie this signal to GND as required by the functional strap, the signal should be pulled low through a weak pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently Note: CRB recommends 1-kohm pull-down for FD Override There is an internal pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for strapping functions HDA_SDO Weak internal pull-down Do not pull high Sampled at rising edge of RSMRST# HDA_SYNC Weak internal pull-down Do not pull high Sampled at rising edge of RSMRST# GPIO8 GPIO27 11 DMI termination voltage Weak internal pull-up Do not pull low HAD_DOCK_EN# /GPIO[33] GPIO15 11 : x16 - Device functions and disabled 10 : x8, x8 - Device function enabled ; function disabled 01 : Reserved - (Device function disabled ; function enabled) 00 : x8, x4, x4 - Device functions and enabled Disable Danbury:Left floating, no pull-down required 15 -> 0, 14 -> 1, PCI-Express Port Bifurcation Straps Enable Danbury: Connect to Vcc3_3 with 8.2-k? weak pull-up resistor NC_CLE Normal Operation Lane Numbers Reversed Default Value Disabled - No Physical Display Port attached to 1: Embedded DisplayPort Enabled - An external Display Port device is 0: connectd to the EMBEDDED display Port SPI_MOSI NV_ALE E Pin Name CFG[4] Enable Danbury: Connect to +NVRAM_VCCQ with 8.2-kohm weak pull-up resistor [CRB has it pulled up with 1-kohm no-stuff resistor] D Huron River Schematic Checklist Rev.0_7 Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality Note : This is an un-muxed signal This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low Sampled at rising edge of RSMRST# CRB has a 1-kohm pull-up on this signal to +3.3VA rail GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down using a 1k +/- 5% resistor When this signal is sampled high at the rising edge of RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is enabled Default = Do not connect (floating) High(1) = Enables the internal VccVRM to have a clean supply for analog rails No need to use on-board filter circuit Low (0) = Disables the VccVRM Need to use on-board filter circuits for analog rails Voltage Rails DESCRIPTION ACTIVE IN S0 CPU Core Rail Graphics Core Rail S3 AC Brick Mode only All S states USB Table Pair PCIE Routing LANE1 Mini Card2(WWAN) LANE2 Mini Card1(WLAN)SATA LANE3 Card Reader LANE4 Onboard LAN LANE5 USB3.0 LANE6 Intel GBE LAN LANE7 Dock LANE8 New Card Table SATA Pair Device Device SMBus ADDRESSES Touch Panel / 3G SIM USB Ext port (HS) I C / SMBus Addresses Fingerprint Device BLUETOOTH Mini Card2 (WWAN) CARD READER X X HDD1 USB Ext port / E-SATA /USB CHARGER HDD2 USB Ext port 2 N/A 10 EDP CAMERA N/A 11 Mini Card1 (WLAN) ODD 12 CAMERA ESATA 13 New Card Ref Des HURON RIVER ORB Address Hex Bus EC SMBus Battery CHARGER BAT_SCL/BAT_SDA BAT_SCL/BAT_SDA BAT_SCL/BAT_SDA EC SMBus PCH eDP SML1_CLK/SML1_DATA SML1_CLK/SML1_DATA SML1_CLK/SML1_DATA PCH SMBus SO-DIMMA (SPD) SO-DIMMB (SPD) Digital Pot G-Sensor MINI HR UMA PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK Title PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK Size A3 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Table of Content Document Number Rev -1 JE40-HR Date: Thursday, December 02, 2010 Sheet of 102 SSID = CPU CPU1A SANDY Signal Routing Guideline: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils 62.10055.421 Change:62.10053.611 2nd = 62.10055.321 3rd = 62.10040.821 1D05V_VTT OF 19 DMI_RXP[3:0] 19 FDI_TXN[7:0] 1D05V_VTT B B28 B26 A24 B23 DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 G21 E22 F21 D21 DMI_TX#0 DMI_TX#1 DMI_TX#2 DMI_TX#3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 G22 D22 F20 C21 DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3 A21 H19 E19 F18 B21 C20 D18 E17 FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7 A22 G19 E20 G18 B20 C19 D19 F17 FDI0_TX0 FDI0_TX1 FDI0_TX2 FDI0_TX3 FDI1_TX0 FDI1_TX1 FDI1_TX2 FDI1_TX3 19 FDI_FSYNC0 19 FDI_FSYNC1 J18 J17 FDI0_FSYNC FDI1_FSYNC 19 FDI_INT H20 FDI_INT 19 FDI_LSYNC0 19 FDI_LSYNC1 J19 H17 FDI0_LSYNC FDI1_LSYNC A18 A17 B16 EDP_COMPIO EDP_ICOMPO EDP_HPD C15 D15 EDP_AUX EDP_AUX# C17 F16 C16 G15 EDP_TX0 EDP_TX1 EDP_TX2 EDP_TX3 C18 E16 D16 F15 EDP_TX#0 EDP_TX#1 EDP_TX#2 EDP_TX#3 19 FDI_TXP[7:0] Note: Lane reversal does not apply to FDI sideband signals DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7 Note: Intel FDI supports both Lane Reversal and polarity inversion but only at PCH side This is enabled via a soft strap C DMI_RX#0 DMI_RX#1 DMI_RX#2 DMI_RX#3 R402 24D9R2F-L-GP DP_COMP R403 10KR2J-3-GP eDP_HPD Signal Routing Guideline: EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils JE40 delete eDP function NOTE Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort Stuff to disable internal graphics function for power saving FDI_LSYNC0 FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC1 FDI_INT FDI0_TX#0 FDI0_TX#1 FDI0_TX#2 FDI0_TX#3 FDI1_TX#0 FDI1_TX#1 FDI1_TX#2 FDI1_TX#3 PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15 K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32 PEG_RXN15 PEG_RXN14 PEG_RXN13 PEG_RXN12 PEG_RXN11 PEG_RXN10 PEG_RXN9 PEG_RXN8 PEG_RXN7 PEG_RXN6 PEG_RXN5 PEG_RXN4 PEG_RXN3 PEG_RXN2 PEG_RXN1 PEG_RXN0 PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15 J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32 PEG_RXP15 PEG_RXP14 PEG_RXP13 PEG_RXP12 PEG_RXP11 PEG_RXP10 PEG_RXP9 PEG_RXP8 PEG_RXP7 PEG_RXP6 PEG_RXP5 PEG_RXP4 PEG_RXP3 PEG_RXP2 PEG_RXP1 PEG_RXP0 PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9 PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15 M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25 PEG_C_TXN15 PEG_C_TXN14 PEG_C_TXN13 PEG_C_TXN12 PEG_C_TXN11 PEG_C_TXN10 PEG_C_TXN9 PEG_C_TXN8 PEG_C_TXN7 PEG_C_TXN6 PEG_C_TXN5 PEG_C_TXN4 PEG_C_TXN3 PEG_C_TXN2 PEG_C_TXN1 PEG_C_TXN0 C401 C402 C403 C404 C405 C406 C407 C408 C409 C410 C411 C412 C413 C414 C415 C416 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff PEG_TXN15 PEG_TXN14 PEG_TXN13 PEG_TXN12 PEG_TXN11 PEG_TXN10 PEG_TXN9 PEG_TXN8 PEG_TXN7 PEG_TXN6 PEG_TXN5 PEG_TXN4 PEG_TXN3 PEG_TXN2 PEG_TXN1 PEG_TXN0 PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8 PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15 M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25 PEG_C_TXP15 PEG_C_TXP14 PEG_C_TXP13 PEG_C_TXP12 PEG_C_TXP11 PEG_C_TXP10 PEG_C_TXP9 PEG_C_TXP8 PEG_C_TXP7 PEG_C_TXP6 PEG_C_TXP5 PEG_C_TXP4 PEG_C_TXP3 PEG_C_TXP2 PEG_C_TXP1 PEG_C_TXP0 C417 C418 C419 C420 C421 C422 C423 C424 C425 C426 C427 C428 C429 C430 C431 C432 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless 1DIS_PX_Muxless Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff PEG_TXP15 PEG_TXP14 PEG_TXP13 PEG_TXP12 PEG_TXP11 PEG_TXP10 PEG_TXP9 PEG_TXP8 PEG_TXP7 PEG_TXP6 PEG_TXP5 PEG_TXP4 PEG_TXP3 PEG_TXP2 PEG_TXP1 PEG_TXP0 PCI EXPRESS* - GRAPHICS 19 DMI_RXN[3:0] B27 B25 A25 B24 PEG_IRCOMP_R DMI 19 DMI_TXP[3:0] SANDY DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 Intel(R) FDI 19 DMI_TXN[3:0] J22 J21 H22 eDP Note: Intel DMI supports both Lane Reversal and polarity inversion but only at PCH side This is enabled via a soft strap D PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO R401 24D9R2F-L-GP D PEG_RXN[0 15] 83 PEG_RXP[0 15] 83 C NOTE If PEG is not implemented, the RX&TX pairs can be left as No Connect PEG Static Lane Reversal PEG_TXN[0 15] 83 PEG_TXP[0 15] 83 B 20100614 V1.1 NOTE: Select a Fast FET similar to 2N7002E whose rise/ fall time is less than ns If HPD on eDP interface is disabled, connect it to CPU VCCIO via a 10-kȍ pull-Up resistor on the motherboard A HR UMA R404 Do Not Stuff DIS RN401 Do Not Stuff Wistron Corporation DIS 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C 2 A Title CPU (PCIE/DMI/FDI) Size A3 Document Number Rev -1 JE40-HR Date: Thursday, December 02, 2010 Sheet of 102 SSID = CPU CPU1B SANDY 2 OF D JE40 modify 1D05V_VTT SKTOCC# H_PROCHOT# JE40 modify AL33 CATERR# AN33 PECI AL32 PROCHOT# AN32 THERMTRIP# C502 SC47P50V2JN-3GP 22,27 CRB : 47pf CEKLT:43pf 27,42 H_PROCHOT# H_PECI R513 H_PROCHOT#_R 56R2J-4-GP Connect EC to PROCHOT# through inverting OD buffer 22,36 H_THERMTRIP# THERMAL R501 62R2J-GP 1 AN34 SNB_IVB# CLOCKS C26 H_SNB_IVB# BCLK BCLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# SM_DRAMRST# DDR3 MISC 18 MISC SANDY SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 AP33 UNCOREPWRGOOD R503 10KR2J-3-GP 22,36,97 H_CPUPWRGD 19,37 PM_DRAM_PWRGD DY R505 Do Not Stuff V8 SM_DRAMPWROK 37 VDDPWRGOOD B BUF_CPU_RST# XDP_DBRESET# 18,27,31,36,65,66,71,82,97 PLT_RST# AR33 RESET# JTAG & BPM PM_SYNC PWR MANAGEMENT AM34 A16 A15 CLK_EXP_P CLK_EXP_N 20 20 CLK_DP_P_R CLK_DP_N_R RN502 Do Not Stuff DIS R502 4K99R2F-L-GP R8 AK1 A5 A4 SM_RCOMP_0 R506 SM_RCOMP_1 R507 SM_RCOMP_2 R508 JE40 modify 1D05V_VTT Disabling Guidelines: If motherboard only supports external graphics: Connect DPLL_REF_SSCLK on Processor to GND through 1K +/- 5% resistor Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K +/- 5% resistorpower (~15 mW) may be wasted D SM_DRAMRST# 37 140R2F-GP 25D5R2F-GP 200R2F-L-GP Signal Routing Guideline: SM_RCOMP keep routing length less than 500 mils C 19 H_PM_SYNC A28 A27 PRDY# PREQ# AP29 AP27 TCK TMS TRST# AR26 AR27 AP30 XDP_TRST# TDI TDO AR28 AP26 XDP_TDO DBR# AL35 XDP_DBRESET# BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7 AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32 C JE40 modify 1D05V_VTT XDP_TDO XDP_TRST# RN501 SRN51J-GP B JE40 modify 3D3V_S0 RN503 SRN1K5J-1-GP BUF_CPU_RST# HR UMA Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C A Title Size Custom Document Number Rev -1 JE40-HR Date: Thursday, December 02, 2010 A CPU (THERMAL/CLOCK/PM ) Sheet of 102 SSID = CPU OF OF CPU1D 14 M_A_DQ[63:0] M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 D C B 14 14 14 M_A_BS0 M_A_BS1 M_A_BS2 14 14 14 M_A_CAS# M_A_RAS# M_A_WE# C5 D5 D3 D2 D6 C6 C2 C3 F10 F8 G10 G9 F9 F7 G8 G7 K4 K5 K1 J1 J5 J4 J2 K2 M8 N10 N8 N7 M10 M9 N9 M7 AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8 AP11 AN11 AL12 AM12 AM11 AL11 AP12 AN12 AJ14 AH14 AL15 AK15 AL14 AK14 AJ15 AH15 SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63 AE10 AF10 V6 SA_BS0 SA_BS1 SA_BS2 AE8 AD9 AF9 DDR SYSTEM MEMORY A SANDY SA_CAS# SA_RAS# SA_WE# SANDY SA_CLK0 SA_CLK#0 SA_CKE0 AB6 AA6 V9 SA_CLK1 SA_CLK#1 SA_CKE1 AA5 AB5 V10 SA_CLK2 SA_CLK#2 SA_CKE2 AB4 AA4 W9 SA_CLK3 SA_CLK#3 SA_CKE3 AB3 AA3 W10 SA_CS#0 SA_CS#1 SA_CS#2 SA_CS#3 AK3 AL3 AG1 AH1 M_A_DIM0_CS#0 14 M_A_DIM0_CS#1 14 SA_ODT0 SA_ODT1 SA_ODT2 SA_ODT3 AH3 AG3 AG2 AH2 M_A_DIM0_ODT0 14 M_A_DIM0_ODT1 14 M_A_DIM0_CLK_DDR0 14 M_A_DIM0_CLK_DDR#0 14 M_A_DIM0_CKE0 14 15 M_B_DQ[63:0] M_A_DIM0_CLK_DDR1 14 M_A_DIM0_CLK_DDR#1 14 M_A_DIM0_CKE1 14 SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7 C4 G6 J3 M6 AL6 AM8 AR12 AM15 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7 D4 F6 K3 N6 AL5 AM9 AR11 AM14 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15 AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 M_A_DQS#[7:0] 14 M_A_DQS[7:0] 14 M_A_A[15:0] 14 SANDY 15 15 15 M_B_BS0 M_B_BS1 M_B_BS2 15 15 15 M_B_CAS# M_B_RAS# M_B_WE# M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 C9 A7 D10 C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2 J7 J8 K10 K9 J9 J10 K8 K7 M5 N4 N2 N1 M4 N5 M2 M1 AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9 AJ11 AT8 AT9 AH11 AR8 AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15 AA9 AA7 R6 AA10 AB8 AB9 SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63 DDR SYSTEM MEMORY B CPU1C SB_CLK0 SB_CLK#0 SB_CKE0 AE2 AD2 R9 SB_CLK1 SB_CLK#1 SB_CKE1 AE1 AD1 R10 SB_CLK2 SB_CLK#2 SB_CKE2 AB2 AA2 T9 SB_CLK3 SB_CLK#3 SB_CKE3 AA1 AB1 T10 SB_CS#0 SB_CS#1 SB_CS#2 SB_CS#3 AD3 AE3 AD6 AE6 M_B_DIM0_CS#0 15 M_B_DIM0_CS#1 15 SB_ODT0 SB_ODT1 SB_ODT2 SB_ODT3 AE4 AD4 AD5 AE5 M_B_DIM0_ODT0 15 M_B_DIM0_ODT1 15 SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7 D7 F3 K6 N3 AN5 AP9 AK12 AP15 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7 C7 G3 J6 M3 AN6 AP8 AK11 AP14 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15 AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 M_B_DIM0_CLK_DDR0 15 M_B_DIM0_CLK_DDR#0 15 M_B_DIM0_CKE0 15 D M_B_DIM0_CLK_DDR1 15 M_B_DIM0_CLK_DDR#1 15 M_B_DIM0_CKE1 15 C M_B_DQS#[7:0] 15 M_B_DQS[7:0] 15 B SB_BS0 SB_BS1 SB_BS2 SB_CAS# SB_RAS# SB_WE# M_B_A[15:0] 15 SANDY HR UMA A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU (DDR) Size A3 Document Number Rev -1 JE40-HR Date: Thursday, December 02, 2010 Sheet of 102 SSID = CPU OF CPU1E CFG2 DIS_PX_Muxless D R702 Do Not Stuff PEG Static Lane Reversal CFG2 AK28 AK29 AL26 AL27 AK26 AL29 AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 AJ31 AH31 AJ33 AH33 RSVD#AJ31 RSVD#AH31 RSVD#AJ33 RSVD#AH33 AJ26 RSVD#AJ26 1: Normal Operation; Lane # definition matches socket pin map definition SANDY RSVD#AT26 RSVD#AM33 RSVD#AJ27 RSVD#T8 RSVD#J16 RSVD#H16 RSVD#G16 0:Lane Reversed M_VREF_DQ_DIMM0_C M_VREF_DQ_DIMM1_C C B4 D1 D1:VREF_DQ CHB RSVD#B4 RSVD#D1 RN701 SRN1KJ-7-GP F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29 RSVD#F25 RSVD#F24 RSVD#F23 RSVD#D24 RSVD#G25 RSVD#G24 RSVD#E23 RSVD#D23 RSVD#C30 RSVD#A31 RSVD#B30 RSVD#B29 RSVD#D30 RSVD#B31 RSVD#A30 RSVD#C29 J20 B18 A19 RSVD#J20 RSVD#B18 RSVD#A19 J15 RSVD#J15 RSVD#AR35 RSVD#AT34 RSVD#AT33 RSVD#AP35 RSVD#AR34 RESERVED B4:VREF_DQ CHA RSVD#L7 RSVD#AG7 RSVD#AE7 RSVD#AK2 RSVD#W8 RSVD#B34 RSVD#A33 RSVD#A34 RSVD#B35 RSVD#C35 L7 AG7 AE7 AK2 W8 AT26 AM33 AJ27 T8 J16 H16 G16 AR35 AT34 AT33 AP35 AR34 B34 A33 A34 B35 C35 RSVD#AJ32 RSVD#AK32 AJ32 AK32 RSVD#AH27 AH27 RSVD#AN35 RSVD#AM35 AN35 AM35 RSVD#AT2 RSVD#AT1 RSVD#AR1 D C AT2 AT1 AR1 B B SANDY HR UMA A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU (RESERVED) Size A3 Document Number Rev -1 JE40-HR Date: Thursday, December 02, 2010 Sheet of 102 SSID = CPU CPU1F PROCESSOR CORE POWER A VIDALERT# VIDSCLK VIDSOUT AJ29 AJ30 AJ28 C841 SC10U6D3V5KX-1GP 2 C840 SC10U6D3V5KX-1GP C839 SC10U6D3V5KX-1GP C838 SC10U6D3V5KX-1GP C810 SC10U6D3V5KX-1GP C809 SC10U6D3V5KX-1GP C807 SC10U6D3V5KX-1GP 2 C806 SC10U6D3V5KX-1GP R803 43R2J-GP C845 SC10U6D3V5KX-1GP C844 SC10U6D3V5KX-1GP C843 Do Not Stuff 2 DY C842 Do Not Stuff C830 SC10U6D3V5KX-1GP C829 SC10U6D3V5KX-1GP C814 SC10U6D3V5KX-1GP 2 H_CPU_SVIDALRT# C813 SC10U6D3V5KX-1GP J23 C805 SC10U6D3V5KX-1GP VCCIO 1D05V_VTT VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 D No-stuff sites outside the socket may be removed No-stuff sites inside the socket cavity need to remain AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12 C812 SC10U6D3V5KX-1GP PEG AND DDR VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO C VR_SVID_ALERT# 42 H_CPU_SVIDCLK 42 H_CPU_SVIDDAT 42 For CRB VIDSOUT need to pull high 130 ohm closr to CPU and IMVP7 For CRB VIDALERT# need to pull high 75 ohm close to CPU H_CPU_SVIDDAT R804 B 1D05V_VTT 130R2F-1-GP 1 VCC_CORE R801,R802 close to CPU R801 100R2F-L1-GP-U AJ35 AJ34 VCCSENSE 42 VSSSENSE 42 VCC_SENSE VSS_SENSE VCCIO_SENSE VSSIO_SENSE B10 A10 R802 100R2F-L1-GP-U VCCIO_SENSE 45 VSSIO_SENSE 45 B SVID Output Decoupling Recommendation: 470 uF at Bottom Socket Edge 22 uF at Top Socket Cavity 22 uF at Top Socket Edge 22 uF at Bottom Socket Cavity SENSE LINES C827 SC10U6D3V5KX-1GP 2 C828 SC10U6D3V5KX-1GP C826 SC10U6D3V5KX-1GP 2 C831 Do Not Stuff C825 SC10U6D3V5KX-1GP 2 C832 Do Not Stuff DY VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC CORE SUPPLY C811 Do Not Stuff C815 Do Not Stuff C824 SC10U6D3V5KX-1GP C833 SC10U6D3V5KX-1GP DY 2 C804 Do Not Stuff C817 Do Not Stuff DY C823 SC10U6D3V5KX-1GP AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 DY C834 SC10U6D3V5KX-1GP DY 2 C803 Do Not Stuff C818 Do Not Stuff DY C822 SC10U6D3V5KX-1GP 2 C819 Do Not Stuff DY C821 Do Not Stuff DY VCCIO Output Decoupling Recommendation: x 330 uF (3 x 330 uF for 2012 capable designs) x 22 uF & x 0805 no-stuff at Bottom x 22 uF & x 0805 no-stuff at Top 1D05V_VTT C835 SC10U6D3V5KX-1GP C802 Do Not Stuff VCC x x x x DY 2 C DY C837 SC10U6D3V5KX-1GP DY DY C816 SC10U6D3V5KX-1GP C820 Do Not Stuff DY C836 SC10U6D3V5KX-1GP C801 Do Not Stuff D OF SANDY VCC_CORE 53A VCC_CORE POWER A HR UMA Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU (VCC_CORE) Size Custom SANDY Document Number Rev -1 JE40-HR Date: Thursday, December 02, 2010 Sheet of 102 VAXG Output Decoupling Recommendation: x 470 uF at Bottom Socket Edge x 22 uF at Top Socket Cavity x 22 uF at Top Socket Edge x 22 uF at Bottom Socket Cavity x 22 uF at Bottom Socket Edge VCC_GFXCORE POWER Disabling Guidelines for External Graphics Designs: Can connect to GND if motherboard only supports external graphics and if GFX VR is not stuffed Can be left floating (Gfx VR keeps VAXG rail from floating) if the VR is stuffed B 1D8V_S0 B6 A6 A2 C922 SC1U10V2KX-1GP PROCESSOR VCCPLL: 1.2A VCCPLL VCCPLL VCCPLL SENSE LINES D R907 100R2F-L1-GP-U VREF Refer to the latest Huron River Mainstream PDG (Doc# 436735) for more details on S3 power reduction implementation +V_SM_VREF_CNT should have 10 mil trace width SM_VREF AL1 +V_SM_VREF_CNT 37 1D5V_S0 DY C914 Do Not Stuff C913 SC10U6D3V5KX-1GP C912 SC10U6D3V5KX-1GP C911 SC10U6D3V5KX-1GP 2 C910 SC10U6D3V5KX-1GP DY C909 Do Not Stuff PROCESSOR VDDQ: 10A AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ C VDDQ Output Decoupling Recommendation: x 330 uF x 10 uF 0D85V_S0 VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA M27 M26 L26 J26 J25 J24 H26 H25 DY C915 SC10U6D3V5KX-1GP PROCESSOR VCCSA: 6A DIS VCC_AXG_SENSE VSS_AXG_SENSE VCC_AXG_SENSE 42 VSS_AXG_SENSE 42 VCCSA Output Decoupling Recommendation: x 330 uF x 10 uF at Bottom Socket Cavity x 10 uF at Bottom Socket Edge 0D85V_S0 R902 need be close to pin H23 B R902 10R2J-2-GP VCCSA_SENSE H23 VCCUSA_SENSE FC_C22 VCCSA_VID1 C22 C24 H_FC_C22 TP901 Do Not Stuff VCCSA_SEL 48 DIS AK35 AK34 Routing Guideline: Power from DDR_VREF_S3 and +V_SM_VREF_CNT should have 10 mils trace width DDR3 -1.5V RAILS R901 Do Not Stuff DIS 1 DIS R905 Do Not Stuff VAXG_SENSE VSSAXG_SENSE SA RAIL R904 Do Not Stuff R903 Do Not Stuff 2 VCC_GFXCORE SANDY MISC C VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG GRAPHICS UMA_PX_Muxless UMA_PX_Muxless UMA_PX_Muxless UMA_PX_Muxless AT24 AT23 AT21 AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17 AL24 AL23 AL21 AL20 AL18 AL17 AK24 AK23 AK21 AK20 AK18 AK17 AJ24 AJ23 AJ21 AJ20 AJ18 AJ17 AH24 AH23 AH21 AH20 AH18 AH17 1.8V RAIL 2 C920 SC10U6D3V5KX-1GP 2 C919 SC10U6D3V5KX-1GP DY C918 Do Not Stuff C908 SC10U6D3V5KX-1GP 2 DY C907 Do Not Stuff UMA_PX_Muxless UMA_PX_Muxless UMA_PX_MuxlessUMA_PX_Muxless C906 Do Not Stuff DY C921 SC10U6D3V5KX-1GP C905 SC10U6D3V5KX-1GP 2 C904 SC10U6D3V5KX-1GP C903 SC10U6D3V5KX-1GP C902 SC10U6D3V5KX-1GP 2 DY C901 Do Not Stuff PROCESSOR VAXG: 24A R906 100R2F-L1-GP-U OF CPU1G C916 Do Not Stuff VCC_GFXCORE D R906,R907 close to CPU SSID = CPU 2 SANDY RN901 SRN1KJ-7-GP VCCPLL Output Decoupling Recommendation: x 330 uF x uF x 10 uF HR UMA A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU (VCC_GFXCORE) Size A3 Document Number Rev -1 JE40-HR Date: Thursday, December 02, 2010 Sheet of 102 SSID = CPU OF CPU1H AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10 AT7 AT4 AT3 AR25 AR22 AR19 AR16 AR13 AR10 AR7 AR4 AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10 AP7 AP4 AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10 AN7 AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10 AM7 AM4 AM3 AM2 AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10 AL7 AL4 AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10 AK7 AK4 AJ25 D C B VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS SANDY VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS OF CPU1I AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 P9 P8 P6 P5 P3 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34 L33 L30 L27 L9 L8 L6 L5 L4 L3 L2 L1 K35 K32 K29 K26 J34 J31 H33 H30 H27 H24 H21 H18 H15 H13 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29 SANDY VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS SANDY VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3 D C B SANDY HR UMA A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU (VSS) Size A3 Document Number Rev -1 JE40-HR Date: Thursday, December 02, 2010 Sheet 10 of 102 1D5V_VGA_S0 1D5V_VGA_S0 VRAM2 VRAM1 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ H1 M8 L8 VREFDQ VREFCA ZQ D7 C3 C8 C2 A7 A2 B8 A3 DQSU DQSU# C7 B7 QSAP_1 85 QSAN_1 85 DQSL DQSL# F3 G3 QSAP_2 85 QSAN_2 85 MDA12 MDA8 MDA15 MDA10 MDA13 MDA9 MDA14 MDA11 VRAM1_VREF VRAM_ZQ1 VRAM_ZQ2 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 M2 N8 M3 BA0 BA1 BA2 J7 K7 CK CK# 85 85 CLKA0 CLKA0# 85 K9 FBA_CKE0 85 85 DQMA1 DQMA2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ G1 F9 E8 E2 D8 D1 B9 B1 G9 CKE D3 E7 DMU DML L3 K3 J3 WE# CAS# RAS# H1 M8 L8 VREFDQ VREFCA ZQ DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 DQSU DQSU# C7 B7 DQSL DQSL# F3 G3 ODT K1 FBA_ODT0 85 CS# RESET# L2 T2 -FBA_CS0 FBA_RST 85 85,89 NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 T7 L9 L1 J9 J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ G1 F9 E8 E2 D8 D1 B9 B1 G9 1D5V_VGA_S0 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 FBA_A0 FBA_A1 FBA_A2 FBA_A3 FBA_A4 FBA_A5 FBA_A6 FBA_A7 FBA_A8 FBA_A9 FBA_A10 FBA_A11 FBA_A12 FBA_A13 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A15 85,89 85,89 85,89 FBA_BA0 FBA_BA1 FBA_BA2 M2 N8 M3 BA0 BA1 BA2 CLKA0 CLKA0# J7 K7 CK CK# FBA_CKE0 K9 CKE DQMA0 DQMA3 D3 E7 DMU DML L3 K3 J3 WE# CAS# RAS# 85 85 R8803 Do Not Stuff DIS_Muxless 85 85 85 VRAM1_VREF R8804 Do Not Stuff DIS_Muxless D MDA7 MDA0 MDA6 MDA2 MDA4 MDA3 MDA5 MDA1 QSAP_0 85 QSAN_0 85 QSAP_3 85 QSAN_3 85 C8802 85,89 85,89 85,89 DIS_Muxless -FBA_WE -FBA_CAS -FBA_RAS C SB to -1 VRAM1_VREF C8817 Do Not Stuff -FBA_WE -FBA_CAS -FBA_RAS T7 L9 L1 J9 J1 85 85,89 Do Not Stuff 85,89 85,89 85,89 NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 DIS_Muxless -FBA_CS0 FBA_RST FBA_BA0 FBA_BA1 FBA_BA2 L2 T2 R8802 Do Not Stuff 85 85,89 85,89 85,89 CS# RESET# FBA_ODT0 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ E3 F7 F2 F8 H3 H8 G2 H7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A15 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 C FBA_A0 FBA_A1 FBA_A2 FBA_A3 FBA_A4 FBA_A5 FBA_A6 FBA_A7 FBA_A8 FBA_A9 FBA_A10 FBA_A11 FBA_A12 FBA_A13 A8 A1 C1 C9 D2 E9 F1 H9 H2 MDA[63 0] 85,89 MDA26 MDA27 MDA28 MDA30 MDA24 MDA31 MDA25 MDA29 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 1 DIS_Muxless K1 ODT 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 R8801 Do Not Stuff VDD VDD VDD VDD VDD VDD VDD VDD VDD A8 A1 C1 C9 D2 E9 F1 H9 H2 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 K8 K2 N1 R9 B2 D9 G7 R1 N9 VRAM1_VREF VDD VDD VDD VDD VDD VDD VDD VDD VDD MDA[63 0] 85,89 MDA23 MDA19 MDA22 MDA16 MDA21 MDA18 MDA20 MDA17 E3 F7 F2 F8 H3 H8 G2 H7 D K8 K2 N1 R9 B2 D9 G7 R1 N9 DIS_Muxless Do Not Stuff Do Not Stuff DIS_Muxless DIS_Muxless B VRAM SAMSUNG 1Gb VR.1GB0B.006 VRAM HYNIX 1Gb 72.51G63.C0U/VR.1GB0G.005 DG requires 4x0.1uF and 8x1.0uF per VRAM HYNIX 2Gb VR.2GB0G.001 VRAM chip C8805 Do Not Stuff C8804 Do Not Stuff C8803 Do Not Stuff C8801 Do Not Stuff Do Not Stuff 1D5V_VGA_S0 FOR VRAM1 B VRAM = N12PGS_N12PGV FB CMD mapping Mode D-N12x VRAM = N12PGS_N12PGV 1D5V_VGA_S0 C8806 Do Not Stuff DIS_Muxless DIS_Muxless DIS_Muxless DIS_Muxless DIS_Muxless 1D5V_VGA_S0 C8809 DIS_Muxless CLOSE TO THE MEMORY CLOSE TO THE MEMORY C8813 Do Not Stuff C8812 Do Not Stuff C8811 Do Not Stuff C8810 Do Not Stuff FOR VRAM2 Do Not Stuff A A HR UMA C8814 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C DIS_Muxless DIS_Muxless DIS_Muxless DIS_Muxless DIS_Muxless Title GPU-VRAM1,2 (1/4) Size Custom Document Number Rev -1 JE40-HR Date: Thursday, December 02, 2010 Sheet 88 of 102 1D5V_VGA_S0 1D5V_VGA_S0 VRAM3 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ H1 M8 L8 VREFDQ VREFCA ZQ MDA58 MDA57 MDA62 MDA60 MDA63 MDA61 MDA56 MDA59 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 MDA51 MDA53 MDA50 MDA52 MDA48 MDA54 MDA49 MDA55 DQSU DQSU# C7 B7 QSAP_6 85 QSAN_6 85 DQSL DQSL# F3 G3 QSAP_7 85 QSAN_7 85 ODT K1 C 85,88 85,88 85,88 85 85 FBA_BA0 FBA_BA1 FBA_BA2 M2 N8 M3 BA0 BA1 BA2 J7 K7 CK CK# K9 CKE CLKA1 CLKA1# 85 FBA_CKE1 85 85 DQMA6 DQMA7 L3 K3 J3 WE# CAS# RAS# -FBA_WE -FBA_CAS -FBA_RAS VREFDQ VREFCA ZQ L2 T2 NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 T7 L9 L1 J9 J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ G1 F9 E8 E2 D8 D1 B9 B1 G9 -FBA_CS1 FBA_RST E3 F7 F2 F8 H3 H8 G2 H7 MDA43 MDA42 MDA45 MDA40 MDA46 MDA41 MDA44 MDA47 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 MDA33 MDA37 MDA32 MDA36 MDA35 MDA39 MDA34 MDA38 DQSU DQSU# C7 B7 DQSL DQSL# F3 G3 ODT K1 FBA_ODT1 R8904 Do Not Stuff 85 85,88 DIS_Muxless 1D5V_VGA_S0 R8902 Do Not Stuff DIS_Muxless 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 FBA_A0 FBA_A1 FBA_A2 FBA_A3 FBA_A4 FBA_A5 FBA_A6 FBA_A7 FBA_A8 FBA_A9 FBA_A10 FBA_A11 FBA_A12 FBA_A13 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A15 85 CS# RESET# L2 T2 -FBA_CS1 FBA_RST 85 85,88 NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 T7 L9 L1 J9 J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 85,88 85,88 85,88 FBA_BA0 FBA_BA1 FBA_BA2 M2 N8 M3 BA0 BA1 BA2 J7 K7 CK CK# K9 CKE 85 85 CLKA1 CLKA1# 85 VRAM3_VREF FBA_CKE1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ G1 F9 E8 E2 D8 D1 B9 B1 G9 R8903 Do Not Stuff DIS_Muxless 85 85 C8902 DIS_Muxless DQMA4 DQMA5 85,88 85,88 85,88 -FBA_WE -FBA_CAS -FBA_RAS D3 E7 DMU DML L3 K3 J3 WE# CAS# RAS# D QSAP_4 85 QSAN_4 85 QSAP_5 85 QSAN_5 85 C SB to -1 modify to VRAM3_VREF VRAM3_VREF C8917 Do Not Stuff DMU DML CS# RESET# Do Not Stuff 85,88 85,88 85,88 D3 E7 VRAM_ZQ4 H1 M8 L8 MDA[63 0] 85,88 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 85 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A15 FBA_ODT1 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DIS_Muxless N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 R8901 Do Not Stuff FBA_A0 FBA_A1 FBA_A2 FBA_A3 FBA_A4 FBA_A5 FBA_A6 FBA_A7 FBA_A8 FBA_A9 FBA_A10 FBA_A11 FBA_A12 FBA_A13 VRAM3_VREF 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 SB to -1 modify to VRAM3_VREF A8 A1 C1 C9 D2 E9 F1 H9 H2 2 VRAM_ZQ3 VDD VDD VDD VDD VDD VDD VDD VDD VDD VRAM3_VREF SB to -1 modify to VRAM3_VREF K8 K2 N1 R9 B2 D9 G7 R1 N9 A8 A1 C1 C9 D2 E9 F1 H9 H2 E3 F7 F2 F8 H3 H8 G2 H7 D VRAM4 MDA[63 0] 85,88 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 VDD VDD VDD VDD VDD VDD VDD VDD VDD K8 K2 N1 R9 B2 D9 G7 R1 N9 DIS_Muxless Do Not Stuff Do Not Stuff DIS_Muxless SB to -1 delete R8906 , R8905 , modify to VRAM2_VREF B VRAM = N12PGS_N12PGV VRAM SAMSUNG 1Gb VR.1GB0B.006 VRAM HYNIX 1Gb 72.51G63.C0U/VR.1GB0G.005 VRAM HYNIX 2Gb VR.2GB0G.001 C8906 2 2 C8905 Do Not Stuff C8904 Do Not Stuff C8903 Do Not Stuff Do Not Stuff Do Not Stuff 1D5V_VGA_S0 C8901 FB CMD mapping Mode D-N12x VRAM = N12PGS_N12PGV B FOR VRAM3 DIS_Muxless DIS_Muxless DIS_Muxless DIS_Muxless DIS_Muxless DIS_Muxless 1D5V_VGA_S0 1 C8909 DIS_Muxless C8914 2 2 Do Not Stuff C8913 Do Not Stuff C8912 Do Not Stuff C8911 Do Not Stuff C8910 CLOSE TO THE MEMORY Do Not Stuff A Do Not Stuff FOR VRAM4 1D5V_VGA_S0 HR UMA CLOSE TO THE MEMORY DIS_Muxless DIS_Muxless DIS_Muxless DIS_Muxless DIS_Muxless A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title GPU-VRAM3,4 (2/4) Size Document Number Custom Rev -1 JE40-HR Date: Thursday, December 02, 2010 Sheet 89 of 102 1D5V_VGA_S0 1D5V_VGA_S0 VRAM5_VREF VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ H1 M8 L8 E3 F7 F2 F8 H3 H8 G2 H7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 MDB14 MDB8 MDB15 MDB10 MDB12 MDB9 MDB13 MDB11 DQSU DQSU# C7 B7 QSBP_1 85 QSBN_1 85 DQSL DQSL# F3 G3 QSBP_2 85 QSBN_2 85 ODT K1 SB to -1 modify to VRAM5_VREF VRAM5_VREF VRAM_ZQ6 VDD VDD VDD VDD VDD VDD VDD VDD VDD A8 A1 C1 C9 D2 E9 F1 H9 H2 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ H1 M8 L8 VREFDQ VREFCA ZQ E3 F7 F2 F8 H3 H8 G2 H7 MDB3 MDB7 MDB0 MDB5 MDB1 MDB6 MDB2 MDB4 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 MDB30 MDB25 MDB31 MDB27 MDB28 MDB26 MDB29 MDB24 DQSU DQSU# C7 B7 QSBP_3 85 QSBN_3 85 DQSL DQSL# F3 G3 QSBP_0 85 QSBN_0 85 ODT K1 M2 N8 M3 BA0 BA1 BA2 J7 K7 CLKB0 CLKB0# 85 85 85 K9 FBB_CKE0 DQMB1 DQMB2 NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 T7 L9 L1 J9 J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ G1 F9 E8 E2 D8 D1 B9 B1 G9 CKE D3 E7 DMU DML L3 K3 J3 WE# CAS# RAS# -FBB_CS0 FBB_RST 85 85,91 1D5V_VGA_S0 FBB_A0 FBB_A1 FBB_A2 FBB_A3 FBB_A4 FBB_A5 FBB_A6 FBB_A7 FBB_A8 FBB_A9 FBB_A10 FBB_A11 FBB_A12 FBB_A13 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A15 FBB_ODT0 85 CS# RESET# L2 T2 -FBB_CS0 FBB_RST 85 85,91 NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 T7 L9 L1 J9 J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 85,91 85,91 85,91 FBB_BA0 FBB_BA1 FBB_BA2 M2 N8 M3 BA0 BA1 BA2 J7 K7 CK CK# K9 CKE D3 E7 DMU DML L3 K3 J3 WE# CAS# RAS# 85 85 R9003 Do Not Stuff CLKB0 CLKB0# 85 FBB_CKE0 VRAM5_VREF 85 85 DIS_Muxless R9004 Do Not Stuff DQMB3 DQMB0 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ G1 F9 E8 E2 D8 D1 B9 B1 G9 C9002 85,91 85,91 85,91 -FBB_WE -FBB_CAS -FBB_RAS VRAM5_VREF DIS_Muxless DIS_Muxless VRAM = N12PGS B SB to -1 modify to VRAM5_VREF Do Not Stuff DIS_Muxless DIS_Muxless Do Not Stuff C C9017 Do Not Stuff -FBB_WE -FBB_CAS -FBB_RAS L2 T2 Do Not Stuff 85,91 85,91 85,91 CK CK# CS# RESET# 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85 85 R9002 Do Not Stuff DIS_Muxless D FBB_BA0 FBB_BA1 FBB_BA2 85 85,91 85,91 85,91 FBB_ODT0 MDB[63 0] 85,91 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A15 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 FBB_A0 FBB_A1 FBB_A2 FBB_A3 FBB_A4 FBB_A5 FBB_A6 FBB_A7 FBB_A8 FBB_A9 FBB_A10 FBB_A11 FBB_A12 FBB_A13 1 C 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 R9001 Do Not Stuff DIS_Muxless K8 K2 N1 R9 B2 D9 G7 R1 N9 VREFDQ VREFCA ZQ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 VRAM_ZQ5 MDB[63 0] 85,91 MDB20 MDB17 MDB18 MDB19 MDB22 MDB21 MDB23 MDB16 VDD VDD VDD VDD VDD VDD VDD VDD VDD A8 A1 C1 C9 D2 E9 F1 H9 H2 SB to -1 modify to VRAM5_VREF VRAM6 VRAM5 K8 K2 N1 R9 B2 D9 G7 R1 N9 D DIS_Muxless VRAM = N12PGS B VRAM SAMSUNG 1Gb VR.1GB0B.006 VRAM HYNIX 1Gb 72.51G63.C0U/VR.1GB0G.005 VRAM HYNIX 2Gb VR.2GB0G.001 1D5V_VGA_S0 1D5V_VGA_S0 C9006 Do Not Stuff DIS_Muxless DIS_Muxless DIS_Muxless DIS_Muxless DIS_Muxless CLOSE TO THE MEMORY C9009 DIS_Muxless 1D5V_VGA_S0 2 2 C9005 Do Not Stuff C9004 Do Not Stuff C9003 Do Not Stuff C9001 Do Not Stuff Do Not Stuff FOR VRAM5 DG requires 4x0.1uF and 8x1.0uF per VRAM chip CLOSE TO THE MEMORY C9014 Wistron Corporation C9013 2 2 A HR UMA Do Not Stuff C9012 Do Not Stuff C9011 Do Not Stuff C9010 Do Not Stuff Do Not Stuff FOR VRAM6 A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C DIS_Muxless DIS_Muxless DIS_Muxless DIS_Muxless DIS_Muxless Title GPU-VRAM5,6 (3/4) Size Document Number Custom Rev -1 JE40-HR Date: Thursday, December 02, 2010 Sheet 90 of 102 VRAM7 1D5V_VGA_S0 K8 K2 N1 R9 B2 D9 G7 R1 N9 VDD VDD VDD VDD VDD VDD VDD VDD VDD A8 A1 C1 C9 D2 E9 F1 H9 H2 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ H1 M8 L8 VREFDQ VREFCA ZQ E3 F7 F2 F8 H3 H8 G2 H7 MDB34 MDB33 MDB36 MDB37 MDB35 MDB38 MDB32 MDB39 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 MDB48 MDB53 MDB50 MDB55 MDB51 MDB54 MDB49 MDB52 VRAM7_VREF DQSU DQSU# C7 B7 QSBP_6 85 QSBN_6 85 DQSL DQSL# F3 G3 QSBP_4 85 QSBN_4 85 ODT K1 CS# RESET# L2 T2 NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 T7 L9 L1 J9 J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ G1 F9 E8 E2 D8 D1 B9 B1 G9 SB to -1 modify to VRAM7_VREF VRAM7_VREF VRAM_ZQ8 J7 K7 CK CK# FBB_CKE1 K9 CKE DQMB6 DQMB4 D3 E7 DMU DML L3 K3 J3 WE# CAS# RAS# 85 85 85 -FBB_WE -FBB_CAS -FBB_RAS H1 M8 L8 VREFDQ VREFCA ZQ 85,90 85,90 DIS_Muxless85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 FBB_A0 FBB_A1 FBB_A2 FBB_A3 FBB_A4 FBB_A5 FBB_A6 FBB_A7 FBB_A8 FBB_A9 FBB_A10 FBB_A11 FBB_A12 FBB_A13 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A15 85,90 85,90 85,90 FBB_BA0 FBB_BA1 FBB_BA2 M2 N8 M3 BA0 BA1 BA2 J7 K7 CK CK# FBB_CKE1 K9 CKE DQMB5 DQMB7 D3 E7 DMU DML L3 K3 J3 WE# CAS# RAS# 1D5V_VGA_S0 85 85 R9102 Do Not Stuff DIS_Muxless CLKB1 CLKB1# 85 VRAM7_VREF DIS_Muxless 85,90 85,90 85,90 R9104 Do Not Stuff CLKB1 CLKB1# VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ E3 F7 F2 F8 H3 H8 G2 H7 MDB58 MDB57 MDB59 MDB56 MDB63 MDB61 MDB60 MDB62 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 MDB41 MDB47 MDB42 MDB45 MDB40 MDB43 MDB44 MDB46 DQSU DQSU# C7 B7 QSBP_5 85 QSBN_5 85 DQSL DQSL# F3 G3 QSBP_7 85 QSBN_7 85 ODT K1 FBB_ODT1 85 CS# RESET# L2 T2 -FBB_CS1 FBB_RST 85 85,90 NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 T7 L9 L1 J9 J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ G1 F9 E8 E2 D8 D1 B9 B1 G9 Do Not Stuff D C 85 85 85 85,90 A8 A1 C1 C9 D2 E9 F1 H9 H2 MDB[63 0] 85,90 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 BA0 BA1 BA2 FBB_BA0 FBB_BA1 FBB_BA2 -FBB_CS1 FBB_RST VDD VDD VDD VDD VDD VDD VDD VDD VDD 85 85 R9103 Do Not Stuff C9118 DIS_Muxless 85,90 85,90 85,90 -FBB_WE -FBB_CAS -FBB_RAS SB to -1 modify to VRAM7_VREF VRAM7_VREF C9117 Do Not Stuff M2 N8 M3 85,90 85,90 85,90 85 C FBB_ODT1 Do Not Stuff A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A15 FBB_A0 FBB_A1 FBB_A2 FBB_A3 FBB_A4 FBB_A5 FBB_A6 FBB_A7 FBB_A8 FBB_A9 FBB_A10 FBB_A11 FBB_A12 FBB_A13 DIS_Muxless N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 R9101 Do Not Stuff K8 K2 N1 R9 B2 D9 G7 R1 N9 2 VRAM_ZQ7 VRAM8 MDB[63 0] 85,90 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 D SB to -1 modify to VRAM7_VREF 1D5V_VGA_S0 DIS_Muxless Do Not Stuff DIS_Muxless VRAM = N12PGS 1D5V_VGA_S0 B CLOSE TO THE MEMORY C9106 C9114 2 2 C9113 Do Not Stuff C9112 Do Not Stuff C9111 Do Not Stuff C9110 C9109 CLOSE TO THE MEMORY Do Not Stuff Do Not Stuff FOR VRAM8 1D5V_VGA_S0 DIS_Muxless Do Not Stuff DIS_Muxless DIS_Muxless DIS_Muxless DIS_Muxless DIS_Muxless DIS_Muxless C9105 2 C9104 HR UMA DIS_Muxless DIS_Muxless DIS_Muxless DIS_Muxless DIS_Muxless A B VRAM SAMSUNG 1Gb VR.1GB0B.006 VRAM HYNIX 1Gb 72.51G63.C0U/VR.1GB0G.005 VRAM HYNIX 2Gb VR.2GB0G.001 1 1 2 C9103 Do Not Stuff Do Not Stuff Do Not Stuff C9102 Do Not Stuff C9101 Do Not Stuff Do Not Stuff FOR VRAM7 1D5V_VGA_S0 DIS_Muxless VRAM = N12PGS A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title GPU-VRAM7,8 (4/4) Size Document Number Custom JE40-HR Date: Thursday, December 02, 2010 Rev -1 Sheet 91 of 102 20100715 DCBATOUT 20100719 SSID = PWR.Plane.Regulator_GFX PWR_DCBATOUT_VGA_CORE PG9201 VGA_CORE VGA_CORE_PWR VGA_CORE PG9206 PG9216 2 Do Not Stuff PG9202 PU9202 Do Not Stuff Do Not Stuff PG9203 Do Not Stuff 2nd = 84.08030.037 DIS_Muxless 1 8 VOUT N12PGS_N12PGV Do Not Stuff 2nd = 84.08028.037 DIS_Muxless PR9203 Do Not Stuff N12PGS_N12PGV DIS_Muxless 1 DIS_Muxless DIS_Muxless DIS_Muxless DIS_Muxless PWR_VGA_CORE_VOUT PTC9202 Do Not Stuff DIS_Muxless Do Not Stuff PG9208 Do Not Stuff PG9218 Do Not Stuff PG9209 Do Not Stuff PG9219 Do Not Stuff PG9210 Do Not Stuff PG9220 Do Not Stuff PG9211 Do Not Stuff PG9221 Do Not Stuff PG9212 Do Not Stuff PG9222 Do Not Stuff PG9214 Do Not Stuff PG9223 Do Not Stuff PG9213 Do Not Stuff PG9224 Do Not Stuff PG9215 Do Not Stuff PG9225 Do Not Stuff PG9227 Do Not Stuff PG9226 Do Not Stuff Do Not Stuff D PTC9204 Do Not Stuff C PTC9203 Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff 2nd = 77.C3371.051 2nd = 77.C3371.051 2nd = 77.C3371.051 Do Not Stuff Do Not Stuff PU9205 S S S G PU9201 Do Not Stuff S S S G Do Not Stuff 2nd = 84.08028.037 DIS_Muxless PU9204 Do Not Stuff 86 PWR_VGA_CORE_VOUT PC9208 PWR_VGA_CORE_D1 PWR_VGA_CORE_D0 PG9205 PWRCNTL_1 DIS_Muxless 86 PWRCNTL_0 Do Not Stuff PG9217 2 PWR_VGA_CORE_FB VGA_CORE_PWR Do Not Stuff PG9207 GND 14 6 EM/DEM 17 G0 FB G1 D1 D0 DIS_Muxless Do Not Stuff 2nd = 68.R3610.10M Do Not Stuff 15 12 11 DIS_Muxless PL9201 Do Not Stuff PGOOD CS 13 DIS_Muxless PR9205 Do Not Stuff PC9206 2PWR_VGA_CORE_BOOT_C1 Do Not Stuff PWR_VGA_CORE_UGATE PR9218 VGA_CORE_UGATE PWR_VGA_CORE_PHASE Do Not Stuff PWR_VGA_CORE_LGATE VGA_CORE_LGATE PR9219 Do Not Stuff PWR_VGA_CORE_BOOT1 VDD 10 BOOT UGATE PHASE LGATE DIS_Muxless 4 1 SB 20100831 C PC9203 Design Current = 21.94A 24.14A165KHz 200K >323KHz 100K >500KHz VGA_CORE_PWR PQ9201 Do Not Stuff B DY DY 8209A_EN/DEM_VGA Do Not Stuff TP9202 PQ9206_3 PR9215 Do Not Stuff VGACORE_GND_SENSE PR9216 Do Not Stuff PWR_VGA_CORE_EN_R# DIS_Muxless N12PGS_N12PGV:64.43025.6DL N12PGS_N12PGV:63.75334.1DL 1GND_SENSE_1 DIS_Muxless PR9207 Do Not Stuff DIS_Muxless PC9212 Do Not Stuff PR9217 Do Not Stuff DY R4 PR9213 Do Not Stuff DIS_Muxless Switching freq >350KHz DGPU_PWROK 22,93 DIS_Muxless PR9210 Do Not Stuff PWR_VGA_CORE_D1 PR9214 Do Not Stuff R2 PR9209 Do Not Stuff VGA_Core to 1.05V SB to -1 modify PR9213 PWR_VGA_CORE_FB PWR_VGA_CORE_D0 PR9212 Do Not Stuff 3D3V_AUX_S5 H 1.00V H 0.975V I/P cap: 10U 25V K1206 X5R/ 78.10622.52L Inductor: 1.5UH PCMC104T-1R5MN Cyntec DCR:4.2mohm Isat =33Arms 68.1R510.10J O/P cap: 330U 2V EEFSX0D331ER 9mOhm 3Arms Panasonic/ 79.33719.L01 H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037 L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/6.1mohm@4.5Vgs/ 84.00460.037 B DIS_Muxless DY H L L H P0 - HOT P0 - COLD R3 3D3V_VGA_S0 8209A_PGOOD_VGA DY DIS_Muxless PWR_VGA_CORE_D1 PWR_VGA_CORE_D0 P-State DIS_Muxless DIS_Muxless PC9209 PC9210 PR9208 Do Not Stuff N12P GS PD9201 Do Not Stuff PC9211 Do Not Stuff Do Not Stuff 8209A_EN/DEM_VGA DY TP9203 0806 check Power Do Not Stuff Do Not Stuff 19,27,36,37,47 PM_SLP_S3# PR9211 Do Not Stuff RT8208A Do Not Stuff PR9206 2 DIS_Muxless 3D3V_VGA_S0 Vout=0.75V*(R1+R2)/R2 N12P GV P-State A PWR_VGA_CORE_D1 PWR_VGA_CORE_D0 VGA_CORE_PWR P8 , P12 L L 0.85V P0 - HOT L H 1.00V P0 - COLD H L 1.025V H H A HR UMA Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title RT8208B_+VGA_CORE Size Document Number Custom Rev -1 JE40-HR Date: Thursday, December 02, 2010 Sheet 92 of 102 1D5V_VGA_S0 +3VS to 3.3V_DELAY Transfer SB modify to 84.03006.A37 R9301 Do Not Stuff D DIS 3D3V_VGA_S0 1D5V_VGA_S0 2nd = 84.08882.037 check layout 1D05V_VTT Do Not Stuff DIS_Muxless DIS_Muxless TC9302 Do Not Stuff 1D05V_VGA_S0 U9302 Do Not Stuff TC9301 Do Not Stuff Do Not Stuff Do Not Stuff 2ND = 79.3971V.3AL DIS_Muxless DIS_Muxless DIS_Muxless D D D D S S S 3.6A G R9304 Do Not Stuff RUN_ENABLE DIS_Muxless -1 modify R9305 Q9303 to DY DY Muxless S RUNON_R_1 RUNON_R_1 Do Not Stuff 2nd = 84.DM601.03F Muxless Q9301 Do Not Stuff 3.3V_ALW_1 C9302 1 S S S G C9301 D D D D G Do Not Stuff 2ND = 84.03413.A31 Do Not Stuff AO4468, SO-8 Id=11.6A, Qg=9~12nC Rdson=17.4~22m ohm Q9302 Do Not Stuff 1 D G 1D5V_S3 Do Not Stuff D R9302 Do Not Stuff Muxless 1.05V to 1.05V_VGA_S0 Transfer Do Not Stuff Muxless S 3D3V_S0 D U9301 Do Not Stuff D R9303 Do Not Stuff RUNON_R G 18 DGPU_PWR_EN# Muxless D 1 R9306 Do Not Stuff C9308 Do Not Stuff DIS_Muxless DIS_Muxless R9307 Do Not Stuff DY DY C C9303 Do Not Stuff DIS_EN_1D5_RUN_R2ND = 84.00610.C31 DY Muxless DGPU_PWR_EN 3D3V_S0 Do Not Stuff R9305 Do Not Stuff R9308 Do Not Stuff Q9303 Do Not Stuff G 3.3V_RUN_VGA_1 DY C DIS_EN_1D5_RUN D S RUNON_R_1 Q9305 2ND = 84.2N702.031 22,92 DGPU_PWROK Q9304 Do Not Stuff DGPU_PWROK_R Do Not Stuff B Do Not Stuff S 5V_S5 2ND = 84.2N702.031 DY DY 1D5V_VGA_S0 VCC ON DIS2 GND NC#9 PG G1/G2 S/DIS1 D DIS_Muxless R9309 Do Not Stuff 1D8V_VGA_S0 DIS_Muxless 3D3V_VGA_S0 U9305 Do Not Stuff -1 co-layout SLG55221 C9307 Do Not Stuff 2 C9305 C9306 DIS_Muxless 1 22,92 DGPU_PWROK 1D5V_VGA_S0 5V_S5 Do Not Stuff A DIS_Muxless -1 modify R9322 Ղٙ RUNON_R_1 DGPU_PWROK 22,92 DY Do Not Stuff Do Not Stuff DIS_Muxless DGPU_PWROK_TO1D8V VIN GND EN NC#4 VOUT B +3VS to 1.8V Transfer I=300mA Do Not Stuff DIS_Muxless SLG_RUN_ENABLE_VGA U9303 Do Not Stuff 6 EN DC2 DC1 5V_S5 DY DY VCC GND HV R9323 Do Not Stuff RT9025 for 1D8V_VGA 5V_S5 R9322 Do Not Stuff Do Not Stuff 22,92 DGPU_PWROK C9304 G DY 1D05V_VGA_S0 U9304 Do Not Stuff Do Not Stuff R9310 Do Not Stuff 2 Do Not Stuff HR UMA A 1D8V_S0_NV = IFPA_IOVDD & IFPB_IOVDD, it should be the latest ramp up rail Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title DISCRETE VGA POWER Size Document Number Custom Rev -1 JE40-HR Date: Thursday, December 02, 2010 Sheet 93 of 102 LVDS Channel A RN9401 Do Not Stuff DIS D 84 84 84 84 GPU_LVDSA_TX0 GPU_LVDSA_TX0# GPU_LVDSA_TX1# GPU_LVDSA_TX1 GPU_LVDSA_TX2# GPU_LVDSA_TX2 GPU_LVDSA_TXC GPU_LVDSA_TXC# 17 17 17 17 LVDSA_DATA0 LVDSA_DATA0# LVDSA_DATA1# LVDSA_DATA1 D LVDSA_DATA2_R# 49 LVDSA_DATA2_R 49 LVDSA_CLK_R 49 LVDSA_CLK_R# 49 RN9408 SRN0J-7-GP UMA_Muxless C LVDSA_DATA0_R 49 LVDSA_DATA0_R# 49 LVDSA_DATA1_R# 49 LVDSA_DATA1_R 49 RN9405 Do Not Stuff DIS 84 84 84 84 5 RN9410 SRN0J-7-GP LVDSA_DATA0_R 49 LVDSA_DATA0_R# 49 LVDSA_DATA1_R# 49 LVDSA_DATA1_R 49 C 3D3V_S0 LVDSA_DATA2_R# 49 LVDSA_DATA2_R 49 LVDSA_CLK_R 49 LVDSA_CLK_R# 49 LVDSA_DATA2# LVDSA_DATA2 LVDSA_CLK LVDSA_CLK# RN9403 SRN2K2J-1-GP RN9404 Do Not Stuff UMA_Muxless 17 17 17 17 DIS 86 GPU_LVDS_CLK 86 GPU_LVDS_DATA B Panel BL brightness/Power En/BL En 17 L_BKLT_CTRL 17 L_BKLT_EN 17 LVDS_VDD_EN A 27 BRIGHTNESS R9406 Do Not Stuff 86 VGA_LBKLT_CTL R9407 Do Not Stuff LBKLT_CTL_R 86 VGA_LCDVDD_EN 86 VGA_BLEN DY 8 RN9413 Do Not Stuff 4 B UMA_Muxless LBKLT_CTL 49 PANEL_BLEN 27 LCDVDD_EN 49 HR UMA LCDVDD_EN 49 PANEL_BLEN 27 LBKLT_CTL 49 DIS Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title LVDS_Switch Size A4 DIS Document Number JE40-HR Thursday, December 02, 2010 Date: LVDS_DDC_CLK 49 LVDS_DDC_DATA 49 RN9407 SRN0J-6-GP 17 LVDS_DDC_CLK_R 17 LVDS_DDC_DATA_R RN9412 SRN0J-7-GP 2 Rev -1 Sheet 94 of 102 A Close to CRT Board CONN 86 VGA_CRT_BLUE 86 VGA_CRT_GREEN 86 VGA_CRT_RED 17 CRT_RED 17 CRT_GREEN 17 CRT_BLUE CRT DDCDATA & DDCCLK RN9501 Do Not Stuff RN9503 SRN0J-6-GP CRT_BLUE_R 50 CRT_GREEN_R 50 CRT_RED_R 50 17 CRT_DDC_DATA 17 CRT_DDC_CLK RN9502 SRN0J-7-GP 5V Tolerance DIS D CRT_RED_R 50 CRT_GREEN_R 50 CRT_BLUE_R 50 86 VGA_CRT_DDCDATA 86 VGA_CRT_DDCCLK DDCDATA 50 DDCCLK 50 UMA_Muxless RN9504 Do Not Stuff Pull high ڇCRT D DDCDATA DDCCLK DIS UMA_Muxless C C SB to -1 modify port Logic 3D3V_S0 dGPU_SELECT_A dGPU_SELECT_B RN9505 SRN0J-6-GP 3D3V_S0 dGPU_SELECT_B dGPU_SELECT_A UMA_Muxless RN9506 Do Not Stuff DIS B B L=>B0 -DIS H=>B1 -UMA CRT Hsync & Vsync level shift dGPU_SELECT_A 5V_S0 5V_S0 86 VGA_CRT_HSYNC 14 73.74125.F0B 2nd = 73.74125.L13 73.74125.F0B 2nd = 73.74125.L13 CRT_VSYNC1_1 CRT_HSYNC1_1 5V_S0 CRT_VSYNC 73.74125.F0B 2nd = 73.74125.L13 17 CRT_HSYNC 13 For UMA CRT 14 10 14 50 CRT_VSYNC1_1 R9503 10R2J-2-GP CRT_VSYNC_CON 50 12 U9506D TC74VHCT125AFTQK2M-GP HR UMA 73.74125.F0B 2nd = 73.74125.L13 A Wistron Corporation 11 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C 17 CRT_HSYNC_CON dGPU_SELECT_B U9506C TC74VHCT125AFTQK2M-GP A R9504 10R2J-2-GP 5V_S0 dGPU_SELECT_B For UMA CRT CRT_HSYNC1_1 SB to -1 modify R9503,R9504 to 10 ohm U9506A TC74VHCT125AFTQK2M-GP For DIS CRT 86 VGA_CRT_VSYNC 14 For DIS CRT U9506B TC74VHCT125AFTQK2M-GP Title CRT_Switch Size A3 Document Number Rev -1 JE40-HR Date: Thursday, December 02, 2010 Sheet 95 of 102 SSID = SDIO D D C C B B A A HR UMA Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title TOUCH PANEL Size A2 Date: Document Number Rev -1 JE40-HR Thursday, December 02, 2010 Sheet 96 of 102 CPU 1 1 1 AFTP8 5V_S5 AFTP9 AFTP10 AFTP11 AFTP12 AFTP13 PLT_RST# Test Point࣋ڇDimm Doorؚၲױၦྒྷ 1 HS6 STF256R89H178-GP DY DIS_Muxless HS7 -2 delete SPR5 STF256R89H178-GP Do Not Stuff SPRING-63-GP C SPR3 AFTP7 3D3V_S5 27,36 S5_ENABLE 5,18,27,31,36,65,66,71,82 Do Not Stuff Do Not Stuff SPR2 AFTP1 5,22,36 H_CPUPWRGD HS5 DIS_Muxless SB to -1 BOM add SPR2 D VGA HS4 3D3V_S0 3D3V_AUX_S5 19,27 PM_PWRBTN# 1 1 H11 Do Not Stuff H10 Do Not Stuff H2 Do Not Stuff H3 Do Not Stuff H4 Do Not Stuff H5 Do Not Stuff H6 Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff H7 Check test point HS1 STF237R128H42-1-GP H8 Do Not Stuff D STF237R128H42-1-GP STF237R128H42-1-GP H1 H9 HS2 HS3 C Change:34.40V16.001 3G Sku 5V_S0 AD_JK DY 3G_RF EC9704 3G_RF SCD1U50V3KX-GP DY 1 EC9701 EC9705 2 1 1 EC9706 SCD1U50V3KX-GP EC9702 Do Not Stuff B EC9703 SCD1U50V3KX-GP DY 3G_RF Do Not Stuff 3G_RF 3G_RF 3G_RF 1D05V_VTT RFC9713 Do Not Stuff RFC9715 Do Not Stuff RFC9716 SCD1U50V3KX-GP SCD1U50V3KX-GP SCD1U50V3KX-GP SCD1U50V3KX-GP RFC9714 Do Not Stuff RFC9717 1D5V_S3 3D3V_S0 5V_S0 3D3V_S5 EC9715 3G_RF B DCBATOUT INT_MIC_L_R 29,49 1 3G_RF EC9716 2 2 3G_RF EC9718 3G_RF EC9717 SCD01U25V2KX-3GP 1D05V_VGA_S0 EC9719 SCD1U50V3KX-GP 3D3V_S5 1D5V_S3 EC9713 SCD1U50V3KX-GP 3G_RF DY SCD1U50V3KX-GP EC9714 Do Not Stuff SCD1U50V3KX-GP Do Not Stuff DY ECL9701 Do Not Stuff DY RFC9712 1 5V_S0 DCBATOUT 1D05V_VGA_S0 1 EC9709 3G_RF 3G_RF EC9710 HR UMA A 3G_RF 2 1 2 Do Not Stuff 1 2 2 SCD1U50V3KX-GP EC9712 SCD1U50V3KX-GP EC9707 3G_RF SC56P50V2JN-2GP EC9708 3G_RF 3G_RF SC56P50V2JN-2GP EC9711 SCD1U50V3KX-GP SC56P50V2JN-2GP RFC9704 DY SC56P50V2JN-2GP RFC9710 RFC9709 SC1000P50V3JN-GP-U RFC9703 SC56P50V2JN-2GP RFC9705 SCD01U25V2KX-3GP 3G_RF RFC9706 SC56P50V2JN-2GP RFC9708 SC56P50V2JN-2GP 3G_RF 3G_RF3G_RF SC1000P50V3JN-GP-U SCD1U50V3KX-GP SCD1U50V3KX-GP SCD1U50V3KX-GP RFC9702 RFC9701 RFC9707 RFC9711 A DCBATOUT Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title UNUSED PARTS/EMI Capacitors Size A3 Document Number Rev -1 JE40-HR Date: Thursday, December 02, 2010 Sheet 97 of 102 Power Sequence PU4601 PM_SLP_S4# 1D5V_S3 PU4501 RUNPWROK 1D05V_S0 U4801 1.05VTT_PWRGD 0D85V_S0 0D85V_S0 1D5V_S3 D D 1D05V_VTT 0D75V_EN ALL_POWER_OK 0D75V_S0 PLT_RST# U? U? U? U? ALL_POWER_OK EC S0_PWR_GOOD PCH PM_DRAM_PWRGD AND GATE VDDPWRGOOD CPU H_CPU_SVIDCLK C C ALL_POWER_OK H_CPUPWRGD U? VCC_GFXCORE CPU_CORE SYS_PWROK VCC_CORE U? H_CPU_SVIDCLK IMVP_PWRGD B AND GATE B S0_PWR_GOOD HR UMA A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Change History Size A3 Document Number Rev -1 JE40-HR Date: Thursday, December 02, 2010 Sheet 98 of 102 Intel-Power Up Sequence (AC mode) (DC mode) red word: KBC GPIO +RTC_VCC +RTC_VCC T1 T1 PCH_RTCRST# PCH_RTCRST# +PWR_SRC +PWR_SRC T2 +3.3V_RTC_LDO D red word: KBC GPIO T2 +3.3V_RTC_LDO T3 S5_ENABLE KBC GPIO36 control Press Power button KBC_PWRBTN_EC# T4 +5V_ALW T5 +3.3V_ALW T6 T4 S5_ENABLE +5VALW_PCH_VCC5REFSUS KBC GPIO36 control T5 +5V_ALW +15V_ALW T7 T8 T9 T10 >10ms PCH_RSMRST#(EC Delay 40ms) T11 +5V_ALW & +3.3V_ALW need meet 0.7V difference T7 +5V_ALW & +3.3V_ALW need meet 0.7V difference +5VALW_PCH_VCC5REFSUS PCH to KBC GPI94 SUS_PWR_DN_ACK T6 +3.3V_ALW TPS51125 to KBC GPIO46 3V_5V_POK D KBC_PWRBTN_EC# GPIO3 EC_ENABLE# (GPIO51) keep low T3 +KBC_PWR KBC GPIO43 to PCH +15V_ALW PCH to KBC GPIO00 3V_5V_POK PCH_SUSCLK_KBC T8 T9 TPS51125 to KBC GPIO46 T10 KBC GPO84 to PCH PM_PWRBTN# PCH to KBC GPI94 T12 10ms T13 PCH_SUSCLK_KBC AC KBC_PWRBTN_EC# PCH to KBC GPIO01 KBC_PWRBTN_EC# GPIO3 3V_5V_POK T13 DC PCH_RSMRST# KBC GPO84 to PCH T14 AC PM_PWRBTN# PM_SLP_S4# AC PM_PWRBTN# T14 T15 PM_SLP_S3# >30us T16 PM_LAN_ENABLE PM_SLP_S4# T15 PM_SLP_S3# >30us C KBC GPO16 to LAN T17 +3.3V_LAN T16 PM_LAN_ENABLE KBC GPO16 to LAN T17 +3.3V_LAN +1.5V_SUS T18 +V_DDR_REF(0.9V) T19 +5V_RUN +5V_RUN & +3.3V_RUN need meet 0.7V difference T21 T18 +V_DDR_REF(0.9V) T19 C +5V_RUN & +3.3V_RUN need meet 0.7V difference +5V_RUN T20 +3.3V_RUN T21 T22 +5VS_PCH_VCC5REF T20 +3.3V_RUN +1.5V_SUS T22 +5VS_PCH_VCC5REF +1.5V_RUN T23 +1.8V_RUN T24 T25 >1ms H_PWRGD KBC GPIO71 to RT8208B +1.5V_RUN T23 +1.8V_RUN T24 T25 >1ms GFX_CORE_EN(Discrete only) H_PWRGD KBC GPIO71 to RT8208B GFX_CORE_EN(Discrete only) Delay 5ms T27 T28 T28 KBC GPIO30 to APL5930 T30 T31 +1.8V_RUN_VGA(Discrete only) T30 KBC GPIO66 to APL5930 T31 +3.3V_RUN_VGA(Discrete only) T32 +3.3V_RUN_VGA_EN(Discrete only) >DY reserved T32 +3.3V_RUN_VGA_EN(Discrete only) >DY reserved 1.8V_VGA_RUN_EN(Discrete only) Delay 5ms +1.8V_RUN_VGA(Discrete only) KBC GPIO66 to APL5930 1.8V_VGA_RUN_EN(Discrete only) T29 +1.0V_RUN_VGA(Discrete only) KBC GPIO30 to APL5930 T29 +1.0V_RUN_VGA(Discrete only) 1.0V_RUN_VGA_EN(Discrete only) Delay 4ms +3.3V_RUN_VGA(Discrete only) T27 1.0V_RUN_VGA_EN(Discrete only) T26 +VGA_CORE(Discrete only) T26 +VGA_CORE(Discrete only) KBC GPI95 T33 >Reserved for sequence KBC GPI95 RUNPWROK T33 >Reserved for sequence T34 T35 +1.05V_VTT RUNPWROK 1.5CPU_1.05VTT_PWRGD(after delay 1ms GPI96-VDDPWRGOOD_EC output T34 T35 +1.05V_VTT B 1.5CPU_1.05VTT_PWRGD(after delay 1ms GPI96-VDDPWRGOOD_EC output T37 +0.75V_DDR_VTT TPS51218 to KBC GPI34 T36 for s3 reduction) TPS51218 to KBC GPI34 T36 for s3 reduction) H_VTTPWRGD B T38 T37 +0.75V_DDR_VTT T38 H_VTTPWRGD +1.05V_VTT T39 CPU to TPS51611 GFX_VR_EN(UMA only) +1.05V_VTT T39 UMA GFX CORE Power T40 +CPU_GFX_CORE(UMA only) CPU to TPS51611 GFX_VR_EN(UMA only) UMA GFX CORE Power T40 +CPU_GFX_CORE(UMA only) 1.5CPU_1.05VTT_PWRGD T41 ( >99ms ) T41 T42 ( >99ms ) +VCC_CORE KBC GPO53 to ISL62883 IMVP_VR_ON +VCC_CORE CLKIN_BCLK(from CK505) stable CPU CORE Power 1ms CLK_CPU_BCLK CLKIN_BCLK(from CK505) stable 43 ISL62883 to CLOCKGEN CK_PWRGD >1ms ISL62883 to CLOCKGEN 1.5CPU_1.05VTT_PWRGD 1.5CPU_1.05VTT_PWRGD T46 >5ms T46 >5ms ISL62884 to KBC GPO14 T44 >1ms IMVP_PWRGD 3ms< +1.5V_RUN_CPU KBC GPIO47 to PCH PM_PWROK 3ms< +1.5V_RUN_CPU PM_DRAM_PWRGD T47 100ns T47 100ns T48 >1ms (for S3 Reduction) T48 >1ms H_VTTPWRGD T50 >1ms (for S3 Reduction) A PM_PWROK H_VTTPWRGD T51 >1ms T50 >1ms +VCC_CORE PM_PWROK 0.05ms< T51 >1ms T52 1ms KBC LRESET# T54 KBC GPIO45 PLTRST_DELAY# KBC LRESET# HR UMA T55 Wistron Corporation H_CPURST# KBC GPIO45 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C PLTRST_DELAY# T55 Title H_CPURST# Power Sequence Size A1 Date: Document Number Rev -1 JE40-HR Thursday, December 02, 2010 Sheet 99 of 102 VGA_CORE RT8208B For Discrete 1D5V_VGA_S0 AO4468 1V_VGA_S0 RT9025 D D Adapter DCBATOUT UP6165BQKF-1 NCP6131S52MNR2G UP6128PQDD APL5916KAI DDR_VREF_S3 AO4407A 0D75V_S0 1D5V_S3 Charger Battery VCC_CORE BQ24745 +AD VCC_GFXCORE 1D05V_VTT 0D85V_S0 AO4468 For UMA 1D5V_S0 UP6183PQAG For Discrete C 3D3V_AUX_S5 SI2301CDS +KBC_PWR 5V_AUX_S5 5V_S5 UP7534BRA8 1D5V_DDR_S0 3D3V_S5 UP7534BRA8 UP7534BRA8 AO4468 5V_USB1_S3 5V_USB2_S3 5V_USB0_S5 5V_S0 USB Power USB Power C AO4468 RT9025 3D3V_S0 3D3V_VGA_S0 1D8V_VGA_S0 For Discrete USB Charge Power For Discrete G9091 RT9025 3D3V_CARD_S0 G5285T11U-GP 3D3V_DAC_S0 B B 1D8V_S0 LCDVDD Power Shape Regulator LDO Switch HR UMA A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Power Block Diagram Size A3 Date: Document Number JE40-HR Thursday, December 02, 2010 Rev -1 Sheet 100 of 102 A B C 3D3V_S5 3D3V_S0 KBC SMBus Block Diagram Θ Θ PCH SMBus Block Diagram D E 5V_S0 Θ 3D3V_S0 SRN2K2J-1-GP SRN2K2J-1-GP Θ SMBCLK SMB_CLK SMBDATA SMB_DATA DIMM Θ Θ ΘPCH_SMBCLK Θ PCH_SMBDATA SRN10KJ-5-GP TouchPad Conn SCL SDA 3D3V_S5 SMBus Address:A0 PSDAT1 TPDATA PSCLK1 TPCLK Θ Θ TPDATA TPDATA TPCLK TPCLK 2N7002SPT 3D3V_AUX_KBC Θ SRN2K2J-8-GP Θ SML1CLK SML1_CLK SML1DATA SML1_DATA To KBC & eDP SML0CLK SML0_CLK SML0DATA SML0_DATA Θ SCL Battery Conn SRN100J-3-GP SDA GPIO17/SCL1 BAT_SCL BATA_SCL_1 CLK_SMB GPIO22/SDA1 BAT_SDA BATA_SDA_1 DAT_SMB SMBus address:16 SMBus Address:A4 SRN2K2J-1-GP G-Sensor 3D3V_S0 XDP Θ PCH SRN4K7J-8-GP DIMM ΘPCH_SMBCLK Θ PCH_SMBDATA 3D3V_S5 ΘPCH_SMBCLK Θ PCH_SMBDATA BQ24745 KBC SCLK SCL SDA NPCE795 SDATA SMBus address:12 SRN2K2J-1-GP UMA SDVO_CTRLCLK SDVO_CTRLDATA SMBus address:xx SDA Level Shift PCH_HDMI_CLK PCH_HDMI_DATA SCL LCDVDD_eDP PCH DDC_CLK_HDMI DDC_DATA_HDMI UMA ΘPCH_SMBCLK Θ PCH_SMBDATA 3D3V_S0 Θ Minicard WLAN LCDVDD_eDP SRN2K2J-1-GP Θ SMB_CLK Θ Θ Θ SRN2K2J-1-GP UMA SRN0J-6-GP PCH_SMBCLK L_DDC_CLK LVDS_DDC_CLK_R PCH_SMBDATA L_DDC_DATA eDP SMB_DATA LVDS_DDC_DATA_R Minicard W-WAN GPIO73/SCL2 SML1_CLK GPIO74/SDA2 SML1_DATA SMB_CLK Θ LCD_SMBCLK SCL LCD_SMBDATA SDA SMBus address:XX 2N7002DW-1-GP Θ SMB_DATA UMA CRT_DDC_CLK CRT_DDC_DATA 3D3V_VGA_S0 CRT_DDC_CLK CRT_DDC_DATA Θ SRN2K2J-1-GP DIS SRN0J-6-GP DDC1CLK GPU_LVDS_CLK DDC1DATA GPU_LVDS_DATA LVDS_DDC_CLK CLK LVDS_DDC_DATA DATA LCD CONN DIS DDC2CLK VGA_CRT_DDCCLK DDC2DATA VGA_CRT_DDCDATA SRN0J-6-GP 3D3V_S0 VGA 5V_S0 DIS Θ Θ 3D3V_S0 UMA SRN0J-6-GP SRN2K2J-1-GP SRN10KJ-6-GP UMA Θ CRT_DDCCLK_CON CRT_DDCDATA_CON CRT CONN 5V_S0 3D3V_VGA_S0 UMA 2N7002DW-1-GP Θ Θ 5V_S0 4 SRN1K5J-GP SRN2K2J-1-GP DIS DDC2CLK GPU_HDMI_CLK DDC2DATA GPU_HDMI_DATA DDC_CLK_HDMI TSCBTD3305CPWR HR UMA HDMI CONN DDC_DATA_HDMI Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C SRN0J-6-GP Title SMBUS Block Diagram Size A2 DIS A Date: B C D Document Number Rev -1 JE40-HR Thursday, December 02, 2010 E Sheet 101 of 102 A B C D Thermal Block Diagram E Audio Block Diagram 1 SPKR_PORT_D_LPAGE28 DXP SPEAKER SPKR_PORT_D_R+ P2800_DXP MMBT3904-3-GP SC2200P50V2KX-2GP UMA Thermal P2800 DXN P2800_DXN Codec 92HD79B1 Place near CPU PWM CORE HP OUT HP1_PORT_B_L HP1_PORT_B_R MMBT3904-3-GP GPIO5 PAGE27 KBC NPCE795P GPIO92 SYS_THRM TDR CPU_THRM TDL T8 OTZ THERM_SYS_SHDN# 2N7002 PURE_HW_SHUTDOWN# IMVP_PWRGD G Put under CPU(T8 HW shutdown) GPIO4 GPIO94 GPIO56 VGA_THRM EN D S VR TDR MIC IN HP0_PORT_A_L PAGE28 P2800_VGA_DXP HP0_PORT_A_R THRMDA DXP VREFOUT_A_OR_F FAN_TACH1 FAN1_DAC 3V/5V PGOD TACH FAN VGA Thermal P2800 SC2200P50V2KX-2GP SC2200P50V2KX-2GP VGA P2800_VGA_DXN THRMDC DXN Place near GPU(DISCRETE only) Digital MIC DMIC_CLK/GPIO1 MMBT3904-3-GP VIN 5V DMIC0/GPIO2 3 PH VIN OTZ VSET VOUT FAN CONTROL P2793 PORTC_L Analog MIC PORTC_R PAGE28 VREFOUT_C HR UMA 4 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Thermal/Audio Block Diagram Size Custom Date: A B C D Document Number JE40-HR Thursday, December 02, 2010 Rev -1 Sheet E 102 of 102 ... VSS VSS VSS 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 12 7 12 8 13 3 13 4 13 8 13 9 14 4 14 5 15 0 15 1 15 5 15 6 16 1 16 2 16 7 16 8 17 2 17 3 17 8 17 9 18 4 18 5 18 9 19 0 19 5 19 6 205 206 SO-DIMMB... VSS 1D5V_S3 C1409 SCD1U50V3KX-GP 75 76 81 82 87 88 93 94 99 10 0 10 5 10 6 11 1 11 2 11 7 11 8 12 3 12 4 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD 11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18... DQ 61 DQ62 DQ63 M_A_RAS# M_A_WE# M_A_CAS# 15 17 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 12 9 13 1 14 1 14 3 13 0 13 2 14 0 14 2 14 7 14 9 15 7 15 9 14 6 14 8 15 8 16 0 16 3 16 5