Chương 3 họ vi điều khiển 8051

CHƯƠNG HỌ VI ĐiỀU KHIỂN 8051 Kiến trúc phần cứng 8051 8051 Pin Diagram PDIP/Cerdip P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD)P3.0 (TXD)P3.1 (INT0)P3.2 (INT1)P3.3 (T0)P3.4 (T1)P3.5 (WR)P3.6 (RD)P3.7 XTAL2 XTAL1 GND 10 11 12 13 14 15 16 17 18 19 20 8051 (8031) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vcc P0.0(AD0) P0.1(AD1) P0.2(AD2) P0.3(AD3) P0.4(AD4) P0.5(AD5) P0.6(AD6) P0.7(AD7) EA/VPP ALE/PROG PSEN P2.7(A15) P2.6(A14) P2.5(A13) P2.4(A12) P2.3(A11) P2.2(A10) P2.1(A9) P2.0(A8) Writing “1” to Output Pin P1.X Read latch Vcc TB2 write a to the pin Internal CPU bus D Write to latch Clk Q Load(L1) P1.X pin P1.X Q output pin is Vcc M1 TB1 Read pin 8051 IC output Writing “0” to Output Pin P1.X Read latch Vcc TB2 write a to the pin Internal CPU bus D Write to latch Clk Q Load(L1) P1.X pin P1.X Q output pin is ground M1 TB1 Read pin 8051 IC output Reading “1” at Input Pin Read latch TB2 write a to the pin MOV P1,#0FFH Internal CPU bus D Write to latch Clk Q MOV A,P1 Vcc Load(L1) 1 P1.X Q M1 TB1 Read pin Read pin=1 Read latch=0 Write to latch=1 8051 IC external pin=High P1.X pin ... XTAL1 GND 10 11 12 13 14 15 16 17 18 19 20 8051 (8 031 ) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vcc P0.0(AD0) P0.1(AD1) P0.2(AD2) P0 .3( AD3) P0.4(AD4) P0.5(AD5) P0.6(AD6) P0.7(AD7)... cứng 8051 8051 Pin Diagram PDIP/Cerdip P1.0 P1.1 P1.2 P1 .3 P1.4 P1.5 P1.6 P1.7 RST (RXD)P3.0 (TXD)P3.1 (INT0)P3.2 (INT1)P3 .3 (T0)P3.4 (T1)P3.5 (WR)P3.6 (RD)P3.7 XTAL2 XTAL1 GND 10 11 12 13 14... P0 .3 P0.4 8951 P0.5 P0.6 P0.7 10 K Reading ROM (1/2) PSEN ALE P0.0 P0.7 7 437 3 latches the address and send to ROM Send address to ROM 74LS3 73 G D Address OE OC A0 A7 D0 D7 EA P2.0 A8 P2.7 A12 8051