Luận án tiến sĩ nghiên cứu noc cấu hình lại được trên FPGA và phát triển thuật toán ánh xạ động ứng dụng trên nền tảng noc

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B GIO DC V O TO TRNG I HC BCH KHOA H NI NGUYN VN CNG NGHIấN CU NoC CU HèNH LI C TRấN FPGA V PHT TRIN THUT TON NH X NG NG DNG TRấN NN TNG NoC LUN N TIN S K THUT IN T H Ni 2017 B GIO DC V O TO TRNG I HC BCH KHOA H NI NGUYN VN CNG NGHIấN CU NoC CU HèNH LI C TRấN FPGA V PHT TRIN THUT TON NH X NG NG DNG TRấN NN TNG NoC Chuyờn ngnh: K thut in t Mó s: 62520203 LUN N TIN S K THUT IN T NGI HNG DN KHOA HC: PGS TS PHM NGC NAM H Ni 2017 i LI CAM OAN Tụi xin cam oan rng cỏc kt qu khoa hc c trỡnh by quyn lun ỏn ny l kt qu nghiờn cu ca bn thõn tụi sut thi gian lm nghiờn cu sinh v cha tng xut hin cụng b ca cỏc tỏc gi khỏc Cỏc kt qu nghiờn cu l chớnh xỏc v trung thc Giỏo viờn hng dn H Ni, ngy 08 thỏng 05 nm 2017 Tỏc gi PGS TS Phm Ngc Nam Nguyn Vn Cng ii LI CM N u tiờn, tụi xin by t li cm n sõu sc v kớnh trng n thy giỏo PGS TS Phm Ngc Nam, ngi ó hng dn v nh hng khoa hc cho tụi sut khúa hc Cm n cỏc thnh viờn nhúm NoC ca Lab ESRC ó h tr v cựng tụi thc hin mt s thớ nghim lun ỏn ny Tụi xin trõn trng cm n Ban Lónh o, quý thy cụ v cỏn b, chuyờn viờn Vin in t Vin thụng, B mụn in t v K thut mỏy tớnh v Vin o to Sau i hc ó to cỏc iu kin thun li v ni hc tp, nghiờn cu, cỏc th tc hnh chớnh v gúp ý chuyờn mụn cho tụi sut quỏ trỡnh hc v nghiờn cu ti trng i hc Bỏch khoa H Ni Tụi cng xin trõn trng cm n Ban Giỏm hiu trng i hc Cụng nghip Tp.HCM, Ban Lónh o v ng nghip ca tụi ti Phõn hiu Qung Ngói ó to cỏc iu kin thun li v thi gian tụi hc v nghiờn cu ti trng i hc Bỏch khoa H Ni Xin cm n cỏc nghiờn cu sinh ó quan tõm v ng viờn tụi sut khúa hc Cui cựng, tụi xin by t lũng bit n n gia ỡnh, c bit l v v cỏc ca tụi Nhng ngi ó luụn ng viờn v giỳp tụi sut thi gian va qua õy cng l ng lc ln nht tụi vt qua cỏc khú khn v hon thnh lun ỏn ny Tỏc gi iii MC LC LI CAM OAN i LI CM N ii MC LC iii DANH MC CC T VIT TT vii DANH MC CC HèNH V, TH x DANH MC CC BNG BIU xii M U 1 t Mc tiờu, i tng, phng phỏp v phm vi nghiờn cu 3 Cỏc kt qu t c ca lun ỏn Cu trỳc ca lun ỏn CHNG C S Lí THUYT 1.1 Lý thuyt v mng trờn chip 1.1.1 Ngun gc v thut ng .7 1.1.2 Cu hỡnh mng 1.1.2.1 Mng li n-chiu (n-Dimensional Mesh) 1.1.2.2 Mng K-ary n-cube 1.1.2.3 Mng cú s chiu thp 10 1.1.3 C ch iu khin lung 10 1.1.3.1 Bn tin 10 1.1.3.2 C ch iu khin lung Store-and-Forward (SAF) 11 1.1.3.3 C ch iu khin lung Wormhole (WH) 11 1.1.3.4 C ch iu khin lung Virtual cut-through (VCT) 12 1.1.3.5 C ch iu khin lung kờnh o (Virtual Channel) 12 1.1.4 Thut toỏn nh tuyn 13 1.1.4.1 Phõn loi nh tuyn 13 1.1.4.2 Cỏc nh tuyn 14 1.1.5 Tng quan kin trỳc b nh tuyn 14 1.2 Cụng ngh FPGA 16 iv 1.2.1 Kin trỳc FPGA 17 1.2.1.1 Tng quan kin trỳc FPGA 17 1.2.1.2 Kin trỳc FPGA ca Xilinx 18 1.2.2 Cu hỡnh li tng phn 19 1.2.2.1 Cu hỡnh li tng phn ng 21 1.2.2.2 Cỏc u im ca cu hỡnh li tng phn 22 1.2.2.3 H tr cu hỡnh li FPGA ca Xilinx 23 1.3 K thut ỏnh x ng dng lờn nn tng mng trờn chip 24 1.3.1 Bi toỏn ỏnh x 24 1.3.2 nh x ti thi gian thit k 25 1.3.3 nh x ti thi gian chy 26 1.4 Kt lun chng 26 CHNG PHT TRIN NN TNG PHN CNG CU HèNH LI C CHO NoC 2.1 28 Thit k b nh tuyn cho NoC 28 2.1.1 Gii thiu 28 2.1.2 xut kin trỳc b nh tuyn 29 2.1.2.1 La chn cỏc thụng s thit k 29 2.1.2.2 B m ngừ vo 32 2.1.2.3 B gii mó flit 32 2.1.2.4 Chuyn mch v kờnh o 33 2.1.2.5 B phõn x 34 2.1.3 Kt qu v ỏnh giỏ 34 2.1.3.1 Kt qu tng hp 35 2.1.3.2 Kt qu mụ phng 36 2.2 Thit k b giao tip mng cho NoC 40 2.2.1 Gii thiu 40 2.2.2 Phng phỏp tip cn 40 2.2.3 xut kin trỳc b giao tip mng 42 2.2.4 Kt qu v ỏnh giỏ 44 2.3 Phỏt trin nn tng phn cng cu hỡnh li tng phn ng 45 2.3.1 Gii thiu 45 v 2.3.2 Xõy dng h thng (nn tng phn cng) cu hỡnh 47 2.3.2.1 Lung thit k 47 2.3.2.2 Thit lp h thng 48 2.3.3 Cỏc trng hp nghiờn cu 50 2.3.3.1 Cu hỡnh li c s h tng truyn thụng 50 2.3.3.2 Cu hỡnh li cỏc PE 53 2.3.4 Kt qu thc nghim 54 2.4 Kt lun chng 56 CHNG TRIN KHAI CC NG DNG Cể TH IU CHNH MC CHT LNG VO NN TNG CU HèNH LI C DA TRấN NoC TI THI GIAN CHY 57 3.1 Gii thiu 57 3.2 Mụ t bi toỏn ỏnh x 59 3.3 Cỏc nh ngha v xõy dng bi toỏn ỏnh x 60 3.3.1 Mụ hỡnh ng dng 60 3.3.1.1 th tỏc v ng dng 61 3.3.1.2 Mụ hỡnh cht lng 61 3.3.2 Mụ hỡnh phn cng 62 3.3.3 Xõy dng bi toỏn ỏnh x 63 3.4 Cỏc gii phỏp cho bi toỏn ỏnh x cỏc ng dng lờn NoC ti thi gian chy 65 3.4.1 Gii phỏp ti u s dng thut toỏn tỡm kim y 66 3.4.1.1 Thut toỏn 66 3.4.1.2 Kt qu mụ phng v ỏnh giỏ 67 3.4.2 Gii phỏp heuristic cho bi toỏn ỏnh x ti thi gian chy 70 3.4.2.1 Chin lc chn vựng gn li 70 3.4.2.2 Thut toỏn ỏnh x heuristic 73 3.4.2.3 Kt qu mụ phng v ỏnh giỏ 75 3.5 Kt lun chng 82 KT LUN 83 Ni dung v cỏc kt qu t c ca lun ỏn 83 úng gúp khoa hc ca lun ỏn 84 vi Hng phỏt trin ca lun ỏn 85 DANH MC CC CễNG TRèNH CễNG B CA LUN N 86 TI LIU THAM KHO 87 vii DANH MC CC T VIT TT Ký hiu ABP ACMD Ngha ting Anh ca t vit tt Adaptive BackPressure Average Communication Manhattan Distance AMD Average Manhattan Distance ARM ATG AXI C2R CAGR CF CLB CMPS CPU DDR Advanced RISC Machine Application-Specific Integrated Circuit Application Task Graph Advanced eXtensible Interface Core to Router Compound Annual Growth Rate CompactFlash Configurable Logic Block Chip Multi-Processors Central Processing Unit Double Data Rate DDRAM Double Data Rate RAM DMA DP DPR DSP DT EDK FF FFT FIFO Direct Memory Access Dynamic Part Dynamic Partial Reconfigurable Digital Signal Processor Design-time Embedded Development KIT First Fit Fast Fourier Transform First In First Out FPGA Field Programmable Gate Array FT Flit Type GPIO General Purpose Input Output HDL Hardware Description Language ASIC HTTP-VS HTTP video streaming HW/SW Hardware/Software Ngha ting Vit Khong cỏch Manhattan truyn thụng trung bỡnh Khong cỏch Manhattan trung bỡnh Vi x lý ARM Vi mch tớch hp chuyờn dng th tỏc v ng dng Giao din m rng tiờn tin T lừi IP n b nh tuyn Tc tng trng kộp hng nm B nh flash Khi Logic cu hỡnh Chip a x lý n v x lý trung tõm Tc d liu kộp B nh truy cp ngu nhiờn tc d liu kộp Truy nhp b nh trc tip Phn ng Cu hỡnh li tng phn ng X lý tớn hiu s Thi gian thit k B cụng c phỏt trin nhỳng Thut toỏn ỏnh x first fit Bin i Fourier nhanh Vo trc trc Mng cỏc cng cú th lp trỡnh ti ch Loi flit Cỏc giao tip vo mc ớch chung Ngụn ng mụ t phn cng Truyn ti video qua giao thc http Phn cng/Phn mm viii Ký hiu IC Ngha ting Anh ca t vit tt Integrated Circuit ICAP Internal Configuration Access Port InP IP ISE ISP JTAG LCD LE LUT MD MPEG-4 MPSoC MWD NI Indefinite Postponement Intellectual Property (IP Core) Integrated Software Environment Instruction Set Processor Joint Test Action Group Cable Liquid Crystal Display Logic Element Logic Look-up Table Manhattan Moving Picture Experts Group Multiprocessor System on Chip Multi-Window Display Network Interface NN Nearest Neighbor NoC OB PC PCB PE PIP PL PLB PLD PR QoS R2C RAM RI RPA RR RT RTL SAF Network-on-Chip Overall Benefit Personal Computer Printed circuit board Processing Element Picture In Picture Programmable Logic Processor Local Bus Programmable Logic Device Partial Reconfiguration Quality of service Router to Core Random Access Memory Routing Information Reprogrammability Reconfigurable Region Run-time Register Transfer Level Store-And-Forward SDK Software Development KIT SN Sequence Number Ngha ting Vit Mch tớch hp Cng truy nhp cu hỡnh bờn Trỡ hoón khụng xỏc nh Lừi s hu trớ tu Mụi trng phn mm tớch hp Vi x lý lnh Cỏp JTAG Mn hỡnh tinh th lng Phn t logic Bng tra logic Khong cỏch Manhattan H thng a x lý trờn chip B giao tip mng Thut toỏn ỏnh x nearest neighbor Mng trờn chip Giỏ tr li ớch tng th Mỏy tớnh cỏ nhõn Bng mch in Phn t x lý (tớnh toỏn) Logic lp trỡnh Thit b logic kh trỡnh Cu hỡnh li c tng phn Cht lng dch v T b nh tuyn n lừi IP B nh truy cp ngu nhiờn Thụng tin nh tuyn Kh nng lp trỡnh li Vựng cu hỡnh li c Thi gian chy Mc truyn ghi B cụng c phỏt trin phn mm ca Xilinx S th t 79 Bng 3.6 Giỏ tr ACMD ỏnh x cỏc ng dng lờn nn tng 5x5, 6x6 v 7x7 Thut toỏn 5x5 CV_NF 6x6 CV_TG CV_NF 7x7 CV_TG CV_NF CV_TG FF 2,070 1,874 2,237 1,845 2,296 1,870 NN 1,828 1,713 2,053 1,773 2,158 1,771 Chen 1,860 1,691 2,106 1,742 2,164 1,850 Tỏc gi 1,592 1,430 1,763 1,496 1,866 1,521 Giỏ tr AMD v ACMD ca cỏc ng dng trin khai lờn cỏc nn tng vi kớch thc khỏc (5x5, 6x6 v 7x7) theo cỏc thut toỏn ỏnh x khỏc c ch nh Bng 3.5, Bng 3.6, Hỡnh 3.11 v Hỡnh 3.12 Cỏc giỏ tr AMD v ACMD c ct gim ln lt theo thut toỏn heuristic v chin lc chn vựng ca tỏc gi bi vỡ thut toỏn ỏnh x ca tỏc gi xut ó xem xột ti u cho c hai iu kin ú l khong cỏch MD v tr truyn thụng gia cỏc cp tỏc v ca ng dng iu ny cng cú ngha rng, thut toỏn ca tỏc gi cú tr v tiờu th nng lng thp hn so vi cỏc thut toỏn khỏc 0,003 Giỏ tr AMD 0,002 0,002 FF NN 0,001 Chen Tỏc gi 0,001 0,000 CV_NF CV_TG CV_NF CV_TG CV_NF CV_TG 5x5 6x6 7x7 Chin lc chn vựng, kớch thc nn tng Hỡnh 3.11 Giỏ tr AMD ca cỏc ng dng ó c ỏnh x theo cỏc thut toỏn khỏc 80 0,003 Giỏ tr ACMD 0,002 0,002 FF NN 0,001 Chen Tỏc gi 0,001 0,000 CV_NF CV_TG CV_NF CV_TG CV_NF CV_TG 5x5 6x6 7x7 Chin lc chn vựng, kớch thc nn tng Hỡnh 3.12 Giỏ tr ACMD ca cỏc ng dng ó c ỏnh x theo cỏc thut toỏn c) ỏnh giỏ hiu qu chin lc chn vựng NF v ca tỏc gi Chn mt vựng gn li sau ú ỏnh x cỏc ng dng vo nú khụng nhng mang li li ớch v hiu nng, chng phõn mnh cho cỏc PE trờn nn tng phn cng nh ó phõn tớch trờn m cũn giỳp trin khai nhanh cỏc ng dng lờn h thng, ny rt quan trng cho mt h thng qun lý ng Tip theo, thi gian chy ca thut toỏn chn vựng v t l ca cỏc thụng s OB, AMD, ACMD gia chin lc chn vựng ca tỏc gi xut v NF s c ỏnh giỏ Thi gian chy thut toỏn chn vựng c thng kờ theo giỏ tr trung bỡnh trin khai cỏc ng dng lờn cỏc nn tng vi kớch thc khỏc ln lt l 5x5, 6x6, 7x7, 8x8, 9x9 v 10x10 i vi mt nn tng xỏc nh, tỏc gi chy 2000 ln vi tng s tỏc v ca cỏc ng dng thay i t (x*y) n (x*y +5) Vớ d, vi nn tng cú kớch thc 5x5, thc hin chy 2000 ln cho cỏc ng dng cú tng s tỏc v thay i t 25 n 30 Kt qu thi gian chy thut toỏn chn vựng c ch nh Bng 3.7 Do chin lc chn vựng ca tỏc gi xut s dng mt k thut n gin hn nờn cú thi gian chy nh hn so vi NF hay núi cỏch khỏc chin lc ca tỏc gi xut cú phc tớnh toỏn nh hn 81 Bng 3.7 Thi gian chy trung bỡnh ca cỏc chin lc chn vựng Thi gian chy trung bỡnh (ms) Kớch thc nn tng S tỏc v 5x5 2530 CV_NF 0,1165 6x6 3641 7x7 CV_TG Gain (%) 0,0704 -39,55 0,2129 0,1018 -52,20 4954 0,3913 0,1302 -66,72 8x8 6469 0,6970 0,1722 -75,30 9x9 8186 1,3365 0,2099 -84,29 10x10 100105 2,2836 0,2564 -88,77 Tip theo, tỏc gi ỏnh giỏ tớnh hiu qu cho cỏc chin lc chn vựng thụng qua t s ca cỏc giỏ tr OB, AMD v ACMD gia chin lc chn vựng ca tỏc gi trờn chin lc chn vựng NF Hỡnh 3.13 cho thy li ớch thu c t chin lc chn vựng ca tỏc gi so vi NF i vi cỏc giỏ tr OB, AMD v ACMD Tt c cỏc giỏ tr OB, AMD v ACMD c ci thin i vi trng hp nn tng cú kớch thc 5x5, giỏ tr OB c ci thin trung bỡnh khong 12,2%; cỏc giỏ tr AMD v ACMD gim trung bỡnh ln lt 8,6% v 8,3% Vi nn tng cú kớch thc 6x6, giỏ tr OB tng trung bỡnh khong 39,8%; giỏ tr AMD v ACMD gim trung bỡnh ln lt 16,6% v 15,9% Tng t, trng hp nn tng cú kớch thc 7x7, cỏc giỏ tr ny tng v gim trung bỡnh ln lt l 46,5% v 18,2%, 17,4% Kt qu ny chng minh rng chin lc chn vựng ca tỏc gi xut mang li hiu qu cao hn so vi NF v s dng ti nguyờn, tr v tiờu th nng lng 30 OB AMD ACMD 25 Gain (%) 20 15 10 -5 FF NN Chen -10 -15 Cỏc thut toỏn ỏnh x a) Nn tng cú kớch thc 5x5 TG 82 50 40 30 OB AMD ACMD Gain (%) 20 10 -10 FF NN Chen TG -20 -30 Cỏc thut toỏn ỏnh x b) Nn tng cú kớch thc 6x6 70 60 OB AMD ACMD 50 Gain (%) 40 30 20 10 -10 FF NN Chen TG -20 -30 Cỏc thut toỏn ỏnh x c) Nn tng cú kớch thc 7x7 Hỡnh 3.13 Cỏc ci thin chin lc chn vựng ca tỏc gi 3.5 Kt lun chng Trong chng ny, bi toỏn ỏnh x cỏc ng dng cú th iu chnh mc cht lng vo nn tng cu hỡnh li ng da trờn NoC khụng ng nht cú xem xột v trớ t cỏc tỏc v ó c xõy dng bng mụ hỡnh toỏn hc Ngoi ra, cú hai gii phỏp c xut gii quyt bi toỏn ỏnh x ny bao gm mt thut toỏn phõn vựng v hai thut toỏn ỏnh x ng Kt qu t c cho thy gii phỏp ó xut cho phộp trin khai linh hot cỏc ng dng lờn nn tng phn cng cu hỡnh li c cho cht lng dch v tng th ca cỏc ng dng sau trin khai lờn nn tng t c giỏ tr cc i Cỏc úng gúp chớnh ca chng ny ó c ng ti trờn cỏc bi bỏo [HN2] v [TC3] 83 KT LUN Ni dung v cỏc kt qu t c ca lun ỏn Trong Chng 1, tỏc gi ó trỡnh by mt cỏch cú h thng cỏc ni dung kin thc liờn quan n ni dung ca lun ỏn lm c s cho nhng xut cỏc chng tip theo nh kin trỳc NoC, cụng ngh FPGA, kh nng cu hỡnh li tng phn ng ca FPGA v cỏc k thut ỏnh x cỏc ng dng lờn nn tng NoC Tỏc gi ó trỡnh by hai xut mi Chng gm mt kin trỳc ca b nh tuyn vi s lng kờnh o khụng u trờn cng v mt kin trỳc ca b giao tip mng s dng b m kộp Kt qu tng hp v mụ phng cho thy rng kin trỳc b nh tuyn t c deadlock free v ct gim ti nguyờn phn cng trung bỡnh lờn n 23,5% so vi b nh tuyn s dng kờnh o tr v thụng lng mng c m bo V mt kin trỳc b giao tip mng s dng b m kộp ó c thit k Vi kin trỳc ny, tr v thụng lng b giao tip mng c ci thin nh vo kh nng ghi c song song d liu vo/ra cỏc b m Ngoi ra, mt nn tng phn cng cú th cu hỡnh li tng phn ng cng c phỏt trin trờn FPGA da trờn cỏc kin trỳc NoC ó c xut trờn Nn tng ny cho phộp t ng cu hỡnh li cỏc mụ un cho lp truyn thụng hoc lp tớnh toỏn ca NoC Cu hỡnh li lp tớnh toỏn l cu hỡnh li cỏc lừi PE cú ng dng mi c trin khai lờn nn tng Trong lp truyn thụng, cỏc mụ un nh b m, b phõn x, chuyn mch hoc b nh tuyn hoc cu trỳc mng cng cú th c cu hỡnh li ti thi gian chy ti u kin trỳc v thớch nghi vi ti lm vic ca ng dng thay i ng Phỏt trin mt nn tng cu hỡnh li tng phn ng ny s l la chn phn cng hn trin khai cỏc ng dng cú th iu chnh mc cht lng lờn nú Kt qu t c chng ny c ch cỏc cụng trỡnh [TC1], [TC2] v [HN3] Trong Chng 3, tỏc gi ó xõy dng bi toỏn ỏnh x cỏc ng dng cú th iu chnh mc cht lng vo nn tng phn cng khụng ng nht cu hỡnh li ng da trờn NoC Cỏc gii phỏp gii quyt bi toỏn ỏnh x ó c xut bao gm ba thut toỏn ỏnh x mi Kt qu t c cho thy cỏc thut toỏn ó xut cú nhiu u im hn so vi mt vi thut toỏn ỏnh x liờn quan ó cụng b úng gúp chớnh ca chng ny c th hin cỏc cụng trỡnh [HN2] v [TC3] 84 úng gúp khoa hc ca lun ỏn úng gúp khoa hc ca lun ỏn c th hin cỏc ni dung v kt qu t c ó trỡnh by Chng v Chng 3, cú th ch nh sau: úng gúp th nht: Phỏt trin nn tng phn cng cu hỡnh li c ti thi gian chy trờn FPGA da theo kin trỳc NoC Nn tng ny cú kh nng t ng cu hỡnh li cỏc mụ un cho lp truyn thụng NoC ti u húa cu trỳc truyn thụng theo yờu cu thay i ca ng dng nhm nõng cao hiu qu s dng ti nguyờn v ci thin hiu nng mng; hoc cu hỡnh li lp tớnh toỏn cú ng dng mi trin khai lờn nn tng Ngoi ra, kin trỳc nn tng ny cng cho phộp nõng cp, sa li v thay i thit k d dng tng lai Trong úng gúp ny, cú hai kin trỳc mi c xut cho NoC: o Kin trỳc b nh tuyn vi s lng kờnh o khụng u trờn cng Kin trỳc ny ci thin chi phớ phn cng trin khai lờn FPGA m bo c hiu nng cao cho mng o Kin trỳc b giao tip mng s dng b m kộp, nú cho phộp ti u tr ghi/c d liu vo/ra b m bng k thut ghi/c song song úng gúp th hai: Xõy dng bi toỏn ỏnh x cỏc ng dng cú th iu chnh mc cht lng lờn nn tng phn cng a lừi cu hỡnh li c da trờn kin trỳc NoC v cỏc thut toỏn gii quyt bi toỏn ỏnh x ny Hng xut ny cú tớnh kh thi cao v hon ton cú th trin khai thc t nhm gúp phn ci thin tớnh nng cho cỏc thit b nhỳng Ngoi cỏc mụ hỡnh toỏn hc c xõy dng cho bi toỏn ỏnh x, tỏc gi cng ó xut ba thut toỏn mi gm: o o o Thut toỏn ỏnh x da trờn ý tng tỡm kim y , thut toỏn ny phự hp vi bi toỏn ỏnh x cú cỏc iu kin nh kớch thc nn tng phn cng nh, s lng tỏc v v s mc cht lng trờn mi ng dng nh Thut toỏn heuristic cho bi toỏn ỏnh x ng, thut toỏn ny cú kh nng gii quyt bi toỏn ỏnh x vi kớch thc mng v s lng ng dng ln; thi gian thc hin nhanh; ci thin chi phớ truyn thụng, nng lng tiờu th bng cỏch ti thiu cỏc thụng s ADM v ACDM Chin lc chn vựng v cp phỏt ti nguyờn hiu qu cho cỏc ng dng ti thi gian chy da trờn phng phỏp gúc quột hỡnh hc cng c xut 85 Hng phỏt trin ca lun ỏn Cỏc kt qu t c ca lun ỏn ch rng hng nghiờn cu phỏt trin mt nn tng khụng ng nht cu hỡnh li c tng phn ng trờn FPGA da trờn kin trỳc NoC l kh thi Gii phỏp trin khai cỏc ng dng cú th iu chnh mc cht lng vo nn tng phn cng cu hỡnh li c ti thi gian chy l tim nng S kt hp gia hai gii phỏp ny s to mt h thng linh hot v thớch nghi theo s thay i ca cỏc ng dng Nú cho phộp khai thỏc hiu qu v cõn bng gia sc mnh tớnh toỏn ca phn cng cu hỡnh v s linh hot ca phn mm Gii phỏp ny cng cho thy tớnh hiu qu ca nú m ti nguyờn ca thit b hn ch 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DỤC VÀ ĐÀO TẠO TRƢỜNG ĐẠI HỌC BÁCH KHOA HÀ NỘI NGUYỄN VĂN CƢỜNG NGHIÊN CỨU NoC CẤU HÌNH LẠI ĐƢỢC TRÊN FPGA VÀ PHÁT TRIỂN THUẬT TOÁN ÁNH XẠ ĐỘNG ỨNG DỤNG TRÊN NỀN TẢNG NoC Chuyên ngành: Kỹ thuật. .. trí đặt tác vụ vào tảng phần cứng sau ánh xạ 68 Hình 3.6 Minh họa trình ánh xạ thuật toán heuristic đề xuất 74 Hình 3.7 So sánh lợi ích chi phí theo thuật toán ánh xạ 74 Hình 3.8 Giá... điểm cấu hình lại phần 22 1.2.2.3 Hỗ trợ cấu hình lại FPGA Xilinx 23 1.3 Kỹ thuật ánh xạ ứng dụng lên tảng mạng chip 24 1.3.1 Bài toán ánh xạ 24 1.3.2 Ánh xạ thời
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