MOSFET MODELING FOR VLSI SIMULATION - Theory and Practice Episode 16 doc

12.5 Optimization Method 577 11. Minimization and maximization of the performance function under the nonlinear constraint given by Eq. (12.16) gives the slow and fast z vectors, respectively. The procedure outlined above was carried out using the same data as was used for generating WCF discussed in section 12.2. The results of optimi- zation, using Idrive as the performance function, are shown in Table 12.2. Note that the values for only few important parameters are shown. Since Idrive is a function of the model parameters and device W and L, the optimization was carried out using W = 3 pm and L = 1 pm. It should be pointed out that the parameters were obtained using two steps of optimi- zation. In the first step, parameters pertaining to the threshold voltage model were optimized. These parameters were then fixed and other parameters for Idrive were then optimized. In Table 12.2, the numbers in the bracket show standard deviation times the amount of the shift in the parameter value from their respective mean (typical) values. Note that the change in the parameter value is less than 30 for the so called four independent parameters AL, AW, Cox and Vfb. This is understandable because overall change for Idrive is the effect of other parameters too. The optimized DC parameter values shown in Table 12.2 are then used to calculate Idrive bounds. These bounds are shown as dotted line in Figure 12.2. Clearly, the optimization technique results in a more realistic WCF compared to the principal factor method. The histrogram of Idrive, for WJL, = 12.5/1 n-channel devices, based on data collected from 3 different lots (117 die locations from different wafers) for a typical 1 pm CMOS technology is shown in Figure 12.3. The vertical lines designated as TS and TF are the slow and fast bounds, respectively, generated by the principal factor method, while the corresponding bounds generated by the optimization method discussed above are designated as 0s and OF, respectively. Note from this figure that the bounds generated Table 12.2. Mean (typical), minimum (slow) and maximum (fast) valuesjor some important n-channel parameters obtained using the optimization method Parameter Mean Minimum Maximum name (Typical) (Slow) (Fast) Units AL 0.36 0.315(- 1.45)U 0.418(1.65) fl pm AW 0.79 1.02(2.53) fl 0.570( 2.29) 0 pm 2.25 2.23(-0.83) U 2.27(0.73) fl lo-’ F/cmZ cox PO 577 VFB -0.65 -0.56(2.67) fl -0.745( -2.79) U V 600.43(1.51) U 556(-1.27) fl cm2/V.s - 0.568( -0.69) - 00 0.642 0.7 l(0.67) 578 12 Statistical Modeling and Worst-case Design Parameters N NI OF TF m 3 2 v M UN c- gE: u m 0 -s N 0 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 Ids(mA) Fig. 12.3 Histogram showing variation of Idrive measured from different wafers and lots on n-channel devices. TF and TS are the Fast (best) and Slow (worst) bounds, respectively, based on principal factor method, while the corresponding bounds based on optimization method are shown as OF and OS, respectively by the principal factor method are 8-1 1 % higher compared to the optimization method. Although optimization method generates realistic WCF, however, it needs large amount of statistically meaningful data that is not always available. Same is the case with the Factor rotation method. To a first approximation, WCF could be generated using principal factor method. In the latter approach, it is more appropriate to replace Vfb as independent parameter by N,, the bulk concentration. References [l] R. Spence and R. S. Soin, Tolerance Design of Electronic circuits, Addison-Wesley Publishing Co., Reading, MA, 1988. [2] P. Yang and P. Chatterjee, ‘Statistical modeling of small geometry MOSFET’, IEEE- IEDM82, Tech. Digest, pp. 286-289 (1982). [3] P. Cox, P. Yang, S. S. Mahant-Shetti, and P. Chatterjee, ‘Statistical modeling for efficient parametric yield estimation of MOS VLSI circuits’, IEEE Trans. Electron Devices, ED-32, pp. 471-478 (1985). [4] N. Herr and J. J. Barnes, ‘Statistical circuit simulation modeling of CMOS VLSI’, IEEE Trans. Computer Aided Design, CAD-5, pp. 15-22 (1986). [5] J. P. Spoto, W. T. Coston, and C. P. Hernandez, ‘Statistical integrated circuit design and characterization’, IEEE Trans. Computer Aided Design, CAD-5, pp. 91-103 (1986). References 579 [6] T. K. Yu, S. M. Kang, I. N. Hajj, and T. N. Trick, ‘Statistical performance modeling and parametric yield estimation of MOS VLSI’, IEEE Trans. Computer Aided Design, [7] P. Tuohy, A. Gribben, A. J. Walton, and J. M. Robertson, ‘Realistic worst-case parameters for circuit simulation’, IEEE Proc., 134, Pt. I, pp. 137-140 (1987). [8] S. Inohira, T. Shinmi, M. Nagata, T. Toyabe, and K. Iida, ‘A statistical model including parameter matching for analog integrated circuits simulation,’ IEEE Trans. Computer Aided Design, CAD-4, pp. 621-628 (1985). [9] M. Pelgrom, A. Duinmaijer, and A. Welbers, ‘Matching properties of MOS transistor’, IEEE J. Solid-state Circuits, 24, pp. 1433-1439 (1989). [lo] C. Michael and M. Ismail, ‘Statistical modeling of device mismatch for analog MOS integrated circuits’, IEEE J. Solid-state Circuits, 27, pp. 154-166 (1992). [11] L. A. Glasser and D. W. Doubberpuhl, The Design and Analysis of VLSI Circuits, Addison-Wesley Publishing Co., Reading, MA, 1985. [12] W. Maly and A. J. Strojwas, ‘Statistical simulation of the IC manufacturing process’, IEEE Trans. on Computer Aided Design, CAD-1, pp. 120-131 (1982). [I31 S. R. Nassif, A. J. Strojwas, and S. W. Director, ‘FABRICHSII: A statistical based IC fabrication process simulator,’ IEEE Trans. on Computer Aided Design, CAD-3, pp. 40-46 (1984). Also see Report (Feb. 1990) on FABRICS 11: ‘A statistical simulator of the IC manufacturing process’, Department of Electrical Engineering, Carnegie- Mellon University, Pittsburgh, PA, 15213. [14] S. R. Nassif, A. J. Strojwas, and S. W. Director, ‘A methodology for worst-case analysis of integrated circuits’, IEEE Trans. on Computer Aided Design, CAD-5, pp. 104-1 13 (1 986). CAD-6, pp. 1013-1022 (1987). [lS] D. G. Rees, ‘Foundations ofStatistics’, Chapman and Hall, New York, 1987. [16] R. E. Walpole and R. H. Myers, Probability and Statisticsfor Engineers and Scientists, McGraw Hill, New York, 1976. [17] C. W. Helstrom, Probability and Stochastic Processes for Engineers, Macmillan Publishing Company, New York, 1984. [18] N. D. Arora and L. M. Richardson, ‘MOSFET modeling for circuit simulation’ in Advanced MOS Device Physics (N. G. Einspruch and G. Gildenblat, eds.), VLSI Electronics: Microstructure Science, Vol. 18, pp. 236-276, Academic Press Inc., New York, 1989. [19] V. Bernett and T. Lewis, ‘Outliers in Statistical Data, John Wiley & Sons, New York, 1978. [20] J. A. Power, A. Mathewson, and W. A. Lane, ‘MOSFET statistical parameter extraction using multivariate statistics’, 1991 Int. Conf. Microelectronics Test Structures, 4, [21] M. Bolt, M. Rocchi, and J. Engel, ‘Realistic statistical worst-case simulations of VLSI circuits’, IEEE Trans. Semicond. Manuf., 4, pp. 193-198 (1991). [22] D. A. Divekar, R. W. Dutton, and W. J. McCalla, ‘Experimental study of Gummel- Poon Model parameter correlations for bipolar junction transistors’, IEEE Journal of Solid-state Circuits, SC-12, pp. 552-559 (1977). [23] A. A. Afifi and V. Clark, Computer-Aided Multivariate Analysis, Lifetime Learning Publications, Belmont, CA, 1984. [24] J. Vlach and K. Singhal, Computer Methods for Circuit Analysis and Design, Van Nostrand Rienhold Company, New York, 1983. [25] D. F. Morrison, Multivariate Statistical Methods, McGraw-Hill Book Company, New York, 1976. [26] R. A. Johnson and D. W. Wichern, Applied Multivariate Statistical Analysis, Prentice- Hall Inc., Englewood Cliffs, New Jersey, 1982. [27] M. E. Johnson, Multivariate Statistical Simulation, John Wiley & Sons, New York, 1987 pp. 209-214 (1991). (P. 52). Appendix Appendix A. Important Properties of Silicon, Silicon Dioxide and Silicon Nitride at 300 K Property Si SiO, Si,N, Units Atomic number Molecular weight Density at 300 K Relative permittivity Breakdown field Refractive index Thermal conductivity Lattice constant Intrinsic carrier Intrinsic Debye (Dielectric constant) (Dielectric strength) Energy gap E, concentration ni length 14 28.29 60.08 2.33 2.27 11.7 3.9 - 3 x los 8 x lo6 3.42 1.46 1.412 0.014 5.43 1 1.12 8.0 1.45 x lo1’ - 2.4~ lo-’ - ~ 140.28 g/mol 3.0 g/cm - 7-7.5 ~ 1 x lo7 V/cm 2.05 - - W1cm.K A cm- ’ 5.0 eV - cm - Bulk electron 1350 2-30 - cm2/V.s Bulk hole 480 - - cm2/V.s mobility p, mobility pD Appendix D 58 1 Appendix B. Some Important Physical Constants at 300K ~~ Constant Symbol Magnitude Units Electronic charge Free-electron mass Boltzmann’s Constant Planck’s Constant Permittivity of free space Thermal voltage at 300 K Thermal energy at 300 K 4 1.602 x lop” C m 9.11 x g k 1.38 x J/K 8.62 x lo-’ eV/K h 6.25 10-34 J-s €0 8.854 x F/cm kT 0.02586 eV V, = kT/q 0.02586 V Appendix C. Unit Conversion Factors 1 pm 1 nm Icm =10-8A 1 mil = 25.4pm = inches 1 eV 0°C =273K (micrometer or micron) = 10-6meters = 10-~cm = 104A (nanometer) = 10-9 meters = 10-7 cm = 10-~ pm = 108, = 1.602 x 10-”J = 3.83 x Cal= 1.78 x 10-36Kg Appendix D. Magnitude Prefixes Magnitude. prefix Multiple factor Symbol atto femto pic0 nano micro milli centi Kilo Mega Giga Tera 10-15 10-9 10-3 103 109 10- l2 10-6 10-2 lo6 1oI2 a f P P m K M G T n C 582 Appendix Appendix E. Methods of Calculating 4s from the Implicit Rearranging Eq. (6.30) for q5s yields Eq. (6.23) or (6.30) Assume 4: is an initial guess of 4s then the next value of the estimate of 4s is given by the Schroder series expression [1] Y” (3y”)Z - y’y”’ K3 4s= +,”+ K KK2 + 2Y’ 6(Y‘I2 1Oy’y”y’’’ - (y’)’~’’’’ - 15(y”)3 + K4 24(Y‘I3 where only the first 5 terms in the series are shown and taken into account. The prime on y denotes the order of the derivative of the function f(4,) [cf. Eq. (6.31)] given by Y ~=f(4~)=O and K= Y’ Note that the first two terms of the series correspond to the Newton- Raphson iteration. The other 3 terms are smaller, but their contribution is significant in weak inversion. A good initial guess for the surface potential is suggested [2] where and 4ss is 4s in weak inversion given by Eq. (6.90). That is, The semi-empirical Eq. (E.3) is such that in strong inversion #: M v,b + V, and in weak inversion 4: M 4ss; therefore, it follows the general behavior Appendix F 583 of the surface potential 4s. The absolute value sign in Eq. (4) is to prevent the argument of the logarithm from becoming negative in weak inversion. With the initial guess given by Eq. (E.3), an accurate estimation of C#Is is obtained in all the regions of device operation using Eq. (E.2). Only one or two iterations are normally required. Other non-iterative approaches for calculating 4s, such as storing values of 4s in a 2-D array [3], or approximating the potential using cubic spline functions [4], have also been proposed. An approximate solution of Eq. (E.l) in different regimes of device operation has also been suggested. Since in strong inversion, defined as Vgb > Vgbh, the logarithm term varies very little, an approximate expression for 4s is given by 4,(strong inversion) % 24f + V,, + 6Vt. (E.6) A better estimate (within 1% of the exact solution) for 4, in strong inversion is obtained by substituting (E.3) in the right hand side of Eq. (E.1). For weak inversion region, defined as vgb < Vgbm, 4s is given by Eq. (E.5). A better estimate can be found by substituting C#Iss in Eq. (E.1). However, for moderate inversion, no simple relationship exist. References A. M. Ostrowsky, Solutions of Equations and Systems of Equations, Academic Press, New York, 1973. C. Turchetti and G. Masetti, ‘A CAD-oriented analytical MOSFET model for high- accuracy applications,’ IEEE Trans. Computer-Aided Design, CAD-3, pp. 117-i22 (19841 S. Yu, A. F. Franz, and T. G. Mihran, ‘A physical parametric transistor model for CMOS circuit simulation’, IEEE Trans. Computer-Aided Design, CAD-7, pp. 1038-1052 (1988). H. J. Park, P. K. KO, and C. Hu, ‘A charge sheet capacitance model of short channel MOSFET’s for SPICE, IEEE Trans. Computer-Aided Design, CAD-10, pp. 376-389 (1991). Appendix F. Charge Based MOSFET Intrinsic Capacitances In this appendix, the expressions for the intrinsic capacitances for large and wide device will be presented. These capacitances are based on the charge equations given in section 7.3 and the definition of the capacitance equation (7.40). In order to write the equations in a tractable form we first define [1] [1] [2] [3] [4] 584 Appendix some auxiliary functions D =- avbs a vth Duth = ~ a vbs 5Vgt - 2h1 w= Jg- hl 12h2 12h2 Linear Region. The gate capacitances based on Eq. (7.58) can be written as 1 (f2 'ds + 2f3) - f3 I/ds(fl + 0.5f3) C,, = - = Cox, [ - 0.5 - a VS 12h1 12h: F.2) 1 [ + hl vds(Duth + 0.5f2) 12hi - cox, __ cGB= ~QG a vb c,,= aQG - Coxz[ - 0.5 + (" + x)] a vd 6h2 24hi hl Vds Note that the sum of all the four capacitances CGS, CGB, CGD and CGG is zero. The bulk capacitances based on Eq. (7.60) can be written as f4( 1 - 24 + 2h, h4 12h2 Duth + 0.5( - h4 + 12) + + Clh4(f1 + o.sf,)] c B=-c aQ a VS BS - 12hi F.3) 6h2 24h: C -&=Cox,[ -DUth-O.5f2- - 12h2 12hi BB - a Vb Appendix F The drain capacitances based on Eq. (7.55) can be written as 8QD C,, = = 0.5COxt a vg 585 Saturation Region. Differentiating Eq. (7.61~) with respect to V,, V,, V, and Vg Yields the corresponding capacitances C,,, C,,, C,, and C,,, respectively, which are shown below: Again, differentiating (7.61d) with respect to V,, V,, V, and Vg we get the corresponding capacitances C,,, C,,, C,, and C,,, respectively, which are given by the following equations CBB=Coxt -d 3a [ vth 586 Appendix The transcapacitances corresponding to the drain charge will be cDS= -ACoxtfl CDB = &CoxtDuth F.7) CDD = 0 CDG = - &Cox*. Subthreshold Region. V1 VJb + Vbs. Differentiating Eq. (F.7) w.r.t Vs, Vb, V, and V, we get the corresponding capacitances CGs, CGB, CGD and CGG in the subthreshold region. where 91 = JY2 + 4wgs - Vl) and 1 91 92 = - Y + - CY2 + wgs - VAI. The channel charge is zero in the subthreshold region and therefore the gate and drain charges will also be zero resulting in CDs=O; CDB=O; CDD=O; CDG=O and also Since the channel charge is zero therefore the bulk charge is [...]... capacitances, 48 4-4 88 intrinsic capacitances, 47 7-4 84 on-chip, 47 7-4 8 1 off-chip,48 1-4 84 inversion layer mobility: current method, 44 8-4 52 split C-V method, 45 2-4 57 saturation voltage, 47 2-4 77 Subject Index low currents, 408 subthreshold slope, 44 7-4 48 substrate current, 40 5-4 07 Measurement of doping profile: C-V method (MOS capacitor), 42 8-4 34 C-V method (MOSFET) , 43 4-4 36 DC method (MOSFET) , 43 6-4 38 four-point... device, 27 0-2 76 in Ihantola-Moll model, 25 1-2 53 in Pao-Shah model, 23 5-2 38 in piece-wise models, 24 9-2 56 in short-channel models, 28 7-3 10 in strong inversion, 24 5-2 59 in weak inversion, 25 9-2 65, 30 5-3 07 temperature effects, 31 3-3 17 Drain induced barrier lowering, 21 0-2 19 measurement of, 44 5-4 47 Drain series resistance, 10 2-1 07, 31 0-3 12 Drift velocity, 29 Effective mass, 18 Effective mobility, 27 6-2 89 Effective... diffused drain, 9 6-9 7 speed, 86 MOSFET degradation: impact on circuit performance, 39 4-3 96 mechanism, 38 3-3 88 measurement of, 38 8-3 94 simulation program, 39 4-3 95 Narrow width devices, 195 Narrow channel effects, 20 5-2 10 combined with short-channel effects, 21 9-2 21 nMOST (n-channel MOS transistor), 70 Nonquasi-static modeling, 360 Nonuniform doping, 40, 9 4-9 5, 17 9-1 81 measurement of, 42 7-4 38 Normal (Gaussian)... region, 24 7-2 50, 29 5-3 02 Scaling laws: constant field, 87 constant voltage, 89 Sheet resistance, 34 Short-channel effects, 19 5-2 05 Short-channel devices, 8 7-8 8, 194 Small signal conductances, diode, 57 MOSFET, 8 4-8 5, 36 0-3 62 Small signal equivalent circuits diode, 6 2-6 3 MOSFET, 117 Source resistance, 10 2-1 07, 31 0-3 12 SPICE Diode model, 53 6-5 39 SPICE MOSFET models, 54 2-5 59 level 1, 54 2-5 47 level 2, 54 8-5 5... layer mobility, 31 4-3 16 junction capacitances, 66 substrate current, 39 6-3 97 threshold voltage, 22 1-2 25 Thermal voltage, 19 Threshold voltage: anomalous effect, 20 3-2 05 body-effect, 176 defined in MOS capacitor, 74 MOSFET, 144, 16 7-1 69 drain voltage, effect on, 21 0-2 19 in ion-implanted channels, 17 7-1 94 in narrow-width devices, 20 5-2 10 in short-channel devices, 19 5-2 03 measurement of, 43 8-4 43 constant current... method, 45 2-4 57 surface, 233 temperature effects, 31 4-3 16 Model parameter extraction, 50 1-5 04 confidence intervals in, 52 2-5 26 using linear methods, 502 using optimization methods: 50 1-5 03, 53 1-5 34, 53 6-5 38 basics definition in, 50 4-5 09 Gauss-Newton, 51 1-5 12 local minima in, 521 Lavenberg-Marquardt, 5 1 2-5 13 multiple targets, 51 8-5 20 steepest decent, 51 0-5 1 1 Model parameter redundancy, 52 1-5 22 examples... above and the ellipses become more elongated (see Fig H.2b) The equation for the joint probability density functionf(z,, z2) of a bivariate normal distribution for two standarized variables z1 and z2 can be written as 1 1 f (z1,zd = exp[ -~ (z: - 2rz,z2 + zi) (H .16) 2ltJF-F 2(1 - r 2 ) 1 Simplifying equation (H .16) we get (z: - 2rzlz2 + zi) = -2 ( 1- r2)1n(zO2ltJT7) (H.17) which gives an equation for. .. 5 2-5 3 Built-in potential (of junctions), 4 2-4 3 temperature effects, 66 Bulk charge, varying, 251 Bulk mobility, 29 Burried-channel transistor, 71, 7 8-8 0, 178 threshold voltage of, 18 7-1 89, 19 0-1 93 drain current of, 27 0-2 75 Capacitances: charge based model, 33 7-3 40 depletion (junction), 5 3-5 6 diffusion, 5 6-5 7 extrinsic, 83 gate overlap, 10 9- 113 intrinsic, 82, 32 5-3 58 measurement of, 41 4-4 21, 47 7-4 88,... capacitor, 13 5-1 38 in MOSFET, 171 Diffusion constant, 36 Diffusion length, 46 Diode (junction): area (bottom-wall) capacitance, 5 9-6 0 breakdown voltage, 5 2-5 3 built-in potential, 4 2-4 3 circuit model, 6 1-6 4 current equation, 4 6-4 8 depletion width, 4 3-4 5 electric field, 4 1-4 5 601 ideality (emission) factor, 50 forward bias, 39, 49 diffusion capacitance, 5 6-5 7 junction capacitance, 5 3-5 6 periphery (side-wall)capacitance,... layer, 69 thickness of, 14 0-1 41 hot-electrons, 385 Channel length modulation, 248, 29 5-3 02 Channel stop, 98 Charge sharing, 19 5-2 01 Charge sheet model of MOSFET, 23 8-2 42 Circuit simulation program, need for, 3-4 CMOS (complementary MOS) transistor, 2, 9 9-1 00 latchup, 101 n-well, 99 Compensated semiconductors, 21 Compensated transistor (p-channel), 7 8-8 0, 178 threshold voltage of, 18 7-1 89 Subject Index Conductances . z1 and z2 can be written as (z: - 2rz,z2 + zi) . 1 1 f (z1,zd = exp[ -~ 2ltJF-F 2( 1 - r2) (H .16) 1 Simplifying equation (H .16) we get (z: - 2rzlz2 + zi) = -2 ( 1-. 3.9 - 3 x los 8 x lo6 3.42 1.46 1.412 0.014 5.43 1 1.12 8.0 1.45 x lo1’ - 2.4~ lo-’ - ~ 140.28 g/mol 3.0 g/cm - 7-7 .5 ~ 1 x lo7 V/cm 2.05 - - W1cm.K A cm- ’. 556 (-1 .27) fl cm2/V.s - 0.568( -0 .69) - 00 0.642 0.7 l(0.67) 578 12 Statistical Modeling and Worst-case Design Parameters N NI OF TF m 3 2 v M UN c- gE: u m 0 -s N