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SPICE Diode and MOSFET 11 Models and Their Parameters In this chapter we will discuss the pnjunction diode and MOSFET models, as implemented in Berkeley SPICE2G and higher versions. No attempt will be made to derive the model equations, as that has already been done at appropriate places in previous chapters. Here we will only describe equations used to model different regions of device operation. Emphasis will be on model parameters required to run SPICE and how to measure them. Berkeley SPICE has four different MOSFET models of varying complexity and accuracy [1]-[3]. These are (1) the Level 1 model-a first order model suitable only for long channel devices; (2) the Level 2 model that includes various second order effects present in small geometry devices, and is considered to be a physical model; (3) the Level 3 model-a semi-empirical model that includes most of the second order effects described in the Level 2 model; (4) the Level 4 model, called the BSIM (Berkeley Short-channel Igfet Model), that is a parameter based model. These different models can be activated by a parameter called LEVEL. We will describe all four levels of MOSFET model equations and their parameters. However, first we will describe the diode model parameters and how to determine them. 11.1 Diode Model The SPICE diode model has been discussed in detail in section 2.9. Table 11.1 shows model parameters that determine both DC and AC characteristics of a diode. Out of these ten parameters, the first seven (Z,, q, r,, Cjo, 4, rn and z) are determined from diode drain current and capacitance measurements. The remaining three parameters are often not measured and default values are generally assumed for silicon pn junction diodes. For other type of diodes such as SBD (Schotkey Barier Diode), parameter XTZ needs to be changed. In what follows we will discuss extraction for the first seven parameters. 11.1 Diode Model 537 Table 11.1. SPICE Diode model parameters Parameter SPICE name in parameter Parameter the text name description Default value Units IS XN RS CJO PB MJ TT BV EG XTI saturation current emission coefficient series resistance zero-bias junction capacitance pn junction potential pn grading coefficient transit time reverse breakdown voltage band-gap voltage IS temperature exponent 1.10-l4 A - 1 0 n 0 F 1 .o V 0.5 0 sec infinite V 1.1 eV 3.0 - - These parameters are entered in the MODEL statement in the SPICE input file. Recall that SPICE calculates the diode current I, using the following equation [cf. Eq. (2.82)] I d -I - s[ exp ( ',;;"') - I] which after rearranging in terms of V, (voltage across the diode) becomes (11.1) where I,, rs and y are model parameters that can be determined either using linear regression methods, as discussed in section 9.14 or a nonlinear optimization method (cf. Chapter 10). In the latter case we fit the experi- mental I, versus V, data to model equation (11.1) such that (1 1.2) is minimum, where Vexp and Vca, are the measured and calculated V,, respectively, and 1 is the number of data points. The result of this curve fitting is shown in Figure 11.1 for a typical n+p diode fabricated using a lpm CMOS process. The values for the parameter I,, q and r, for two types of diodes (n'p and p'n) are shown in Table 11.2. For comparison the parameters obtained using the linear regression method (cf. section 10.14) are also shown in this table. Note that extracted parameter values from two different methods are not exactly the same. However, for circuit simulation purposes, the parameter 538 11 SPICE Diode and MOSFET Models s - 10-4 u 10-5 3 10-6 0 U z U U 0 I %= 8.99 10-14 A r,= 15.88R n = 1.19 10-9 1 ) 1 o-’oo.o 0.5 1 .o 1.5 I DIODE FORWARD VOLTAGE, Vd (V) Fig. 11.1 Plot of log(1,) versus V, for a n’p diode. Circles are experimental points while continuous line is nonlinear least-square lit to Eq. (1 1.1) Table 11.2. Diode parameters I,, n and R, Linear Optimization Linear Optimization regression method regression method 1, 4.53 x 10-l~~ 8.99 x 10-1~~ 4.1 x 10-IZA 4.05 x 10-12A v 1.119 1.19 1.335 1.346 R, 11.03R 15.88 R 10.78 R 14.27 R set obtained using the optimization method is more appropriate, as these values are obtained by fitting over all portion of the curve in the current range of interest. Unlike the linear regression method, the optimization method yields all three parameters simultaneously. The parameters Cjo, 4 and m describe the junction capacitance due to the space charge in the junction depletion region. When the junction reverse voltage vd is less than 4/2, the junction capacitance Cj is given by the following equation [cf. Eq. (2.74)] (11.3) where Cjo varies from device to device, but is typically of the order of 1.0 x pF/pn2. The barrier potential 4 is usually about 0.5-0.7 V and the gradient factor m is assumed to be between 0.333 (linearly graded 11.1 Diode Model 539 junction) and 0.5 (abrupt junction), although values outside this range are not uncommon. The parameters 4 and m are generally determined by curve fitting Eq. (1 1.3) with measured data using a nonlinear least square optimization program. Very often, Cjo is also treated as a parameter to be optimized along with 4 and m rather than taking its value from measured data. This is because 3 parameters (Cjo, 4 and m) when optimized together give better fit over the entire data range of interest (see Figure 2.19 and Table 9.4). Transient Time z,. The parameter z, is the diode transit time and is used to calculate the diode diffusion capacitance C,, [cf. Eq. (2.77)] when the diode is forward biased. Typical values of z, range from 1 to 100 nsec. There are different electrical methods to calculate transit time z,, like the voltage decay method, the reverse recovery method, etc [4]. However, the simplest method of obtaining z, is to compute it from the reverse recovery method. In this method, we measure the diode storage time t, by switching the diode from a forward voltage V’ to a reverse voltage V,, and using the following equation [4]-[6] (11.4) where I, and I, are the forward and reverse current, respectively, when the diode is switched from the forward voltage V, to the reverse voltage V,. Note that this equation requires evaluation of the error function, which is approximately given by [4] erf(x) = ~ exp (- z2)dz ho S’ Due to the complexity of Eq. (1 1.4), the Newton-Raphson method is needed to compute Z, and is thus fairly involved. However, the following simple equation is often used to calculate z, t, = zr [ In (1 + 91. (11.6) As shown in Figure 11.2, there is a discrepancy of 30% between the z, calculated using Eqs. (11.4) and (11.6) even when I, >> I,. Therefore, it is advisable to use Eq. (11.4). While using Eq. (11.6), it has been suggested that IJ>>Z, must be kept in the measurements. This way, the affect of 540 11 SPICE Diode and MOSFET Models Fig. 11.2 Plot of tJtt versus IJ/Ir using Eq. (11.4) (continuous line) and (11.6) (dotted line). Continuous line predicts more exact value of z, n+ p diode t 250.0 10. 0.0 I 1.0 1 + Ir /If Fig. 11.3 Plot of t, versus (1 + If/I,) for a n'p diode using Eq. (11.6). Circles are experimental points while continuous line is linear regression of Eq. (11.6) recombination in the heavily doped region is entirely eliminated [4]. Under these conditions, the plot of t, versus ln(1 + If/Ir) will be a straight line (see Figure 11.3) the slope of which gives 7,. The plot will be highly curved if the condition I, >> I, is not met and then a unique value of lifetime can no longer be extracted. 11.1 Diode Model I ___ - 8V I 11 \I I -3v I I 54 1 I -T_Lr INPUT SIGNAL I._. -; c-xc (CH.l) , I __. - _.~__I HP 5Llll D OSCILLOSCOPE HP 7550A PLOTTER - - - - - - - - - - Fig. 11.4 Test setup for measuring storage time using reverse recovery method Equipment required for measuring z, are (1) a fast pulse generator such as an HP8116A, (2) a fast oscilloscope, such as a Tektronix 7854 or an HP54111D with dual trace plug-in, and (3) an X-Y recorder (optional). The advantage of the HP8116A function generator is that it can supply an asym- metric pulse waveforms. However, if not available, two pulse generators are needed to adjust the voltages Vr and V, independently. The test configu- ration is shown in Figure 11.4. The time delay due to connectors and series resistance in the circuit should be carefully minimized. The resistor R, (350 a) is chosen such that the DC current flowing into the diode is limited within the range of f 15 mA for voltages between Vr =. 8 V (forward bias) and V, = - 3 V (reverse bias) and the RC delay time introduced by this resistor is negligible as compared to the diode transit time. During forward bias (at t = 0-), a positive voltage (Vs = 8 V) at f= 100 Hz was applied to the circuit. The current was then calculated by dividing the Fig. 11.5 Storage time t, as a function of input pulse for n'p diode 542 1 I SPICE Diode and MOSFET Models Table 11.3. Diode transit time t, calculation using nS nS Error function Eq. (1 1.4) 241.3 415 Transit time nip P+n Log function Eq. (1 1.6) - 339 voltage measured on resistor R, (50 0). At t = 0, a negative voltage is applied to the diode; the input pulse changes from + 8 V to - 3 V at t = 0. The diode storage time was measured as the time from beginning of the reverse current transition to the time when the reverse current begins to decay toward its leakage current value (see Figure 11.5). The lifetime z calculated using the above method for both n+p and p+n diodes are shown in Table 11.3. Note the difference between z, calculated using Eqs. (1 1.4) and (1 1.6). 11.2 MOSFET Level 1 Model The level 1 model is often referred to as the Shichman-Hodges model. It is the simplest of the four MOSFET models in SPICE and is accurate onZy for long channel devices. 11.2.1 DC Model The threshold voltage Vth for the SPICE Level 1 model is [cf. Eq. (5.16)] (11.7) where V,, is the zero-bias (V,, = 0 V) threshold voltage of a long channel device, y is the body factor, and +f is the bulk Fermi potential. Note that no short channel or narrow width effects are taken into account; for details see section 5.1. The saturation voltage V,,,, is calculated using the following equation [cf. Eq. (6.54)] (11.8) The drain current I,, is calculated using the following relations [cf. Eq. (6.62)] S,[(Vg,- Kh-+vdS)Vds](1 +A&,) linear region, Vgs > I/,,and v,,~ v,,,, Ids= 0.5PO(Vgs - vth)2(1 + nvds) saturation region, V,, > V,,,, subthreshold region, V,, I V,, vdsat = vgs - Kh. (11.9) I0 where Po = K( W/L) and K = poco,. 11.2 MOSFET Level 1 Model 543 Note that the channel length modulation factor, I, is included in both the linear and saturation regions, so as to make the current and its first derivative continuous, as was explained in section 6.4.1. Also note that the subthreshold current is zero. In addition to the intrinsic MOSFET DC current equations described above, one needs to model the source/drain (S/D)-to-substrate pn junctions. Since in the normal operation of the device these junctions are reverse biased, the only DC parameter of the S/D junction which is of interest is the saturation (leakage) current I,. In SPICE this is specified as J,, the saturation current per unit area, or I,, the total saturation current. If J, is specified then one needs to specify the source and drain areas A, and Ad, respectively. 11.2.2 Capacitance Model The parameters of the dynamic model are the source/drain junction capacitances, the overlap capacitances, and the intrinsic MOSFET capaci- tances. The junction capacitances are the sum of both the bottom-wall (area) capacitance and side-wall (periphery) capacitance. The source diode capacitance C,, is computed as follows [cf. Eq. (3.26)] (11.10) where A, and P, are the area and periphery of the source-to-bulk pn junction, respectively, and Cjo and Cjswo are the junction capacitance per unit area and per unit periphery, respectively, at zero back bias. A similar equation holds for the drain-to-bulk junction capacitance CBD. These equations are used for all SPICE models. The intrinsic device capacitances (also sometimes referred to as gate oxide capacitances) are based on the Meyer model (see section 7.1.1). There are only three intrinsic capacitances C,,, C,, and CGB in the Meyer model. Their values change with bias conditions as follows: Strong Inuersion Region. In the strong inversion region when V,, > Vth, the gate capacitance is calculated using the following relations: Linear Region: In this case Vgs > (vth + Vd,) (1 1.1 la) (1 1.1 1 b) (1 1.1 lc) c,, = 0. 544 11 SPICE Diode and MOSFET Models Saturation Region: In this case V,h < V,, < (V,h + V&) c,, = 3 2 cox, (11.12a) c,D = 0 (1 1.12b) c,, = 0 (1 1.12c) cox, = WLC,,. (1 1.12d) Weak Inversion Region. In SPICE this region, defined as V,, < I/th, is divided into two parts. For the sake of simplicity the transition between the saturation and weak inversion regions is made linear, resulting in the following equations. where When (vih - 4f) < vgs < I/th? (11.13a) c,, = 0 (1 1.1 3b) (11.13~) (1 1.14a) (1 1.14b) (1 1.14~) Note that these capacitances do not require any new parameters. The overlap capacitances C,,,, CGD0 and C,,, are then added to C,,, CGD and C,,, respectively, in different regions of device operation and are calculated from the following equations: c,,, = c,sow ( 1 1.1 5a) cGDO = Cgdo (1 1.15b) CGBO = CgboL. (11.15~) Normally Cgso = Cgdo, the overlap capacitance per unit width at the source and drain ends, respectively. The model parameters for the SPICE Level 1 model are shown in Table 11.4. These parameters are entered in the MODEL statement in the SPICE input file. In addition to the model parameters shown in Table 11.4, the device parameters shown in Table 11.5 are also required. These device parameters 546 11 SPICE Diode and MOSFET Models Table 11.5. Device parameters Parameter SPICE name in parameter Parameter Default the text name description value Units L, L Drawn Channel length (mask dimensions) m wm W Drawn Channel width (mask dimensions) m AS Source diffusion area 0.0 m2 As Ad AD Drain diffusion area 0.0 m2 PS Perimeter of the source diffusion window 0.0 m ps Pd PD Perimeter of the drain diffusion window 0.0 m - NRS Number of squares in the source diffusion 1.0 m ~ NRD Number of squares in the drain diffusion 1.0 ~ electrical parameters will always override the value computed from process parameters, if also specified. Thus, if VTO, NSUB and TOX are input, the threshold voltage will assume the value entered as VTO, while GAMMA will be computed from NSUB and TOX. Similarly, if KP is not specified but UO is specified, then KP will be computed using either the specified value of TOX or its default value, if not specified. If VTO is not an input parameter then one needs to specify NSUB, TOX and TPG, which are then used to calculate V,, using Eq. (5.15). The last parameter TPG denotes the type of the gate and can take any of the following three values + 1 for gate type opposite to the substrate TPG = - 1 for gate type same as the substrate (11.16) and is used to calculate Qms and hence V,,(= Qms- qN,,/C,,) [cf. Eq. (4.14)], as follows: I 0 for aluminum gate - 0.5 - 0.5E, - 0.54, for TPG = 0 forTPG= -1 where E, is the energy gap for silicon [cf. Eq. (2.3)]. SPICE sets all parameters to the default values if negative values are input by the user, with the exception of VTO, TPG and NSS. Thus, if GAMMA is specified as a negative value, then SPICE assumes it to be zero, which is the default value. 0 For a p-channel enhancement and an n-channel depletion device VTO is negative, while it is positive for n-channel enhancement devices. Recall that p-channel depletion devices are not fabricated, but if simulated, their VTO will be positive. Qms = - 0.5E, - 0.54, for TPG = 1 (11.17) 1 0.5E, - 0.54, [...]... Sheu, ‘Inverse-geometry dependence of MOS transistor electrical parameters,’ IEEE Trans Computer-Aided Design, CAD-6, pp 58 2-5 85 (1987) 562 1 1 SPICE Diode and MOSFET Models [12] E Khalily, P H Decher, and D A Teegarden, ‘TECAP2 An interactive device characterization and model development system’, Tech Digest, IEEE Int Conf on Computer-Aided Design, ICCAD-84, pp 18 4-1 51 (1984) [13] S L Wong and C A T... shifts to yield fast p-channel device operation and the n-channel device skewed for lower drive current SF (Slow p-channel, Fast n-channel): This is a mixed case in which the a-channel has the largest currents and p-channel has the lowest currents The parameters reflect the process variation with appropriate shifts to yield slow p-channel device operation and the n-channel device skewed for higher drive... L (effective channel length) and W (effective channel width) is denoted by adding a letter ‘L‘ and ‘W’ at the start of the parameter name For example, v f b is a basic parameter with units of volts, and LVFB and WVFB are parameters which accounts for length and widths dependence of V F B ; that is, LVFB and WVFB are the corresponding L and W sensitiuityfuctors for V F B and have units of Volts.pm In... Digest, IEEE Int Conf on Computer-Aided Design, ICCAD-84, pp 18 4-1 51 (1984) [13] S L Wong and C A T Salama, ‘Improved simulation of p- and n-channel MOSFETs using an enhanced SPICE MOS3 model’, IEEE Trans Computer-Aided Design, CAD-6, pp 58 6-5 91 (1987) Statistical Modeling and Worst-case Design Parameters 12 In integrated circuit technology, the final dimensions of all structures (transistors, capacitors,... Scharfetter, and H C Poon, ‘Compact short-channel IGFET model (CSIM),’ Memorandum No UCB/ERL M84/20, Electronics Research Laboratory, University of California, Berkeley, March 1984 [3] B J Sheu, D L Scharfetter, P K KO ,and M C Jeng, ‘BSIM: Berkeley short-channel IGFET model for MOS transistors’, IEEE J Solid-state Circuits, SC-22, pp 55 8-5 65 (1 987) [4] D K Schroder, Semiconductor Material and Device... basic parameters, 5 for threshold voltage (V,,, d f , y , K , and v ] ) and 4 for drain current (Po, U o , U , and n) However, 5 parameters ( v ] , Po, U o , U , and n) depend on bias voltages Vd, and V,, as follows: + uObvbs u l = u l z + ulbVbs+ uld(vds - ‘dd) v]1 = v]lz + v]lbvbs + v ] l d ( V d s - vdd) uO = uOz n1 = 1 0 1 + nbI/bs + ndVd/ds (11.48a) (11.48b) (11.48~) (11.48d) and p o (or Po) is... form, if the following substitutions are made (11.26a) 11 SPICE Diode and MOSFET Models 550 (1 1.26~) (11.26d) With this substitution, Eq (11.25) becomes: (V, - $V 2- i X 2 ) ( X 2- V2) +(yFJq)(X 3- Vi’2) U= Vl - (YFl/rl)X - x2 (11.27) It is clear that the above equation can be written as a fourth order polynomial equation in X as: X4 + A X 3 + B X 2 +CX +D =0 (11.28) where the coefficients A, B, C and. .. probability theory, the basic theory is covered in Appendix H [15 ]-1 171 12.2 Model Parameter Sensitivity The first step in generating the WCF is to obtain the mean and standard deviation for each of the model parameters obtained from different dice and wafers Once the mean pi and the standard deviation si for each parameter p i is known, a test for 'outlier' data points (erroneous data points that reflect... Comparison of the Four MOSFET Models As was stated earlier, the Level 1 model is useful only for hand calculations and rough estimate of the circuit performance The Level 2 model is more physical compared to the Level 3 model However, Level 2 model often 11 SPICE Diode and MOSFET Models 560 causes convergence problems, and also takes 25% more CPU time, compared to Level 3 model, for each model evaluation... However, it has a large number of length and width dependent parameters, and therefore, requires large number of devices to extract the parameters Performance comparison of the four models have been reported recently with the aim to see how different models scale with the device length and width For this comparison, n-channel MOSFETs ranging in masked channel length (L,) and width (W,) from 10.4 to 1.4pm . I._. -; c-xc (CH.l) , I __. - _.~__I HP 5Llll D OSCILLOSCOPE HP 7550A PLOTTER - - - - - - - - - - Fig. 11.4 Test setup for measuring storage time using reverse. However, for circuit simulation purposes, the parameter 538 11 SPICE Diode and MOSFET Models s - 1 0-4 u 1 0-5 3 1 0-6 0 U z U U 0 I %= 8.99 1 0-1 4 A r,= 15. 88R n = 1.19 1 0-9 . (11.28) (V, - $V2 - iX2)(X2 - V2) - +(yFJq)(X3 - Vi’2) U= Vl - (YFl/rl)X - x2 X4 + AX3 + BX2 + CX + D = 0 where the coefficients A, B, C and D are: B = - 2(V1