MOSFET MODELING FOR VLSI SIMULATION - Theory and Practice Episode 7 doc

216 5 Threshold Voltage distribution of the potential 4. Physically speaking, Eq. (5.100) means that the influence of the lateral drain-source field on the potential barrier height is equivalent to and can be replaced by the reduction in the doping concen- tration [50]. Although Eq. (5.100) could be solved for any doping profile, assuming a step doping profile one obtains [49] while where and Vis is given by Eq. (5.101). The above model for V,, shows an approxi- mately inverse quadratic dependence on channel length L and an inverse dependence on oxide capacitance Cox. It should be pointed out that the weak dependence of the short-channel effect on the junction depth Xj has not been taken into account. In normal enhancement devices, this effect is small. Figure 5.26 shows the V,, variation with drain bias for two different back bias (Kb = 0 V and V,, = - 2 V). Continuous lines are experimental data while dashed lines are based on Eq. (5.102). As can be seen, agreement between the experimental data and the model is fairly good. Empirical Approach. Very often in actual devices, the exponential depen- dence of the DIBL effect on L is not observed. In such cases an empirical approach is often used, assuming the surface potential to be constant along the length of the channel, even for short channel devices. This assumption results in a very simple expression for cr, which can be derived as follows [79]: When V,, is small (< 0.1 V), the substrate depletion region width X,, may be calculated using the Poisson equation. When V,, is large, an additional potential will be imposed in the region already depleted. Since no additional charge appears in Poisson’s equation, this additional potential satisfies the Laplace equation: d2V, ~ = 0. dx2 (5.103) 5.3 Threshold Voltage Variations with Device Length and Width 217 Under the simplifying assumptions that (1) source/drain junction depths are small compared to the channel length, and (2) using the approximate boundary conditions that I/, = 0 at the source region and I/, = V,, at the drain region, we can solve Eq. (5.103), resulting in the following expression for the field E, at the source end 1791 vds E ZL' 1- (5.104) According to Gauss' law, this field is equivalent to a charge E~E,~E,, which reduces the threshold voltage by an amount (5.105) where G = E~E~~/(~:C,,L). Note that the dependence of o on Vsb has not been included, although depending on the process, the effect could be large (see Fig. 5.26). For circuit models the following empirical expression for G is normally used [Sl] EoEsi AVth = ~ 'ds = CJ 'ds ~CUXL (5.106) I where oo,ol and m are constants that are used to better fit the model for the geometry dependence of the DIBL effect, for a given range of Xj and Nb. The exponent m of L varies in the range 1-3. The back bias dependence of m has also been proposed [83], but for circuit models, it is more appropriate to take m as constant as is done in almost all empirical models [SO]. SPICE Level 3 model uses Eq. (5.106) with m = 3, CJ, = 0 and o0 as a fixed constant value, not a fitting parameter. The threshold voltage as a function of drain bias for a typical n-channel 1 pm CMOS technology at two substrate bias is shown in Figure 5.29. Symbols are experimental data while dashed and continuous lines are based on Eq. (5.106). Based on a 2-D solution, Masuda et al. [S2] have proposed the following empirical formula (5.107) which was fitted to the data for the following range of parameters: N,= lo1'- 10'6cm-3, Xj=0.15-0.41pm to, = 500 A 5 = 4.1. - 8.8. lo-: (5.108) m = 2.6 - 2.3. CUX 218 I toX =150 A EXPERIMENTAL (Vsb =3V) 0 EXPERIMENTAL (Vsb = 0) MODEL (Vsb = 3V) - MODEL (Vsb = 0) - 5 Threshold Voltage DRAIN VOLTAGE, Vd, (VOLTS) Fig. 5.29 Variation of threshold voltage with drain voltage at two different back bias V,, = 0 and 3 V with channel length as a parameter for a typical n-channel 1 pm CMOS process A slightly different form for the back bias v,b (through C,) dependence has also been proposed [84] (5.109) where cd is the depletion capacitance and is obtained by differentiating the bulk charge Qb. For example, for a uniformly doped substrate, we can write (5.110) YCOX Cd = 2d+Ti,b' On the other hand, Yang and Chaterjee's [SS] model uses an effective body factor to account for the drain bias effect as where y is the long channel body factor, which becomes bias dependent for implanted devices, and G, is a fitting parameter. It is interesting to note that diflerent short channel models show diferent functional dependences on the channel length L. Thus, the charge sharing models show a v,, dependence of 1/L, the empirical models show v,, dependence of 1/L" (1 < n < 3), the 2-D models show V,, dependence of exp( - L/Lo). 5.3 Threshold Voltage Variations with Device Length and Width 219 The dependencies are quite different and do cause confusion as to which model is valid. Obviously, the model to choose depends upon the process technology. It has been found that for circuit models Eq. (5.106) is fairly general and fits most of the technology data the author has come across. 5.3.4 Small-Geometry EfSect When both the device width W and length L are small, that is, when both W and L are of the same order of magnitude as the depletion width Xdm, then the device is called a small geometry device." For example, in a 2 pm CMOS technology a device with W/L= 3/2(pm) could be called a small geometry device. A first order estimate of the threshold voltage induced by small-geometry effect can be obtained by superposing the short-channel and narrow-width effects such that AVfh = AKhJ + AVth,W so that the total threshold voltage at low V,, for small-geometry devices becomes (5.112) This is the approach used in most of the circuit simulators, including SPICE. However, Eq. (5.112) overestimates AVth due to the small-geometry effect. This is because short-channel and narrow-width effects are not really independent as assumed in Eq. (5.112). In fact, there is a coupling between these two efects which results in a compensating efect. This is because both W and L determine the gate controlled charge and the volume of the charge must be properly identified. Therefore, mere addition of the two effects does not accurately predict Kh. We will develop a simple model for small small-geometry devices based on Yau's charge sharing approach which will illustrate this compensating effect on Vth. Figure 5.30 shows one side of the extra charge AQJ2 in the depletion region due to the narrow width effect for an assumed triangular region. Since the short-channel effect reduces the bulk charge, the resulting geometry indicated by the dotted line shows the amount of the extra charge induced due to short-channel effect. The volume V of the extra charge that is responsible for AVth,W is obtained by first finding the wedge volume and then subtracting the volume of the pyramid shape regions shown by lo A device with minimum L and W allowed by the process technology is referred to as the minimum size device for that technology. 220 5 Threshold Voltage CHARGE LOST BY DUE TO NARROW 4+ LJd C Fig. 5.30 Geometry for the computation of the threshold voltage of a small-geometry MOSFET dotted lines, that is, -Y- = 2(iGwLXim - $wX,X:m) where the factor of 2 accounts for both sides of the device and X, is given by Eq. (5.65). The compensated depletion charge due to width effect becomes (5.113) Comparing this equation with Eq. (5.88) clearly shows the effect of the short channel on the extra charge in the width direction. From Yau’s model [cf. Eq. (5.66)] we have so that AV,, due to the small geometry effect is obtained by adding Eqs. (5.113) and (5.114) as Clearly, the change in threshold voltage due to the small geometry effect is reduced by the extra term that originates due to the compensating effect. This is basically the model proposed by Merckel [S7]. Note that the value of the fitting parameter G, will be different when used with Eq. (5.88). Others 5.4 Temperature Dependence of the Threshold Voltage 221 [89] have also proposed models for the small-geometry effect, but they are not very different from the above model. The small geometry V,, model for n-channel MOSFET with fully recessed isolation oxide will be [67] (5.116) 5.4 Temperature Dependence of the Threshold Voltage The threshold voltage of long channel implanted MOSFETs is given by Eq. (5.63) and is determined by device physical parameters, such as flat band voltage Vfb, bulk Fermi potential 4,, and body factor y. Since both 4, (cf. section 2.4) and V,, (cf. section 4.7) are temperature dependent, V,, is also temperature dependent. In fact temperature dependence of V,, is primarily governed by the temperature dependence of 4, and V,, [30], [90]-[93]. Recall that the magnitude of both g5f and V,, decreases with increasing temperature, therefore the magnitude of V,, also decreases with increasing temperature for both n- and p-channel devices. Typically, the 2.01 I I I I 1.8 2 1.6 r '-I 1.L :: 1.2 !i p 1.0 w 0 -I 0.8 0 A. X I- 0.L 0.0; 2b ;o $0 f30 Id0 1;o It0 I TEMPERATURE C0C) Fig. 5.31 Measured threshold voltage variation with temperature for different types of n-channel MOSFETs. Curves (a),(b), (c) and (d) are for enhancement type devices, while curve (e) is for depletion type device. All devices have n+ polysilicon gates. The temperature coefficient of V,, (dVth/dT) is shown on each curve 222 5 Threshold Voltage temperature coefficient of threshold voltage I dl/,h/dTI lies in the range 1-3mV/degree depending upon the type of MOSFET and its physical parameters such as gate oxide thickness to,, substrate concentration N,, etc. Measured values of the threshold voltage as a function of temperature for different types of long-channel MOSFETs are shown in Figures 5.31 and 5.32. The data shown as curves (a), (b), (c) and (d) in Figures 5.31 are for n-channel enhancement type devices, while curve (e) is for n-channel deple- tion type device; all these devices are with n+ polysilicon gates. While curves (a), (b) and (c) are for channel implanted devices, curve (d) is for uniformaly doped device. Although both curves (b) and (c) are for enhance- ment devices, curve (b) has higher t0,(300A), and lower surface concen- tration (3 x ~m-~) compared to curve (c), which has to, = 105 A and N, = 3 x 10l6 ~m-~. The temperature dependence of V,, for p-channel devices is shown in Figures 5.32; curves (a) and (b) are for n+ polysilicon gates while (c) is for p+ polysilicon gate. The 1 dK:,/dTI is shown on each curve. Note that in all these devices V,, varies linearly with the temperature. This linear dependence of V,, on temperature is valid down to 50K [94,95]. The temperature behavior of V,,, can easily be predicted from Eq. (5.63). Remembering that the temperature dependence of Vfb is governed by the temperature dependence of a,,,,, the work function difference between the gate material and the substrate [cf. section 4.7.11, differentiating Eq. (5.63) 0.0r I I I I I I 11 0.21 1.81 0 20 LO 60 80 100 120 KO TEMPERATURE ("C) Fig. 5.32 Measured threshold voltage variation with temperature for different types of p-channel enhancement type MOSFETs. Curves (a) and (b) are with n+ polysilicon gate, while curve (c) is with p+ polysilicon gate 5.4 Temperature Dependence of the Threshold Voltage 223 yields (5.1 17) where the + and the - signs are for n- and p-channel devices, respectively, and d is given by (5.118) Recall that the temperature coefficient of $f is given by Eq. (2.31), repeated here for convenience, (5.119) while that for Oms is given by Eq. (4.81) or (4.82) depending upon type of the gate and substrate materials; that is, (n' poly-Si gate and p-bulk) a@,, - (5.120a) (n' poly-Si gate and n-bulk). (5.120b) Equation (5.1 17) shows that the temperature coefficient of threshold voltage, Tuth, of a MOSFET depends upon the following parameters: The substrate concentration N,; the higher the N,, the higher the $f, and therefore, the higher the Tuth. At lower-temperatures 4f increases; therefore, d will be reduced further and consequently, substrate sensitivity (change in V,, due to change in Vsb) decreases at lower temperatures. Thus, the lower the temperature, the lower the substrate sensitivity. The gate oxide thickness Lox; the higher the to,, the higher the body factor y and hence higher the at term. In other words, thicker gate oxides result in higher Tuth. The back bias Vsb; the higher the Vsb, the lower the sd term, and con- sequently Tot,, becomes smaller at higher vsb. This is evident from curve (a) and (b) (Figs. 5.31 and 5.32) which are for Vsb = 3 V and 0 V, respectively. n-Channel Devices (nMOST). For n-channel enhancement devices (n' polysilicon gate and p-substrate) &D,,/dT is given by Eq. (5.120a). Since Eqs. (5.119) and (5.120) when used in Eq. (5.117) almost compensate each other, it is the last term in Eq. (5.117) that mainly contributes to the temperature coefficient of Vth. Furthermore, for implanted devices, V, and 224 5 Threshold Voltage 24f almost compensate each other, therefore d according to Eq. (5.118) has a relatively larger value compared to unimplanted devices where V, is zero. This explains why unimplanted devices have a lower temperature coefficient compared to the implanted devices (see curves (b) and (c) in Figure 5.31). Since V,, increases d, Turh decreases (compare curves (a) and (b) in Figure 5.31). For n-channel depletion devices (n' polysilicon gate and n-silicon surface), Eqs. (5.120b) for a@,,/aT and (5.119) for a@,,/aT when used in Eq. (5.117), do not compensate each other, but rather add up. Therefore, all three terms of Eq. (5.117) contribute to Tot,, resulting in a higher temperature coefficient compared to enhancement devices (curve e, Figure 5.3 1). For curve (d), higher Tuth is also due to higher to, ( = 420 A) compared to 300w for curve b). p-Channel Devices (pMOST). For p-channel devices with p + polysilicon gates, the situation is similar to that of n-channel enhancement devices with n+ polysilicon gates and therefore, Tofh is almost the same as that of 0.0 1.0 2.0 3.0 4.0 5.0 6.0 CHANNEL LENGTH L ( pm) (a) vsb= ov 8 -2.OY' " ' 1 ' I ' 1 ' 11 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 CHANNEL WIDTH W ( km) (b) Fig. 5.33 Variation of the temperature coefficient of threshold voltage To,,, as a function of (a) channel length, (b) channel width, for a typical 1 pm CMOS process. (After Arora [30].) References 225 n-channel enhancement devices. However, for p-channel compensated devices (n’ polysilicon gate and n-type concentration at the silicon surface), the situation is similar to n-channel depletion devices and therefore, T,)th in this case is higher compared to that of surface channel p-devices (see curves (a) and (b) Figure 5.32). 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