VI ĐIỀU KHIỂN PIC - ĐẶNG LÊ KHOA - TRƯỜNG ĐH KHTN - KHOA ĐIỆN TỬ VIỄN THÔNG docx

Data Memory Addressing Direct Addressing - Operand addresses embedded in the opcode 8 bits of the 16-bit instruction specify any one of 256... Data Memory Addressing Direct Addressing

TRƯỜNG ðẠI HỌC KHOA HỌC TỰ NHIÊN

TRƯỜNG ðẠI HỌC KHOA HỌC TỰ NHIÊN

KHOA ðIỆN TỬ KHOA ðIỆN TỬ VIỄN THÔNG VIỄN THÔNG

CH ƯƠ NG 1: GI Ớ I THI Ệ U

• Vi ñ i ề u khi ể n

• Các h ọ vi ñ i ề u khi ể n

Hệ thống nhúng

• “A system whose principal function is

not computational, but which is

controlled by a computer embedded

within it”

bị trong nhà, văn phòng, ñiều khiển xe hơi

4

M ộ t s ố ứ ng d ụ ng h ệ th ố ng nhúng

PWM 1

PWM 2

10-bit

Microcontroller Families

8

PIC12F508/509 block diagram

10

PIC 18F452 General Architecture

12

Microprocessor Unit

• Includes Arithmetic Logic Unit (ALU), Registers, and Control Unit

14

Arithmetic Logic Unit (ALU)

• CPU d ẫ n n ạ p l ệ nh t ừ b ộ nh ớ , gi ả i mã, và g ử i chúng ñế n b ộ ALU ñể th ự c thi

• ALU th ự c thi các l ệ nh c ộ ng, tr ừ , d ị ch và các phép toán logic.

• ALU ho ạ t ñộ ng k ế t h ợ p v ớ i:

– M ộ t thanh ghi ñ a d ụ ng g ọ i là thanh ghi W

– Và thanh ghi f có th ể ñị nh v ị trong vùng nh ớ d ữ

li ệ u

– Giá tr ị c ố ñị nh (Literal) nhúng trong ch ươ ng trình

Arithmetic Logic Unit

– Reset khi b ộ watchdog timer b ị tràn

• Reset s ẽ làm m ấ t d ữ li ệ u

– Bank Select Register (BSR)

• Thanh ghi 4 bit dùng ñể ñịnh ñịa chỉ trực tiếp trong bộ nhớ dữ liệu– File Select Registers (FSRs)

• Thanh ghi 16-bit ñược dùng như là con trỏ trong ñịnh ñịa chỉ gián

PIC18F - Address Buses

• BUS ñị a ch ỉ

– Bus ñịa chỉ có 21-bit: có bộ nhớ 2MB

– Bus ñịa chỉ 12-bit: có khả năng quản lý bộ nhớ 4KB

Data Bus and Control Signals

• Bus dữ liệu

– 16-bit instruction/data bus for program memory

– 8-bit data bus for data memory

• Các tín hiệu ñiều khiển

– Read và Write

22

Program Memory

Bộ ñếm chương trình 21-bit

có khả năng ñịnh vị bộ nhớ chương trình 2-Mbyte

Vector RESET ở ñịa chỉ

0000h và vector ngắt ở

ñịa chỉ 0008h và 0018h.

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Truy xuất vùng nhớ với nội dụng là các số

• Half of bank 0 and half of

bank 15 form a virtual bank

that is accessible no matter

PIC16F8F2520/4520 Register File Map

000h 07Fh

Bank 0 GPR

Bank 1 GPR

Bank 2 GPR

080h 0FFh 100h

1FFh 200h

2FFh

00h

Access Bank

that is accessible no matter

which bank is selected

256 Bytes

Bank 13 GPR

Bank 14 GPR

EFFh F00h F7Fh

00h 7Fh 80h FFh

Data Memory with Access Banks

GPR=General Purpose Reg

SFR=Special Function Reg

These registers are always accessible regardless which bank is selected – acting as a virtual memory -

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FFF=2 12 =16x256=4096=4K

Data Memory also known as

“Register File”

We will discuss the access to

every region later, while talking

about PIC18 instructions

Accessing Data Memory

• The machine code for a PIC18 instruction has only 8 bits for a data memory address which needs 12 bits The

Bank Select Register (BSR) supplies the other 4 bits.

Data Memory Addressing

Direct Addressing - Operand address(es)

embedded in the opcode

 8 bits of the 16-bit instruction specify any one of 256

Data Memory Addressing

Direct Addressing Examples

 Direct addressing (banked)

addwf 0x55, W, BANKED ; add WREG with the content of

; addr 55 (f=55) in bank 2 (a=1),

; addr 55 (f=55) in bank 2 (a=1),

; save the result to WREG (d=0)

Operand is the content of data memory at add 0x255

Mnemonic in MPASM:

A (a=0) - the access bank; BANKED (a=1) - banked

Data Memory Addressing

Direct Addressing Examples

 Direct addressing (using access bank)

;movlb not required addwf 0x55, F, A ; add WREG to content of

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addwf 0x55, F, A ; add WREG to content of

; addr 55 (f=55) in access

; bank (a=0), save the result

; in the data memory at the

;address 0x55 (d=0)

Operand is the content of data memory add 0x055

Indirect Addressing

 3 File Select Registers (FSR) as a pointer to

the data memory location that is to be read or written.

Data Memory Addressing

 Each FSR has an INDF register associated

with it

 The INDFn register is not a physical register

Addressing INDFn actually addresses the register whose address is contained in the

Indirect Addressing

Data Memory Addressing

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MOVWF INDF2, W ; move WREG to the register

; pointed by FSR2

Indirect Addressing Operations

Data Memory Addressing

Indirect Addressing Example

count set 0x02 lfsr 0, num1 lfsr 1, num2 movlw 3 movwf count, A

Data Memory Addressing

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movwf count, A bcf STATUS, c

addwfc POSTINC0, F decfsz count, 1

bra Again Again: movf POSTINC1, W

SFRs Examples

CH ƯƠ NG 4: CÁC C Ổ NG I/O

36

PIC18F452 I/O Ports

• Five I/O ports

– PORT A through PORT E

– Most I/O pins are multiplexed

– Generally have eight I/O pins with a few exceptions

– Addresses already assigned to these ports in the design stage

– Each port is identified by its assigned SFR

– Each port is identified by its assigned SFR

Parallel I/O Combined I/O Structure

38

Parallel I/O ports Main Features

• Can be configured through software as either input or output

• Ability to set or reset individual bits

• Ability to set or reset individual bits

• Can have internal pull-ups

• Can drive small loads like LEDs

• Can be multifunction

• Different capability for pins (i.e larger current)

Parallel I/O ports

• For most ports, the I/O pin’s direction (input or output) is controlled by the data direction register TRISx (x=A,B,C,D,E): a ‘1’ in the TRIS bit corresponds to that pin being an input, while a ‘0’ corresponds to that pin being an output

• The PORTx register is the latch for the data to be output Reading PORTx

register read the status of the pins, whereas writing to it will write to the port latch

• Example: Initializing PORTB (PORTB is an 8-bit port Each pin is individually configurable as an input or output)

• Example: Initializing PORTB (PORTB is an 8-bit port Each pin is individually configurable as an input or output)

bcf STATUS, RP0 ; select bank0

bcf STATUS, RP1

clrf PORTB ; clear PORTB output data latches

bsf STATUS, RP0 ; select bank1

movlw 0xCF ; value used to initialize data direction

movwf TRISB ; PORTB<7:6>=inputs, PORTB<5:4>=outputs,

; PORTB<3:0>=inputs

40

Relationship between TRIS and PORT

Registers

Illustration: Displaying a Byte

Illustration (3 of 5)

– Logic 0 to TRISC sets up PORTC as an output port

– Byte 55H turns on alternate LEDs

44

PIC18F Programming Model and

Its Instruction Set

PIC18F Programming Model

• Divided into two groups

– ALU Arithmetic Logic

Unit (ALU)

– Special Function

Registers (SFRs) from

data memory

– 8-bit Working Register (equivalent to

an accumulator)

• BSR: Bank Select Register

• BSR: Bank Select Register

– 4-bit Register (0 to F)

• Only low-order four bits are used to provide MSB four bits of a12-bit

address of data memory.

• STATUS: Flag Register

• C (Carry/Borrow Flag):

Example: 9F+52 =F1

1001 1111

0101 0010 -

1111 0001 N=1,OV=0, Z=0, C=0, DC=1

Flags in Status Register

• C (Carry/Borrow Flag):

• DC (Digit Carry Flag):

File Select Registers (FSR)

• There are three registers:

Other Registers

• Program Counter (PC)

– 21-bit register functions as a

pointer to program memory

during program execution

• Special Function Registers

– 21-bit register used as a

memory pointer to copy

bytes between program

memory and data registers