Compal NM b301 DG424 DG524 REV 1 0

A B C D E 1 LCFC Confidential APL G 320 M/B DG424/DG524 Schematics Document Intel Apollolake M-Processor with DDRIIIL + NV(AMD LV2-R17M-M1-70) GPU 2 2017-02-28 REV:1.0 3 4 Issued Date Title LC Future Center Secret Data Security Classification 2013/08/08 Deciphered Date Cover Page 2014/01/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Size C Date: A B C D Document Number Rev 1.0 DG424/DG524 Thursday, March 09, 2017 E Sheet of 58 A B C D E LCFC confidential File Name : Cairo 4D&5D AMD LV2-R17M-M1-70 Board Number : NM-B301 AMD: Level2 PN : DA600013C00 Package: S3 Page 19~24 PCIe Port 1~4 Page 17 UP TO 8G 1.35V DDR3L 1600 MT/s (platform support up to 1866MT/s) VRAM: 512/256*16 GDDR5*4: 4GB/2GB DDR3L-SO-DIMM Memory BUS (DDR3L) Single Channel PCI-Express 4x Gen3 USB 3.0 Conn USB 3.0 Port1 USB 2.0 Port0 USB 3.0 1x USB 2.0 1x Page 25~29 HDMI HDMI Conn Page 31 USB 2.0 Conn Page 34 USB 2.0 1x eDP Conn USB 2.0 Port3 USB 2.0 Port6 eDP x2 Lane Int MIC Conn USB3.0 x1 USB2.0 x1 BGA-1296 31mm*24mm Page 28 Type-C IC USB3.0 Redriver Parade PS8713 Realtek RTS5449 Type-C Conn Page 29 Page 29 Touch Screen USB 2.0 1x TDP 6W SATA Gen3 SATA HDD Page 42 Page 31 Apollolake-M Int Camera Page 28 Reserve SATA Port0 USB2.0 1x SATA ODD Page 42 PCIe 1x SATA Port1 Page 39 RJ45 Conn Page 37 LAN Realtek Page 36 PCIe Port5 USB 2.0 Port7 Int Camera USB 2.0 1x PCIe 1x RTL8111GUL NGFF Card WLAN&BT SATA Gen1 Page 28 USB 2.0 Port4 PCIe Port4 HD Audio SD/MMC Conn FSPI BUS Page 35 Codec & C/R SPK Conn Page 34 Realtek RTS5119 HD Audio SPI ROM 8MB EC SPI Port USB2.0 x1 Page Page 4~16 LPC BUS HP&Mic Combo Conn I2C Page 34 Page 34 USB2.0 Port5 EC ITE IT8986E/BX-LQFP Page 38 Page 44 Touch Pad Page 45 Int.KBD Page 45 TPM Z32H320TC Reserve Thermal Sensor NCT7718W Page 38 Reserve 4 Issued Date Title LC Future Center Secret Data Security Classification 2013/08/08 Deciphered Date Block Diagram 2014/01/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Size C Date: A B C D Document Number Rev 1.0 DG424/DG524 Thursday, March 09, 2017 E Sheet of 58 A B C SIGNAL STATE Power Plane V20B+ +3VALW +3VL +5VALW +5VL +3VALW_SOC +1.24VALW +1.8VALW +1.35V OFF LOW LOW HIGH ON OFF OFF OFF LOW LOW LOW ON OFF OFF OFF S4 (Suspend to Disk) LOW S5 (Soft OFF) LOW O O X X XHCI USB 3.0 X Port device Port X X USB 2.0 Type C USB3.0 Type C( USB 2.0) USB3.0 (2.0) Touch Screen USB2.0 Finger Print CARD READER CAMERA BT SMBUS Control Table SOURCE VGA BATT IT8986HE SODIMM WLAN WiMAX Thermal Sensor TP Module PCH Charger DDI PORT LIST PMIC Port EC_SMB_CK0 EC_SMB_DA0 EC X +3VL X X V X X X X X Device DDI0 DDI1 V NC HDMI eDP eDP EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 PCH_SMB_CLK EC X +3VL EC X X X X X V X +3VS V X X V X X X X X +3VS V X V X X X +3VL +3VGS X X X V +3VS V V PCH PCH_SMB_DATA +3VALW_SOC V +3VS +3VALW_PCH EC SM Bus1 address EC SM Bus0 address EC SM Bus2 address PCH SM Bus address Device Address Device Address Device Address Device Address PMIC 0x68 Smart Battery 0x16 Thermal Sensor 0x98(reserve) DDR SO-DIMM 0xA0 Wlan Rsvd Charger 0x12 I2C4 Bus address (Touch Pad) Device Address Slave 0x15 Descriptor 0x0001 Device BIOS Device ID Map CLK REQ dGPU PCIe1(Func0):Root Port#3 CLKREQ0 LAN WLAN PCIe0(Func0):Root Port#1 PCIe0(Func1):Root Port#2 CLKREQ1 CLKREQ2 BOM Structure Table USB Port Table X X X OFF OFF +CPU_CORE O X ON ON LOW O X ON ON HIGH LOW S3 X ON HIGH LOW S3 (Suspend to RAM) O X HIGH HIGH S0IX(Power On Suspend) O O HIGH +1.05VS VTT O S5 S4 Battery only S5 S4 AC & Battery don't exist Port ON +1.8VS +VNN O Clock ON HIGH O O +VS/VTT ON HIGH O O +V ON HIGH S0 S5 S4/AC Only +VALW HIGH SLP_S0# SLP_S3# SLP_S4# SLP_S5# Full ON +3VS State E PCIE PORT LIST +5VS D , X > Means OFF ) ( O > Means ON Voltage Rails BTO Item For EMC part For EMC un-stuff part EMC 15" part EMC 14" part EMC USB TVS part Cost Down part RF@ RF_NS@ RF_PXNS@ For RF part For RF un-stuff part For RF GPU un-stuff part 14@ 15@ For 14" part For 15" part 8111GUL@ 8111H@ 8111GUL LAN SKU part@ 8111H LAN SKU part@ PX@ TOPAZ@ EXO@ UMA@ Discrete GPU SKU part TOPAZ dGPU SKU part R16M-M1-30 dGPU SKU part UMA SKU ID part TMSEN@ TMSEN_PX@ TMSEN_UMA@ Thermal Sensor part dGPU Thermal Sensor part UMA Thermal Sensor part TPM@ NUVOTON@ NATIONZ@ TPM part NOVOTON TPM part NATIONZ TPM part TS@ FP@ KBL@ Touch Screen part Finger Print part KB Backlight part UART@ RTCRST@ UART debug part Clear RTCRST# function part ME@ @ HDMI@ ME part un-stuff part HDMI Logo part N3350_B0@ N3450_B0@ N4200_B0@ N3350_B1@ N3450_B1@ N4200_B1@ M2GX4@ S2GX4@ H2GX4@ M2G@ S2G@ H2G@ PCB@ Apollolake N3350 B0 stepping QS CPU part Apollolake N3450 B0 stepping QS CPU part Apollolake N4200 B0 stepping QS CPU part Apollolake N3350 B1 stepping MP CPU part Apollolake N3450 B1 stepping MP CPU part Apollolake N4200 B1 stepping MP CPU part Micron 2GB(256x16x4) VRAM X76 SKU Samsung 2GB(256x16x4) VRAM X76 SKU Hynix 2GB(256x16x4) VRAM X76 SKU Micron 2GB VRAM Samsung 2GB VRAM Hynix 2GB VRAM PCB part 2013/08/08 Deciphered Date Size C Date: B C D Notes List 2014/01/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER A Title LC Future Center Secret Data Security Classification Issued Date BOM Structure EMC@ EMC_NS@ EMC_15@ EMC_14@ EMC_USB@ CD@ Document Number Rev 1.0 DG424/DG524 Thursday, March 09, 2017 E Sheet of 58 DDRA_DQ[63:0] 17 DDRA_MA[15:0] 17 DDRA_DQS[7:0] 17 DDRA_DQS#[7:0] 17 APL_SOC BE56 BD54 BF58 BE50 BB50 BD50 BA50 BB54 MEM_CH0_DQ24 MEM_CH0_DQ25 MEM_CH0_DQ26 MEM_CH0_DQ27 MEM_CH0_DQ29 MEM_CH0_DQ28 MEM_CH0_DQ30 MEM_CH0_DQ31 Group DDRA_DQ24 DDRA_DQ25 DDRA_DQ26 DDRA_DQ27 DDRA_DQ29 DDRA_DQ28 DDRA_DQ30 DDRA_DQ31 MEM_CH0_DQ16 MEM_CH0_DQ17 MEM_CH0_DQ18 MEM_CH0_DQ19 MEM_CH0_DQ20 MEM_CH0_DQ21 MEM_CH0_DQ22 MEM_CH0_DQ23 Group Group AY57 BB57 BD59 BF59 AV54 AY55 AV52 BD58 MEM_CH0_DQ40 MEM_CH0_DQ41 MEM_CH0_DQ42 MEM_CH0_DQ43 MEM_CH0_DQ44 MEM_CH0_DQ45 MEM_CH0_DQ46 MEM_CH0_DQ47 MEM_CH0_DQ48 MEM_CH0_DQ49 MEM_CH0_DQ50 MEM_CH0_DQ51 MEM_CH0_DQ52 MEM_CH0_DQ53 MEM_CH0_DQ54 MEM_CH0_DQ55 MEM_CH0_DQ56 MEM_CH0_DQ57 MEM_CH0_DQ58 MEM_CH0_DQ59 MEM_CH0_DQ60 MEM_CH0_DQ61 MEM_CH0_DQ62 MEM_CH0_DQ63 AR39 AV37 AW37 AR37 AT37 AT41 AR41 AW35 DDRA_DQ32 DDRA_DQ33 DDRA_DQ34 DDRA_DQ35 DDRA_DQ36 DDRA_DQ37 DDRA_DQ38 DDRA_DQ39 DDRA_DQS0 DDRA_DQS#0 BB63 BC62 DDRA_DQS1 DDRA_DQS#1 AT59 AT58 DDRA_DQS2 DDRA_DQS#2 BB59 BB58 BJ44 BG39 BG40 BJ40 BG43 BG44 BH45 BH41 DDRA_DQ40 DDRA_DQ41 DDRA_DQ42 DDRA_DQ43 DDRA_DQ44 DDRA_DQ45 DDRA_DQ46 DDRA_DQ47 DDRA_DQS3 DDRA_DQS#3 BD52 BB52 BA34 BE34 BD34 BD37 BB37 BE39 BD39 BB34 DDRA_DQ48 DDRA_DQ49 DDRA_DQ50 DDRA_DQ51 DDRA_DQ52 DDRA_DQ53 DDRA_DQ54 DDRA_DQ55 BJ38 BG34 BG33 BH33 BG38 BH37 BG37 BJ34 DDRA_DQ56 DDRA_DQ57 DDRA_DQ58 DDRA_DQ59 DDRA_DQ60 DDRA_DQ61 DDRA_DQ62 DDRA_DQ63 OF 23 APOLLOLAKE_FCBGA1296 REV = 0.7 @ C DDRA_DQS4 DDRA_DQS#4 AV39 AW39 DDRA_DQS5 DDRA_DQS#5 BJ42 BG42 DDRA_DQS6 DDRA_DQS#6 BB35 BD35 DDRA_DQS7 DDRA_DQS#7 BG36 BH35 DDRA_MA0 DDRA_MA1 DDRA_MA2 DDRA_MA3 DDRA_MA4 DDRA_MA5 DDRA_MA6 DDRA_MA7 DDRA_MA8 DDRA_MA9 DDRA_MA10 DDRA_MA11 DDRA_MA12 DDRA_MA13 DDRA_MA14 DDRA_MA15 BG50 BG51 BH51 BD41 BE41 BJ52 BG53 BG55 BH53 BG52 BH49 BH55 BG54 BG46 BG56 BG57 APL_SOC UC1B MEM_CH0_DQ32 MEM_CH0_DQ33 MEM_CH0_DQ34 MEM_CH0_DQ35 MEM_CH0_DQ36 MEM_CH0_DQ37 MEM_CH0_DQ38 MEM_CH0_DQ39 Group DDRA_DQ16 DDRA_DQ17 DDRA_DQ18 DDRA_DQ19 DDRA_DQ20 DDRA_DQ21 DDRA_DQ22 DDRA_DQ23 MEM_CH0_DQ8 MEM_CH0_DQ9 MEM_CH0_DQ10 MEM_CH0_DQ11 MEM_CH0_DQ12 MEM_CH0_DQ13 MEM_CH0_DQ14 MEM_CH0_DQ15 Group AV59 AU63 AU62 AV58 AV57 AT55 AT54 AY59 Group DDRA_DQ8 DDRA_DQ9 DDRA_DQ10 DDRA_DQ11 DDRA_DQ12 DDRA_DQ13 DDRA_DQ14 DDRA_DQ15 MEM_CH0_DQ0 MEM_CH0_DQ1 MEM_CH0_DQ2 MEM_CH0_DQ3 MEM_CH0_DQ4 MEM_CH0_DQ5 MEM_CH0_DQ6 MEM_CH0_DQ7 Group D AY62 AY61 BE62 BG62 BD63 AW62 AW63 BD62 Group UC1A DDRA_DQ0 DDRA_DQ1 DDRA_DQ2 DDRA_DQ3 DDRA_DQ4 DDRA_DQ5 DDRA_DQ6 DDRA_DQ7 MEM_CH0_DQSP0 MEM_CH0_DQSN0 MEM_CH0_VREFCA MEM_CH0_VREFDQ MEM_CH0_DQSP1 MEM_CH0_DQSN1 MEM_CH0_BA0 MEM_CH0_BA1 MEM_CH0_BA2 MEM_CH0_DQSP2 MEM_CH0_DQSN2 MEM_CH0_ODT0 MEM_CH0_ODT1 MEM_CH0_DQSP3 MEM_CH0_DQSN3 MEM_CH0_CAS_N MEM_CH0_WE_N MEM_CH0_RAS_N MEM_CH0_DQSP4 MEM_CH0_DQSN4 NCTF1 NCTF2 MEM_CH0_DQSP5 MEM_CH0_DQSN5 MEM_CH0_CS1_N MEM_CH0_CS0_N MEM_CH0_DQSP6 MEM_CH0_DQSN6 MEM_CH0_CLKP1 MEM_CH0_CLKN1 MEM_CH0_DQSP7 MEM_CH0_DQSN7 MEM_CH0_CLKP0 MEM_CH0_CLKN0 MEM_CH0_MA0 MEM_CH0_MA1 MEM_CH0_MA2 MEM_CH0_MA3 MEM_CH0_MA4 MEM_CH0_MA5 MEM_CH0_MA6 MEM_CH0_MA7 MEM_CH0_MA8 MEM_CH0_MA9 MEM_CH0_MA10 MEM_CH0_MA11 MEM_CH0_MA12 MEM_CH0_MA13 MEM_CH0_MA14 MEM_CH0_MA15 MEM_CH0_CKE0 MEM_CH0_CKE1 NCTF3 NCTF4 MEM_CH1_RESET_N MEM_CH0_RESET_N MEM_CH0_DQSP8 MEM_CH0_DQSN8 MEM_CH0_CB7 MEM_CH0_CB6 MEM_CH0_CB5 MEM_CH0_CB4 MEM_CH0_CB3 MEM_CH0_CB2 MEM_CH0_CB1 MEM_CH0_CB0 AR35 AT34 DDRA_CAVREF DDRA_DQVREF BJ48 BG49 BH57 DDRA_BA0# DDRA_BA1# DDRA_BA2# AW43 AW41 DDRA_ODT0 DDRA_ODT1 BH47 BG48 BG47 DDRA_CAS# DDRA_WE# DDRA_RAS# DDRA_BA0# DDRA_BA1# DDRA_BA2# D 17 17 17 DDRA_ODT0 DDRA_ODT1 17 17 DDRA_CAS# DDRA_WE# DDRA_RAS# 17 17 17 DDRA_CS1# DDRA_CS0# 17 17 AT43 BB41 BA41 AR43 DDRA_CS1# DDRA_CS0# BB48 BD48 DDRA_CLK1 DDRA_CLK1# BD45 BE45 DDRA_CLK0 DDRA_CLK0# BH61 BH60 DDRA_CKE0 DDRA_CKE1 DDRA_CLK1 17 DDRA_CLK1# 17 DDRA_CLK0 17 DDRA_CLK0# 17 DDRA_CKE0 DDRA_CKE1 17 17 BH58 BJ58 AR30 AR34 DDRB_DRAMRST# DDRA_DRAMRST# TP53 @ BD47 BB47 BA45 BD43 AV47 AV48 AW45 BB43 AW47 AW48 C OF 23 APOLLOLAKE_FCBGA1296 REV = 0.7 @ Follow CRB(v1.2): unstuff RC289, CC160, RC290, RC292, CC161, RC291 03/12 DDRA_CAVREF RC9321 @ 0_0402_5% DDRA_CAVREF_R RC289 @ Follow CRB(PDG w/o 1k damping resister) Double confirm with Intel FAE, follow CRB will have low risk 0_0402_5% DDR_CA 17 CC160 0.022U_0201_6.3V6-K @ +1.35V 1 RC290 24.9_0402_1% @ 2 RC268 1K_0402_1% DDRA_DQVREF RC9320 @ 0_0402_5% DDRA_DQVREF_R RC292 @ 0_0402_5% DDR_DQ 17 DDRA_DRAMRST# RC270 1K_0402_1% DDRA_DRAMRST#_R DDRA_DRAMRST#_R 17 B B CC161 0.022U_0201_6.3V6-K @ RC291 24.9_0402_1% @ A A Issued Date Title LC Future Center Secret Data Security Classification 2013/03/26 Deciphered Date SOC (DDR3L CHA) 2014/01/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Size C Date: Document Number Rev 1.0 DG424/DG524 Thursday, March 09, 2017 Sheet of 58 UC1C APL_SOC APL_SOC UC1D D D Group Group Group Group MEM_CH1_DQ24 MEM_CH1_DQ25 MEM_CH1_DQ26 MEM_CH1_DQ27 MEM_CH1_DQ28 MEM_CH1_DQ29 MEM_CH1_DQ30 MEM_CH1_DQ31 Group AT27 AW29 AR27 AT23 AV27 AR25 AR23 AW27 MEM_CH1_DQ16 MEM_CH1_DQ17 MEM_CH1_DQ18 MEM_CH1_DQ19 MEM_CH1_DQ20 MEM_CH1_DQ21 MEM_CH1_DQ22 MEM_CH1_DQ23 Group BG24 BJ20 BH23 BJ24 BG20 BG21 BH19 BG25 MEM_CH1_DQ8 MEM_CH1_DQ9 MEM_CH1_DQ10 MEM_CH1_DQ11 MEM_CH1_DQ12 MEM_CH1_DQ13 MEM_CH1_DQ14 MEM_CH1_DQ15 Group BA30 BB30 BE30 BD30 BE25 BB27 BD25 BD27 MEM_CH1_DQ0 MEM_CH1_DQ1 MEM_CH1_DQ2 MEM_CH1_DQ3 MEM_CH1_DQ4 MEM_CH1_DQ5 MEM_CH1_DQ6 MEM_CH1_DQ7 Group BJ26 BG30 BH31 BG31 BH27 BG27 BG26 BJ30 MEM_CH1_DQ32 MEM_CH1_DQ33 MEM_CH1_DQ34 MEM_CH1_DQ35 MEM_CH1_DQ36 MEM_CH1_DQ37 MEM_CH1_DQ38 MEM_CH1_DQ39 MEM_CH1_DQ40 MEM_CH1_DQ41 MEM_CH1_DQ42 MEM_CH1_DQ43 MEM_CH1_DQ44 MEM_CH1_DQ45 MEM_CH1_DQ46 MEM_CH1_DQ47 MEM_CH1_DQ48 MEM_CH1_DQ49 MEM_CH1_DQ50 MEM_CH1_DQ51 MEM_CH1_DQ52 MEM_CH1_DQ53 MEM_CH1_DQ54 MEM_CH1_DQ55 MEM_CH1_DQ56 MEM_CH1_DQ57 MEM_CH1_DQ58 MEM_CH1_DQ59 MEM_CH1_DQ60 MEM_CH1_DQ61 MEM_CH1_DQ62 MEM_CH1_DQ63 BF6 BD10 BE14 BB10 BA14 BB14 BD14 BE8 BG28 BH29 AV12 BD6 BD5 BB7 AV10 AY9 AY7 BF5 AV25 AW25 AU2 AT10 AT9 AU1 AY5 AV5 AV6 AV7 AT5 AT6 BD29 BB29 BJ22 BG22 BB12 BD12 BB5 BB6 BC2 BB1 BG9 BG10 BH9 BD16 BB16 BG11 BJ12 BG14 BG12 BH11 BG7 BH13 BG13 BH3 BG15 BG16 AY2 BD2 BD1 BE2 AW1 AW2 AY3 BG2 C OF 23 APOLLOLAKE_FCBGA1296 REV = 0.7 @ MEM_CH1_DQSP0 MEM_CH1_DQSN0 MEM_CH1_VREFDQ MEM_CH1_VREFCA MEM_CH1_DQSP1 MEM_CH1_DQSN1 MEM_CH1_BA0 MEM_CH1_BA1 MEM_CH1_BA2 MEM_CH1_DQSP2 MEM_CH1_DQSN2 MEM_CH1_RAS_N MEM_CH1_CAS_N MEM_CH1_WE_N MEM_CH1_DQSP3 MEM_CH1_DQSN3 MEM_CH1_ODT0 MEM_CH1_ODT1 MEM_CH1_DQSP4 MEM_CH1_DQSN4 MEM_CH1_CLKP1 MEM_CH1_CLKN1 MEM_CH1_DQSP5 MEM_CH1_DQSN5 MEM_CH1_CLKP0 MEM_CH1_CLKN0 MEM_CH1_DQSP6 MEM_CH1_DQSN6 MEM_CH1_CKE0 MEM_CH1_CKE1 MEM_CH1_DQSP7 MEM_CH1_DQSN7 NCTF5 NCTF6 MEM_CH1_MA0 MEM_CH1_MA1 MEM_CH1_MA2 MEM_CH1_MA3 MEM_CH1_MA4 MEM_CH1_MA5 MEM_CH1_MA6 MEM_CH1_MA7 MEM_CH1_MA8 MEM_CH1_MA9 MEM_CH1_MA10 MEM_CH1_MA11 MEM_CH1_MA12 MEM_CH1_MA13 MEM_CH1_MA14 MEM_CH1_MA15 MEM_CH1_CS0_N MEM_CH1_CS1_N NCTF7 NCTF8 MEM_CH1_DQSN8 MEM_CH1_DQSP8 MEM_CH1_CB7 MEM_CH1_CB6 MEM_CH1_CB5 MEM_CH1_CB4 MEM_CH1_CB3 MEM_CH1_CB2 MEM_CH1_CB1 MEM_CH1_CB0 AT30 AR29 BH6 BG8 BH15 BJ6 BH4 BH7 AW16 AV16 BB21 BD21 BD19 BE19 BG18 BG17 BH17 BJ16 BD17 AW17 AV17 BB17 BE23 BD23 BB23 BA23 AW19 BA19 AW21 AW23 AT21 AR21 C OF 23 APOLLOLAKE_FCBGA1296 REV = 0.7 @ B B A A Issued Date Title LC Future Center Secret Data Security Classification 2013/03/26 Deciphered Date SOC (DDR3L CHB) 2014/01/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER Size C Date: Document Number Rev 1.0 DG424/DG524 Thursday, March 09, 2017 Sheet of 58 1 DDI0_RCOMP_P DDI0_TXP_0 DDI0_TXN_0 DDI1_DDC_SCL DDI1_DDC_SDA DDI0_TXP_1 DDI0_TXN_1 RC2 402_0402_1% 28 CPU_EDP_AUX 28 CPU_EDP_AUX# CPU_EDP_AUX CPU_EDP_AUX# EDP_RCOMP_N EDP_RCOMP_P D EDP_RCOMP_N eDP +1.8V_PU 28 CPU_EDP_TX0+ 28 CPU_EDP_TX028 CPU_EDP_TX1+ 28 CPU_EDP_TX1- AG7 AG9 CPU_EDP_TX1+ CPU_EDP_TX1- AG12 AG10 DDI0_RCOMP_P DDI0_RCOMP_N EDP_TXP_0 EDP_TXN_0 DDI0_AUXP DDI0_AUXN EDP_TXP_1 EDP_TXN_1 EDP_TXP_2 EDP_TXN_2 AC7 AC9 10K_0404_4P2R_5% DDI0_TXP_3 DDI0_TXN_3 EDP_RCOMP_N EDP_RCOMP_P AC6 AC5 DDPB_CLK DDPB_DATA DDI0_TXP_2 DDI0_TXN_2 EDP_AUXP EDP_AUXN AG5 AG6 CPU_EDP_TX0+ CPU_EDP_TX0- RPC22 AH10 AH9 DDI1_AUXP DDI1_AUXN EDP_TXP_3 EDP_TXN_3 DDI1_TXP_0 DDI1_TXN_0 DDI1_TXP_1 DDI1_TXN_1 DDI PORT LIST Port DDI0 DDI1 EDP Device HPD Net VGA_HPD# HDMI_HPD# EDP_HPD# DP TO VGA HDMI eDP DDI1_TXP_2 DDI1_TXN_2 HPD Pin DDI1_TXN_3 DDI1_TXP_3 C50 A50 P48 AK3 AK2 +1.8V_PU AM3 AM2 EDP_HPD# AL2 AL1 AG1 AG2 100K_0402_5% D EDP_HPD DDI0_RCOMP_P DDI0_RCOMP_N EDP_HPD# EDP_HPD# 10 AM16 AM15 AK16 AK15 QC1B D AF2 AF3 HDMI_TX2+ HDMI_TX2- AD3 AD2 HDMI_TX1+ HDMI_TX1- AC1 AC2 HDMI_TX0+ HDMI_TX0- AB2 AB3 HDMI_CLKHDMI_CLK+ CPU_EDP_HPD G HDMI_TX2+ 32 HDMI_TX2- 32 HDMI D2 HDMI_TX1+ 32 HDMI_TX1- 32 HDMI D1 HDMI_TX0+ 32 HDMI_TX0- 32 HDMI D0 HDMI_CLKHDMI_CLK+ HDMI CLK 32 32 D 28 G L2N7002KDW1T1G_SOT363-6 S S L2N7002KDW1T1G_SOT363-6 QC1A RC3 100K_0402_5% EDP_HPD# RC9388 @ 0_0402_5% CPU_EDP_HPD OF 23 APOLLOLAKE_FCBGA1296 REV = 0.7 @ +3VS +3VALW UC1F RC9359 AH3 AH2 DDI0_DDC_SCL DDI0_DDC_SDA A54 C54 EDP_RCOMP_P DDPB_CLK DDPB_DATA 32 DDPB_CLK 32 DDPB_DATA DDI0_RCOMP_N APL_SOC UC1E B49 C49 @ eDP RCOMP is used for DDI0/DDI1 ports of HDMI/DP as well as the eDP interface DDI0_RCOMP is not used RC1 402_0402_1% +3VS +3VALW APL_SOC M45 M43 PNL1_VDDEN PNL1_BKLTEN PNL1_BKLTCTL G2 PCH_LCD_VDDEN_Q PCH_ENBKL PCH_BKLT_CTRL_Q PCH_BKLT_CTRL_Q PCH_LCD_VDDEN_Q G1 C52 B53 C53 QC2A PJT138K_SOT363-6 MDSI_A_TE MDSI_C_TE @ QC3B PJT138K_SOT363-6 G1 S1 GPIO_199 GPIO_200 C47 B47 C46 D1 PNL0_VDDEN PNL0_BKLTEN PNL0_BKLTCTL QC2B PJT138K_SOT363-6 S1 A50 C50 32 HDMI_HPD# MIPI_I2C_SDA MIPI_I2C_SCL B51 C51 G2 S2 D2 AK13 AM13 AM9 AM7 MDSI_C_CLKP MDSI_C_CLKN PCH_ENVDD MDSI_A_CLKP MDSI_A_CLKN @ 28 D1 MDSI_C_DP_3 MDSI_C_DN_3 PCH_EDP_PWM AM12 AM10 @ MDSI_A_DP_3 MDSI_A_DN_3 AM5 AM6 MDSI_C_DP_2 MDSI_C_DN_2 D2 MDSI_C_DP_1 MDSI_C_DN_1 MDSI_A_DP_2 MDSI_A_DN_2 RPC3 10K_0404_4P2R_5% RPC2 10K_0404_4P2R_5% AP2 AP3 MDSI_A_DP_1 MDSI_A_DN_1 AK7 AK6 S2 AP6 AP5 MDSI_C_DP_0 MDSI_C_DN_0 AR2 AR1 AP15 AP13 MDSI_A_DP_0 MDSI_A_DN_0 C AP12 AP10 C QC3A PJT138K_SOT363-6 PJT138K[Vgs(th)