A B C D E 1 Compal confidential Schematics Document Mobile Penryn uFCPGA with Intel Cantiga_GM+ICH9-M core logic 2010-04-08 NCL50 REV:1.0 4 Compal Secret Data Security Classification 2007/08/28 Issued Date 2006/03/10 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Compal Electronics, Inc Cover Sheet Size Document Number Custom Montevina UMA Date: Rev 0.2 LA6121P Wednesday, April 14, 2010 Sheet E of 46 A B C Compal confidential D E Montevina 14" UMA CK505 Mobile Penryn/Merom Thermal Sensor EMC1402 72QFN Clock Generator SLG8SP553V uFCPGA-478 CPU P06 P17 P6, 7, Fan conn P06 H_A#(3 35) FSB H_D#(0 63) LVDS Panel Interface P19 CRT 667/800/1066 MHz 1.05V DDR3 800/1066MHz 1.5V Intel Cantiga MCH DDR3 SO-DIMM X2 BANK 0, 1, 2, P15, 16 Dual Channel FCBGA 1329 P18 USB conn x3 P9,10, 11, 12, 13, 14 P30 2 DMI X4 USB2.0 X12 C-Link BT Conn P30 USB Camera PCI-E BUS*2 Azalia Intel ICH9-M RTL8103EL (10/100M) Mini-Card P25 SATA Slave CardReader RTS5159 P20,21,22,23 P26 P26 in1 Slot P27 P27 RJ45/11 CONN LPC BUS P25 SATA Master-1 mBGA-676 WLAN P19 Audio CKT AMP & Audio Jack Codec_AL272 TPA6017A2 P28 P28 SATA HDD Connector P24 ENE KB926 P31 Int.KBD Touch Pad CONN P31 P32 USB Board Conn USB conn x3 SATA ODD ConnectorP24 SPI SPI ROM SST25VF080P30 ZZZ3 4 RTC CKT LED P21 P32 PCB Compal Secret Data Security Classification DC/DC Interface CKT 2006/03/10 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC P33 A 2006/02/13 Issued Date B C D Title Compal Electronics, Inc Block Diagram Size Document Number Custom Montevina UMA Date: Rev 0.2 LA6121P Thursday, April 15, 2010 Sheet E of 46 A Symbol Note : Voltage Rails O MEANS ON USB assignment: X MEANS OFF : means Digital Ground USB-0 Right side daughter board USB-0 Right side daughter board USB-2 Left side : means Analog Ground USB-3 X power plane USB-4 Camera USB-5 WLAN +5VALW +B +1.8V +5VS +1.5V +3VS +3VALW USB-7 Cardreader 45@ : means need be mounted when 45 level assy or rework stage +1.5VS +VCCP USB-8 X USB-9 X DEBUG@ : means just reserve for debug +CPU_CORE State USB-6 Bluetooth @ : means just reserve , no build USB-10 X BATT @ : means need be mounted when 45 level assy or rework stage +0.75VS USB-11 X CONN@ : means ME part PCIe assignment: PCIe-1 X S0 O O O O S1 O O O O S3 O O O X S5 S4/AC O O X X S5 S4/ Battery only O X X X S5 S4/AC & Battery don't exist X X X X PCIe-2 X PCIe-3 WLAN PCIe-4 GLAN (Realtek) PCIe-5 X PCIe-6 X I2C / SMBUS ADDRESSING DEVICE HEX ADDRESS DDR SO-DIMM A0 10100000 DDR SO-DIMM A4 10100100 CLOCK GENERATOR (EXT.) D2 11010010 SMBUS Control Table SOURCE SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2 ICH_SMBCLK ICH_SMBDATA DDC2_CLK DDC2_DATA INVERTER BATT SERIAL EEPROM Thermal Sensor SODIMM CLK CHIP MINI CARD LCD KB926 X V X X X X X X KB926 X X X V X X X X ICH9 X X X X V V V X Cantiga X X X X X X X V 43184330L01： ： UMA GL PR FF- 43184330L01： ：Main@/DEBUG@/NewC@ PCB： ：DA60000GI00 ->M/B Compal Secret Data Security Classification 2007/08/28 Issued Date Deciphered Date 2006/03/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A Title Compal Electronics, Inc Notes List Size Document Number Custom Montevina UMA Date: Rev 0.2 LA6121P Wednesday, April 14, 2010 Sheet of 46 40mA +3VAUX_BT D D 20mA 10mA 177mA 0.35A AC INVPWR_B+ ICH9 LVDS CON 250mA 278mA LAN VIN 1.7A 2A 5.89A +3VALW 3.35A +3VS 1500mA B++ 250mA 1A C 0.58A B+ 1.3A +5VALW DDR3 1.8A 657mA DC 0.3A BATT 1.9A B+++ 12.11A 2.2A +1.5VS 1.56A 3.7A +1.8V ICH9 1.05V_B+ 1.26A +VCCP 2.3A 2A A CPU_B+ 10mA +VCC_CORE 34A/1.025V ICH9 +LCDVDD +3VS_CK505 C Mini card (WLAN) ODD SATA B Web Camera ICH9 MCH CPU CPU A Compal Secret Data Security Classification Issued Date 2007/08/28 Deciphered Date 2006/03/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc Power delevry Size C Date: LVDS CON MCH 1.17A 4.7A 700mA ICH_VCC1_5 ICH9 B 3.7 X 3=11.1V RTS5159 +5VAMP +1.5V +0.75VS SPI ROM +VDDA ALC272 +5VS 7A +3VALW_EC Document Number Rev 0.2 Montevina UMA LA6121P Wednesday, April 14, 2010 Sheet of 46 A 1 Compal Secret Data Security Classification 2007/08/28 Issued Date Deciphered Date 2006/03/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A Title Compal Electronics, Inc Notes List Size Document Number Custom Montevina UMA Date: Rev 0.2 LA6121P Wednesday, April 14, 2010 Sheet of 46 +3VS ITP-XDP Connector @R1 @ R1 XDP_DBRESET# H_A#[3 16] H_ADSTB#1 21 21 21 21 H_STPCLK# H_INTR H_NMI H_SMI# H_A20M# H_FERR# H_IGNNE# A6 A5 C4 H_STPCLK# H_INTR H_NMI H_SMI# D5 C6 B4 A3 M4 N5 T2 V3 B2 D2 D22 D3 F6 B CONTROL BR0# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# A20M# FERR# IGNNE# H1 E2 G5 H_ADS# H_BNR# H_BPRI# H5 F21 E1 H_DEFER# H_DRDY# H_DBSY# F1 H_BR0# D20 B3 H_IERR# H_INIT# H_ADS# H_BNR# H_BPRI# 54.9_0402_1% XDP_TMS R3 54.9_0402_1% XDP_TDO R4 54.9_0402_1% XDP_TRST# R7 54.9_0402_1% XDP_TCK R8 54.9_0402_1% D H_BR0# H4 H_LOCK# C1 F3 F4 G3 G2 H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY# G6 E4 H_HIT# H_HITM# AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET# PROCHOT# THERMDA THERMDC THERMTRIP# BCLK[0] BCLK[1] H_THERMDA_R H_THERMDC_R C7 H_THERMTRIP# A22 A21 CLK_CPU_BCLK CLK_CPU_BCLK# H CLK 21 H_LOCK# H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY# 9 9 Place TP with a GND 0.1" away H_HIT# H_HITM# H_PROCHOT# D21 A24 B25 This shall place near CPU T1 LOCK# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# 9 H_DEFER# H_DRDY# H_DBSY# H_INIT# RESET# RS[0]# RS[1]# RS[2]# TRDY# THERMAL STPCLK# LINT0 LINT1 SMI# RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] IERR# INIT# HIT# HITM# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# ICH 21 H_A20M# 21 H_FERR# 21 H_IGNNE# Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 DEFER# DRDY# DBSY# ADDR GROUP_1 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1 C K3 H2 K2 J3 L1 ADS# BNR# BPRI# 03/18 PV： ： Delete XDP connector C +3VS PV： ： Checklist Ver 1.5 change to 56 ohm XDP_DBRESET# R13 R14 R15 56_0402_1% 0_0402_5% 0_0402_5% 1 H_THERMTRIP# CLK_CPU_BCLK CLK_CPU_BCLK# 0.1U_0402_16V4Z H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#[17 35] H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# XDP/ITP SIGNALS H_ADSTB#0 J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 22 +VCCP 9,21 +3VS 17 17 C2 U1 SMB_EC_CK2 H_THERMDA DP SMDATA SMB_EC_DA2 H_THERMDC 2200P_0402_50V7K THERM# DN ALERT# R6 H_THERMDA H_THERMDC C3 1 VDD SMCLK THERM# GND SMB_EC_CK2 31 SMB_EC_DA2 31 10K_0402_5% +3VS 04/29 R16 10K_0402_5% MV1 reserve 10K for 2nd source EMC1402-1-ACZL-TR_MSOP8 Address:100_1100 H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil RESERVED 9 9 +VCCP R2 JCPU1A H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB#0 ADDR GROUP_0 1K_0402_5% XDP_TDI D Change value in 5/02 PV： ： follow check list ver:1.5 change to 51 ohm 04/29 MV1 R2~R8 change to 54.9 Ohm, follow checklist 2.0 B For Merom, R14 and R15 are 0ohm For Penryn, R14 and R15 are 100ohm PWM Fan Control circuit 04/29 MV1 change R14、 、 R15 to ohm +5VS Modify as KSWAA, need double check the CONN pin define 10/24 Prince Penryn 1A D34 1SS355_SOD323-2 C62 10U_0805_10V4Z JP2 @ 2 @ R17 56_0402_5% +FAN1 1 2 1 +VCCP C OCP# +FAN1 22 31 EN_DFAN1 10mil +VCCP GND GND GND GND D11 @ C168 @ 1000P_0402_25V8J GND GND CONN@ ACES_85205-03001 BAS16_SOT23-3 APL5607KI-TRG_SO8 C63 10U_0805_10V4Z A EN VIN VOUT VSET 0.01U_0402_16V7K E OCP# @ Q1 MMBT3904_NL_SOT23-3 B H_PROCHOT# U6 +3VS FAN_SPEED1 31 A C60 @ R18 56_0402_5% R50 10K_0402_5% Compal Secret Data Security Classification H_IERR# 2007/08/28 Issued Date 2006/03/10 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc Penryn(1/3)-AGTL+/ITP-XDP Size Document Number Custom Montevina UMA Date: Rev 0.2 LA6121P Thursday, April 15, 2010 Sheet of 46 +VCC_CORE T2 T3 T4 T5 T6 17 17 17 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2 +V_CPU_GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2 AD26 C23 D25 C24 AF26 AF1 A26 C3 B22 B23 C21 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2] MISC H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3 COMP[0] COMP[1] COMP[2] COMP[3] R26 U26 AA1 Y1 COMP0 COMP1 COMP2 COMP3 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# E5 B5 D24 D6 D7 AE6 H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# H_PSI# DATA GRP D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# JCPU1C H_DSTBN#2 H_DSTBP#2 H_DINV#2 H_D#[48 63] H_DSTBN#3 H_DSTBP#3 H_DINV#3 H_DPRSTP# 9,21,41 H_DPSLP# 21 H_DPWR# H_PWRGOOD 21 H_CPUSLP# H_PSI# 41 R23 R24 R25 R26 Penryn * Route the TEST3 and TEST5 signals through a ground referenced Zo = 55-ohm trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection B CPU_BSEL CPU_BSEL2 CPU_BSEL1 Resistor placed within 0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal COMP[0,2] trace width is 18 mils COMP[1,3] trace width is mils CPU_BSEL0 166 1 200 266 0 A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067] AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] D +VCCP R19 G21 +VCCPA +VCCPB V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] VCCA[01] VCCA[02] B26 C26 VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] AD6 AF5 AE5 AF4 AE3 AF3 AE2 VCCSENSE VSSSENSE 1 2 0_0402_5% 0_0402_5% C R20 + C6 330U_D2E_2.5VM_R7 +1.5VS CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 AF7 VCCSENSE AE7 VSSSENSE 41 41 41 41 41 41 41 VCCSENSE 41 VSSSENSE 41 C7 0.01U_0402_16V7K 1K_0402_5% 1K_0402_5% 1 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# +VCC_CORE 27.4_0402_1% @ R21 @ R22 H_DSTBN#1 H_DSTBP#1 H_DINV#1 D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2 54.9_0402_1% 9 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 DATA GRP C H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1 D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 27.4_0402_1% H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[16 31] E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 DATA GRP D 9 9 H_D#[32 47] JCPU1B H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0 54.9_0402_1% H_D#[0 15] DATA GRP 10U_0603_6.3V6M C8 Near pin B26 B Penryn Length match within 25 mils The trace width/space/other is 20/7/25 +VCCP +V_CPU_GTLREF +VCC_CORE R27 1K_0402_1% R28 100_0402_1% VCCSENSE R30 100_0402_1% VSSSENSE R29 2K_0402_1% Close to CPU pin within 500mils Close to CPU pin AD26 within 500mils A Compal Secret Data Security Classification 2007/08/28 Issued Date A 2006/03/10 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc Penryn(2/3)-AGTL+/ITP-XDP Size Document Number Custom Montevina UMA Date: Rev 0.2 LA6121P Thursday, April 15, 2010 Sheet of 46 +VCC_CORE Place these capacitors on L8 (North side,Secondary Layer) C9 10U_0805_6.3V6M C10 10U_0805_6.3V6M C11 10U_0805_6.3V6M C12 10U_0805_6.3V6M C13 10U_0805_6.3V6M C14 10U_0805_6.3V6M C15 10U_0805_6.3V6M C16 10U_0805_6.3V6M D D +VCC_CORE JCPU1D B P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25 Place these capacitors on L8 (North side,Secondary Layer) C17 10U_0805_6.3V6M C18 10U_0805_6.3V6M C19 10U_0805_6.3V6M C20 10U_0805_6.3V6M C21 10U_0805_6.3V6M C22 10U_0805_6.3V6M C23 10U_0805_6.3V6M C24 10U_0805_6.3V6M +VCC_CORE Place these capacitors on L8 (North side,Secondary Layer) C25 10U_0805_6.3V6M C26 10U_0805_6.3V6M C27 10U_0805_6.3V6M C28 10U_0805_6.3V6M C29 10U_0805_6.3V6M C30 10U_0805_6.3V6M C31 10U_0805_6.3V6M C32 10U_0805_6.3V6M +VCC_CORE Place these capacitors on L8 (North side,Secondary Layer) C33 10U_0805_6.3V6M C34 10U_0805_6.3V6M C35 10U_0805_6.3V6M C36 10U_0805_6.3V6M C37 10U_0805_6.3V6M C38 10U_0805_6.3V6M C39 10U_0805_6.3V6M C40 10U_0805_6.3V6M C Mid Frequence Decoupling ESR 1980uF Near CPU CORE regulator C41 + @ C42 + C43 + C44 + 330U_D2E_2.5VM_R9M +VCC_CORE 330U_D2E_2.5VM_R9M VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] 330U_D2E_2.5VM_R9M VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] 330U_D2E_2.5VM_R9M C A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 B 11/21 Change ESR=7m ohm +VCCP C45 0.1U_0402_10V6K Inside CPU center cavity in rows C46 0.1U_0402_10V6K C47 0.1U_0402_10V6K C48 0.1U_0402_10V6K C49 0.1U_0402_10V6K C50 0.1U_0402_10V6K Penryn A A Compal Secret Data Security Classification 2007/08/28 Issued Date 2006/03/10 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc Penryn(3/3)-AGTL+/ITP-XDP Size Document Number Custom Montevina UMA Date: Rev 0.2 LA6121P Wednesday, April 14, 2010 Sheet of 46 2 T25 T26 T27 T28 BG23 BF23 BH18 BF18 C54 RESERVED L9 M8 AA6 AE5 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 B15 K13 F13 B13 B14 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 B6 F12 C8 H_RS#0 H_RS#1 H_RS#2 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 7 7 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 MCH_CLKSEL0 T25 MCH_CLKSEL1 R25 MCH_CLKSEL2 P25 P20 P24 CFG5 C25 CFG6 N24 CFG7 M24 CFG8 E21 CFG9 C23 CFG10 C24 CFG11 N21 CFG12 P21 CFG13 T21 CFG14 R20 CFG15 M20 CFG16 L21 CFG17 H21 CFG18 P29 CFG19 R28 CFG20 T28 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 0.1U_0402_16V4Z Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20 PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PM_PWROK THERMTRIP# DPRSLPVR @ C55 +1.5V R54 R55 1 C59 R48 10K_0402_1% C57 2 BC28 AY28 AY36 BB36 DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB BA17 AY16 AV16 AR13 DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB# BD17 AY17 BF15 AY13 M_ODT0 M_ODT1 M_ODT2 M_ODT3 BG22 BH21 SMRCOMP SMRCOMP# BF28 BH28 SMRCOMP_VOH SMRCOMP_VOL AV42 AR36 BF17 BC36 V_DDR_MCH_REF SM_PWROK SM_REXT TP_SM_DRAMRST# B38 A38 E41 F41 CLK_MCH_DREFCLK CLK_MCH_DREFCLK# MCH_SSCDREFCLK MCH_SSCDREFCLK# F43 E43 CLK_MCH_3GPLL CLK_MCH_3GPLL# AE41 AE37 AE47 AH39 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 AE40 AE38 AE48 AH40 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 AE35 AE43 AE46 AH42 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 AD35 AE44 AF46 AH43 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1 SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1 SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF SM_PWROK SM_REXT SM_DRAMRST# PEG_CLK PEG_CLK# R29 B7 N33 P32 AT40 AT11 T20 R32 BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1 A47 PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 15 15 16 16 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 R34 R35 15 15 16 16 DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB 15 15 16 16 DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB# 15 15 16 16 M_ODT0 M_ODT1 M_ODT2 M_ODT3 D 15 15 16 16 +1.5V 80.6_0402_1% 80.6_0402_1% 1 Follow Design Guide For Cantiga: 80.6ohm @ R36 R37 0_0402_5% 499_0402_1% 1 SM_DRAMRST# 15,16 CLK_MCH_DREFCLK CLK_MCH_DREFCLK# MCH_SSCDREFCLK MCH_SSCDREFCLK# CLK_MCH_3GPLL CLK_MCH_3GPLL# 17 17 17 17 17 17 C DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 22 22 22 22 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 22 22 22 22 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 22 22 22 22 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 22 22 22 22 R1120 10K_0402_5%~D D25 B33 B32 G33 F33 E33 +1.5V SYSON 31,33,39 CH751H-40PT_SOD323-2 SM_PWROK DDR3_SM_PWROK 39 B delete test point for Placement.11/17 GFX_VR_EN C34 CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF AH37 AH36 AN36 AJ35 AH34 +VCCP CL_CLK0 CL_DATA0 M_PWROK CL_RST# +CL_VREF TSATN# N28 M28 G36 E36 K36 H36 B12 C56 0.1U_0402_16V4Z Delete them for placement 11/23 T60 T61 CLKREQ#_7 MCH_ICH_SYNC# TSATN# R737 R43 1K_0402_1% CL_CLK0 22 CL_DATA0 22 M_PWROK 22,31 CL_RST# 22 0621 add CLK and DAT for DVI DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC# R44 499_0402_1% CLKREQ#_7 17 MCH_ICH_SYNC# 56_0402_5% +VCCP TSATN# 31 22 *R44*Follow Intel feedback T29 HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC B28 B30 B29 C29 A28 T45 T51 A T52 T53 0830 Add pull-up and pull-down resistor Compal Secret Data Security Classification 2007/08/28 Issued Date Near B3 pin 2006/03/10 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 CANTIGA ES_FCBGA1329 PV： ： follow check list ver:1.5 change to 10K ohm within 100 mils from NB V_DDR_MCH_REF +H_SWNG 221_0603_1% R47 0.1U_0402_16V4Z C58 R45 10K_0402_1% 0.1U_0402_16V4Z 100_0402_1% R52 0.1U_0402_16V4Z 2K_0402_1% A H_RCOMP 24.9_0402_1% 1K_0402_1% +H_VREF SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 NC +V_DDR_MCH_REF generated by DC-DC +VCCP R46 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20 PM 22 PM_BMBUSY# 7,21,41 H_DPRSTP# 15 PM_EXTTS#0 16 PM_EXTTS#1 22,31 PM_PWROK R41 100_0402_5% R42 0_0402_5% 20,25,26 PLT_RST# 6,21 H_THERMTRIP# 22,41 DPRSLPVR AR24 AR21 AU24 AV20 DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# 10K_0402_5% MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 6 6 6 6 10K_0402_5% SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1 DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 17 17 17 7 7 R40 17 17 7 7 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_RS#0 H_RS#1 H_RS#2 CLKREQ#_7 R39 10K_0402_5% M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 PM_EXTTS#1 R38 CLK L10 M7 AA5 AE6 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 CANTIGA ES_FCBGA1329 +VCCP RESERVED RESERVED RESERVED RESERVED DMI H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces AY21 DDR CLK/ CONTROL/COMPENSATION C52 2.2U_0603_6.3V4Z C51 J8 L3 Y13 Y1 Layout note: T24 +3VS H_AVREF H_DVREF Layout Note: H_RCOMP / H_VREF / H_SWNG trace width and spacing is 10/20 R33 1K_0402_1% AP24 AT21 AV24 AU20 A11 B11 RESERVED RESERVED RESERVED SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1 +H_VREF H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# B PM_EXTTS#0 H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_RS#_0 H_RS#_1 H_RS#_2 T22 T23 B31 B2 M1 GRAPHICS VID H_CPURST# H_CPUSLP# them for placement 11/23 20% of 1.5V VCC_SM SMRCOMP_VOL RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED ME C12 E11 R31 1K_0402_1% R32 Delete 3.01K_0402_1% H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12 AL34 AK34 AN35 AM35 T24 MISC H_RESET# H_CPUSLP# H_RESET# H_CPUSLP# H_SWING H_RCOMP SMRCOMP_VOH H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 80% of 1.5V VCC_SM H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 +1.5V HDA C5 E3 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 CFG +H_SWNG H_RCOMP A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20 RSVD C H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 2.2U_0603_6.3V4Z C53 D F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6 U2B 0.01U_0402_25V7K U2A H_D#[0 63] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_A#[3 35] HOST 0.01U_0402_25V7K Title Compal Electronics, Inc Cantiga(1/6)-AGTL/DMI/DDR Size Document Number Custom Montevina UMA Date: Rev 0.2 LA6121P Thursday, April 15, 2010 Sheet of 46 D D B DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 BB20 BD20 AY20 DDR_A_RAS# DDR_A_CAS# DDR_A_WE# DDR_A_RAS# DDR_A_CAS# DDR_A_WE# AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 SA_RAS# SA_CAS# SA_WE# 15 15 15 15 15 15 DDR_A_DM[0 7] SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 DDR_A_DQS[0 7] DDR_A_DQS#[0 7] DDR_A_MA[0 14] 15 15 15 15 CANTIGA ES_FCBGA1329 AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3 SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 SB_BS_0 SB_BS_1 SB_BS_2 BC16 BB17 BB33 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 SB_RAS# SB_CAS# SB_WE# AU17 BG16 BF14 DDR_B_RAS# DDR_B_CAS# DDR_B_WE# DDR_B_RAS# DDR_B_CAS# DDR_B_WE# SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 16 16 16 16 16 16 DDR_B_DM[0 7] B DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 U2E MEMORY BD21 BG18 AT25 SA_BS_0 SA_BS_1 SA_BS_2 A SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 MEMORY C AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12 SYSTEM DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_B_D[0 63] SYSTEM 16 U2D SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 DDR DDR_A_D[0 63] DDR 15 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 DDR_B_DQS[0 7] DDR_B_DQS#[0 7] 16 16 16 C DDR_B_MA[0 14] 16 B CANTIGA ES_FCBGA1329 A A Compal Secret Data Security Classification 2007/08/28 Issued Date 2006/03/10 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc Cantiga(2/6)-DDR3 A/B CH Size Document Number Custom Montevina UMA Date: Rev 0.2 LA6121P Thursday, April 15, 2010 Sheet 10 of 46 A B C D E Need to confirm LED courlor System LED +5VALW R971 0_0603_5% LED1 ON/OFFBTN_LED# LED2 B BATT_LOW_LED# A @ 21 Amber D53 BLUE1 SATA_LED# R146 120_0402_5% HT-297UD/CB _BLUE/AMB_0603 R1098 90.9_0402_1% +5VS HDD LED Modify as NBLB2 HT-191NB_BLUE_0603 R1101 90.9_0402_1% +5VALW HT-191NB_BLUE_0603 +3VALW System Power LED Battery Charge LED +3VS +5VS BATT_LOW_LED# 0_0603_5% Blue 1 R972 0_0603_5% @ R973 0_0603_5% BATT_CHG_LED# 31 R970 31 Blue BATT_CHG_LED# R120 100_0402_5% BT/WLAN LED LED3 31 WL_BT_LED# WL_BT_LED# HT-191UD_Amber_0603 Amber R151 150_0402_5% Modify as NBLB2, need double confirm CONN pin define 10/24 Prince To TP/B Conn JP23 Modify as new ID.2009/12/28 31 31 +5VALW +5VS TP_CLK TP_DATA JP60 TP_DATA SWL# TP_CLK 3 0.1U_0402_16V4Z D29 @ PSOT24C_SOT23 C701 D30 @ PSOT24C_SOT23 SWR# PSOT24C_SOT23 4/2 Add by Vivian SMT1-05_4P Update Footprint SWL# TP_CLK C880 @ 100P_0402_50V8J TP_DATA C881 @ 100P_0402_50V8J SWL# C882 @ 100P_0402_50V8J SWR# C879 @ 100P_0402_50V8J SW7 Left Switch SWR# SW6 Right Switch +5VS SMT1-05_4P OUT LID_SW# LID_SW# 31 R2406 100K_0402_5% C4 0.1U_0402_16V4Z Compal Secret Data Security Classification 2 10K_0402_5% R601 +3VL GND 10K_0402_5% R600 SWR# Modify as KCL00 A3212ELHLT-T SOT23W U7 VCC SWL# LID switch SMT1-05_4P +3VL TP Pin6 +5VS D31 SW8 2 TP Pin1 ON/OFFBTN ACES_85201-08051 CONN@ ON/OFFBTN ACES_85201-0605N CONN@ +5VS CAPS_LED# NUM_LED# CAPS_LED# NUM_LED# ON/OFFBTN_LED# 31 31 GND GND TP_CLK TP_DATA SWL# SWR# ON/OFFBTN_LED# 31 ON/OFFBTN 10 31 ON/OFFBTN_LED# ON/OFFBTN GND GND 6 2007/08/28 Issued Date LID_SW# A B 2006/07/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC C D Title Compal Electronics, Inc KBD, ON/OFF, SW, CIR Size Document Number Rev 0.2 Montevina UMA LA6121P Date: Thursday, April 15, 2010 Sheet E 32 of 46 +5VALW to +5VS Transfer +5VALW B+ +3VALW C762 330K_0402_5% 10U_0805_10V4Z D D D D C759 Q34B +3VALW +1.8V 2 1 OUT R639 SHDN 10K_0402_5% 22,31 SLP_S4# RUNON_1.5VS BYP G916-390T1UF_SOT23-5 R1117 100K_0402_1% 100K_0402_5% 40 SYSON# SYSON# 100K_0402_5% Q13A 9,31,39 SYSON D S R1113 1K_0402_5% SUSP SUSP 40 Q13B SUSP# SUSP# 31,38 2 G VOUT=1.25(1+R912/R913) VOUT=1.25(1+100k/215k)=1.83V +5VS +VCCP +1.5VS +3VS +1.5V H3 H4 H_3P1N H_4P0 H_3P1X3P6N +0.75VS H5 H_4P0 H6 H_4P0 H7 H_1P1 1 H2 H1 H_4P0 Discharge circuit C1406 0.1U_0402_25V4K Q44 2N7002_SOT23-3 SUSP R1116 0_0402_5% R640 C R1114 47K_0402_1% GND IN R1115 +3VL 2N7002DW-7-F_SOT363-6 330K_0402_5% @ AO4466_SO8 C1407 10U_0805_10V4Z 2 S S S G C1405 10U_0805_10V4Z D D D D C1404 0.1U_0402_16V4Z 10U_0805_10V4Z C766 U47 +3VL U34 +1.5VS B+ 0.01U_0402_16V7K +1.5V C765 2N7002DW-7-F_SOT363-6 +1.5V to +1.5VS Transfer DIM LED 2N7002DW-7-F_SOT363-6 C65 4700P_0402_25V7K 01/03 Sparate+5VS and +3VS power timing 2N7002DW-7-F_SOT363-6 R647 0.1U_0402_16V4Z R638 SUSP Q34A D C764 470_0402_5% C C763 RUNON_3VS R224 470_0402_5% SUSP AO4466_SO8 RUNON 10U_0805_10V4Z S S S G 1 C761 AO4466_SO8 R636 2 S S S G 10U_0805_10V4Z R223 330K_0402_5% U33 D D D D 0.1U_0402_16V4Z 10U_0805_10V4Z C760 D DEL DIM LED 9/30 Prince +3VS U32 +3VALW to +3VS Transfer +5VS B+ H16 H_3P0 H17 H18 H_3P0 1 1 FM3 H19 H_3P0 FM4 H20 H_3P0 H21 H_3P0 H23 H_3P0 1 1 FM2 1 FM1 1 SUSP H_4P0X5P0N 2N7002DW-7-F_SOT363-6 SYSON# Q12B Q12A 470_0402_5% 2N7002DW-7-F_SOT363-6 SUSP 1 Q9B H12 H_3P0 R646 470_0402_5% SUSP R643 470_0402_5% SUSP Q9A Q6B R645 470_0402_5% 2N7002DW-7-F_SOT363-6 SUSP 2N7002DW-7-F_SOT363-6 Q6A R644 470_0402_5% 2N7002DW-7-F_SOT363-6 R642 470_0402_5% 2N7002DW-7-F_SOT363-6 R641 1 B B Be used for Stand off 11/06 H22 H_3P0 Delete H8/9/10/11/13/14/15/22 for layout demand 11/28 A A Add H22 1202 Compal Secret Data Security Classification 2007/08/28 Issued Date 2006/07/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc DC/DC Interface Size Document Number Rev 0.2 Montevina UMA LA6121P Date: Thursday, April 15, 2010 Sheet 33 of 46 A B C D VIN ADPIN VIN PD2 LL4148_LL34-2 LL4148_LL34-2 PR9 68_1206_5% PC4 1000P_0402_50V7K N1 PQ1 @ SINGA_4TRJWT-R2513 PR13 68_1206_5% VS EC_ON 31 D S PC9 0.1U_0603_25V7K PQ309 SSM3K7002FU_SC70-3 G PR296 10K_0402_5% TP0610K-T1-E3_SOT23-3 PR14 22K_0402_1% PC13 0.22U_0603_25V7K PR15 100K_0402_1% 1 PC3 100P_0402_50V8J PC5 100P_0402_50V8J 1 PC2 1000P_0402_50V7K 2 2 1 PJPDC1 1 DC_IN_S1 2 PD3 BATT+ PL1 SMB3025500YA_2P PJP602 +CHGRTC 2 +3VLP PAD-OPEN 3x3m BATT++ PL25 HCB4532KF-800T90_1812 DC040003600 BATT+ PJP3 PH1 under CPU botten side : CPU thermal protection at 92 degree C Recovery at 70 degree C PC19 0.01U_0402_50V7K PR28 1K_0402_1% PR34 1K_0402_1% PH4 near main Battery CONN : Reverse BAT thermal protection at 90 degree C Recovery at 53 degree C PR32 100_0402_1% 31 SMB_EC_DA1 31 PR42 10K_0402_1% SMB_EC_CK1 PR40 22K_0402_1% PC20 0.1U_0603_25V7K VL 2 PR36 100_0402_1% SUYIN_200275MR009G180ZR @ 100K_0402_1% +3VALW +3VL 2 @ PR27 100K_0402_1% PC18 1000P_0402_50V7K PR33 PC17 1000P_0402_50V7K 10 11 2 G1 G2 PR43 14K_0402_1% VCC TMSNS1 GND RHYST1 OT1 TMSNS2 OT2 RHYST2 P/N:SD034140280 PH1 100K_0402_1%_NCP15WF104F03RC 1 +3VL 2 PR31 6.49K_0402_1% 37 PR35 1K_0402_1% 1 PU3 @ PR41 47K_0402_1% G718TM1U_SOT23-8 31 BATT_TEMP MAINPWON PH4 100K_0402_1%_NCP15WF104F03RC @ 4 Compal Secret Data Security Classification Issued Date 2007/05/29 Deciphered Date 2008/05/29 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title Compal Electronics, Inc DC Connector/CPU_OTP Size Document Number Rev 1.0 Montevina Blade UMA LA4105P Date: Sheet Thursday, April 15, 2010 D 34 of 46 A B C D PR8 1K_1206_5% A PR19 1K_1206_5% PD1 B+ PR23 PR38 1K_1206_5% 2 LL4148_LL34-2 100K_0402_5% PR24 1K_1206_5% 100K_0402_5% PR20 VIN A PQ7 TP0610K-T1-E3_SOT23-3 ACOFF Precharge detector Min typ Max H >L 14.589V 14.84V 15.243V L >H 15.562V 15.97V 16.388V 31,36 ACIN PR37 100K_0402_5% PQ4 DTC115EUA_SC70-3 PQ3 DTC115EUA_SC70-3 B B BATT ONLY Precharge detector Min typ Max H >L 6.138V 6.214V 6.359V L >H 7.196V 7.349V 7.505V 3 VL B+ PR26 2.2M_0402_5% N1 D PR30 47K_0402_5% P G LM393DR_SO8 PU12A PACIN + - O C 36 PQ5 2 SSM3K7002FU_SC70-3 G 1 PR25 255K_0402_1% PC15 0.01U_0402_25V7K PC16 1000P_0402_50V7K PR29 34K_0402_1% 6251VREF PR39 150K_0402_1% PC14 0.1U_0603_25V7K PRG++ - 1 + O LM393DR_SO8 PU12B RB715F_SOT323-3 36 PR21 511K_0402_1% 8 ACON P 36 G C EN0_TRIP 2 PD4 37 PR22 100K_0402_1% 0.01U_0402_25V7K PC161 N1 S PQ6 DTC115EUA_SC70-3 PR79 10K_0402_5% +5VALW 2 D D Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2009/2/6 Deciphered Date 2010/2/6 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title DCIN & DETECTOR Size Document Number Custom Date: Rev 0.1 LA-5442P Thursday, April 15, 2010 Sheet D 35 of 46 D D CP = 85%*Iada (Acer criteria); CP = 2.95A ADP_I = 19.9*Iadapter*Rsense Iada=0~3.42A(65W) B+ 2 CP mode Iinput=(1/0.02)((0.05*Vaclm)/2.39+0.05) CHGVADJ VCOMP ICM CSIP PHASE VREF UGATE CHLIM BOOT ACLIM VDDP VADJ LGATE GND PGND 16 15 14 13 1 PR92 2.2_0603_5% BST_CHG PC61 0.1U_0603_25V7K BST_CHGA DL_CHG PR224 10K_0402_1% 1 PR225 47K_0402_1% 3 PC65 680P_0402_50V7K B ACIN 31 PR226 10K_0402_1% PACIN C PQ38 B 1 2 4.35V per cell BATT+ 6251VDD PR227 20K_0402_1% E MMBT3904W_SOT323-3 3.294V PC66 4.7U_0805_6.3V6K 4V per cell 4.2V per cell PR88 0.02_1206_1% PR94 4.7_0603_5% CV mode 1.882V PQ23 PACIN SSM3K7002FU_SC70-3 G S PR90 4.7_1206_5% 26251VDD PR97 18.2K_0402_1% IREF=0.7224*Icharge IREF=0.43V~3.24V PL5 S COIL 10UH +-30% SIL1045RA-100PF 4.5A CHG PQ27 AO4468L_SO8 PD13 RB751V-40_SOD323-2 6251VDDP ACPRN 0V PC52 0.1U_0603_25V7K CSOP CHGVADJ 17 DH_CHG 19 D ISL6251AHAZ-T_QSOP24 PR99 31.6K_0402_1% CC=0.6~4.48A PC44 10U_1206_25V6M 1 PR223 14.3K_0402_1% PC214 1000P_0402_25V8J 18 20 PQ25 AO4466_SO8 CSIN 21 CSON 31 PR221 191K_0402_1% 12 PR95 11.5K_0402_1% Vaclim=2.39*((11.5K//152K)/((2.37K//152K)+(11.5K//152K))) 10 11 PR96 2.37K_0402_1% 6251VREF 6251aclim ICOMP PC55 0.047U_0603_16V7K PR83 20_0603_5% PR84 20_0603_5% PC58 0.1U_0603_25V7K PR86 2.2_0603_5% 28.2 LX_CHG PC68 10U_1206_25V6M PR93 140K_0402_1% ACOFF ACOFF B 31,35 6251VREF 1U_0402_16V7K CSOP PR82 20_0603_5% PC63 10U_1206_25V6M PQ28 DTC115EUA_SC70-3 35 PC60 CELLS VIN PD12 1SS355TE-17_SOD323-2 2 PQ22 DTC115EUA_SC70-3 22 C PR77 200K_0402_1% PC62 10U_1206_25V6M IREF ADP_I PR87 100_0402_1% CSON ACPRN VIN PD9 1SS355TE-17_SOD323-2 ACOFF 2 31 31 PR91 150K_0402_1% 1 ACON S 35 ACON 1 G 10K_0402_1% PC64 0.01U_0402_25V7K PACIN 6800P_0402_25V7K 2 PC59 100P_0402_50V8J @ D PQ26 SSM3K7002FU_SC70-3 35 PACIN EN 23 0.01U_0402_25V7K PR89 22K_0402_5% DCIN ACSET ACPRN PR85 6251_EN VDD PC67 0.1U_0603_25V7K 2 352 PC56 PC57 2 DCIN @ PC53 680P_0402_50V7K CSON S PACIN_1 3 PQ20 DTC115EUA_SC70-3 24 1 PR80 PR81 150K_0402_1% PU5 PC51 1U_0402_16V7K PR76 10K_0402_1% ACSETIN FSTCHG PR73 47K_0402_1% Structure> SD028100280 2010/03/05 PVT 19 Reserve location C71 for BKOFF# 2010/03/05 PVT 31 Change R1131 from 22ohm SD028220A80 to 0ohm SD028000080 2010/03/05 PVT D D Modify the lightness of LED2 32 Modify R120 from SD028220080(220ohm) to SD028100080(100ohm) 2010/03/15 Modify the lightness of LED2 32 Modify R146 from SD028300000(300ohm) to SD028120000(120ohm) 2010/03/15 PVT Modify the lightness of LED1/D53 32 Modify R1098/R1101 from SD028220080(220ohm) to SD00000LK80(90.9ohm) 2010/03/15 PVT Modify the lightness of LED3 32 Modify R151 from SD028300000(300ohm) to SD028150000(150ohm) 2010/03/15 PVT SPK noise issue 28 2010/03/15 PVT 28 Reserve C304 for +MIC1_VREFO 2010/03/15 PVT Add BT_OFF# pull high to +3VS 29 Install R603(10K) >SD028100280 2010/03/24 Pre_MP 11 Can't disable BT for combo card 26 Reserve R438 to connect BT_OFF# with JP7 pin5 2010/03/24 Pre_MP 12 Reserver ICH_susclk for EC's CLK IN 22/31 Delete T58 and reserver R592 2010/03/25 Pre_MP 13 Set E0 EC as main source 31 Install R1093 and uninstall R1091 2010/03/29 Pre_MP 14 Set E0 EC as main source 31 Change EC P/N to SA00001J5A0(E0) 2010/03/31 Pre_MP 15 Change R249 to 4.99K that have correct description 31 Change R249 from SD00000HN80 to SD014499180 2010/03/31 Pre_MP 16 Can't disable BT for combo card 26/29 Add location Q15(SB570020020), add location R155/R439(SD028000080), add location(SD028100280) 2010/04/01 Pre_MP 17 Reserver ICH_susclk for EC's CLK IN Reserver location R605 2010/04/08 Pre_MP Add C1409/C1410/C1411(SE070104Z80) 2010/04/08 Pre_MP 10 Avoid MIC noise issue Modify R436/r437 from SD014300280(30Kohm) to SD014150280(15Kohm) PVT C C 18 31 EMI Request 25 19 B B 20 21 22 23 24 25 26 27 A A 28 Compal Secret Data Security Classification 2007/08/28 Issued Date 2006/07/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc HW PIR Size Document Number Rev 0.3 Montevina Blade UMA LA4105P Date: Wednesday, April 14, 2010 Sheet 46 of 46 ... 10 9 11 1 11 3 11 5 11 7 11 9 12 1 12 3 12 5 12 7 12 9 13 1 13 3 13 5 13 7 13 9 14 1 14 3 14 5 14 7 14 9 15 1 15 3 15 5 15 7 15 9 16 1 16 3 16 5 16 7 16 9 17 1 17 3 17 5 17 7 17 9 18 1 18 3 18 5 18 7 18 9 19 1 19 3 19 5 19 7 19 9 2 01 203 10 ... 10 9 11 1 11 3 11 5 11 7 11 9 12 1 12 3 12 5 12 7 12 9 13 1 13 3 13 5 13 7 13 9 14 1 14 3 14 5 14 7 14 9 15 1 15 3 15 5 15 7 15 9 16 1 16 3 16 5 16 7 16 9 17 1 17 3 17 5 17 7 17 9 18 1 18 3 18 5 18 7 18 9 19 1 19 3 19 5 19 7 19 9 2 01 203 VREF_DQ... AVDD1 C14 70 25 C1397 AVDD2 C14 40 0.1U _04 02 _16 V7K 10 U _08 05 _ 10 V4Z C14 50 0.1U _04 02 _16 V7K 40mil FBM-L 11- 1 608 08- 800 LMT _06 03 D U 40 0 _06 03_5% 0. 1U _04 02 _16 V7K L 108 0. 1U _04 02 _16 V7K +VDDA 200 9 /02 /04 2 01 0 /02 /04