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A B C D E 1 su /x / Compal Confidential 2 p PEW76/86/96 M/B Schematics Document // m yc om AMD Danube Only UMA AMD Champlain Processor with RS880M/SB820M 2010-07-20 LA6552P REV: 1.0 ht : 4 2010/04/12 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/10/12 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Cover Page Document Number PEW/76/86/96 LA-6552P Thursday, July 22, 2010 Sheet E of 45 Rev B A B C E Danube Compal Confidential AMD S1G4 Processor PCB Model Name : PEW96 File Name : LA-6552P P/N : DA60000IM10 D ZZZ Memory BUS(DDR3) uPGA-638 Package Champlain page 6,7,8,9 LA-6552P MB Rev0: DA60000IM00 LA-6552P MB Rev1: DA60000IM10 LA-6552P MB Rev1: DAZ0FQ00200 LA-6552P RE1 M/B 204pin DDRIII-SO-DIMM X2 Dual Channel BANK 0, 1, 2, page 10,11 1.5V DDRIII 1066~1333MHz Hyper Transport Link 16 x 16 LVDS page 15 Thermal Sensor ADM1032 ATI RS880M page CRT uFCBGA-528 page 17 page 12,13,14 USB conn X3 A link Express2 Gen1 page 16 page 15 /x / HDMI Conn page 27 CMOS Camera ATI SB820M MINI Card Broadcom BCM57780 page 26 GPP1 page 24 GPP0 yc RJ45 LPC BUS // m page 25 LED RTC CKT ODD X1 Mini card (WL)X1 Card Reader RTS5137 USB port USB port USB port USB HD Audio Gen2 HDA Codec ALC272X page 30 SATA HDD Conn page 23 SATA ODD FFC Conn page 23 port port Audio AMP Phone Jack x2 page 31 Int.KBD page 29 ht page 28 USB X2 Bluetooth Conn page 28 Touch Pad Extend Card/B LID SW / MEDIA/B page 26 page 31 : page 32 page 18 page 26 ENE KB926 Fan Control page 29 S-ATA page 18,19,20,21,22 om WLAN 3.3V 24.576MHz/48Mhz uFCBGA-605 LAN(GbE) 3.3V 48MHz p su USB port 0,1,2 USB port page 27 page 29 EC I/O Buffer BIOS page 29 page 29 Power On/Off CKT page 32 DC/DC Interface CKT 4 page 33 Power Circuit 2010/04/12 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification page 34,35,36,37,38 39,40,41,42 2010/10/12 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Block Diagrams Document Number PEW/76/86/96 LA-6552P Thursday, July 22, 2010 Sheet E of 45 Rev B D D RTC MEM_MA_CLK1_P/N MEM_MA_CLK7_P/N S1G4 CPU SOCKET CPU_CLKP/N 200MHz CLK_NBHT Internal CLK GEN C ATI NB RS880M 100MHz yc om 1066MHz AMD su MEM_MB_CLK1_P/N MEM_MB_CLK7_P/N B_SODIMM ATI SB SB820M CLK_SBLINK_BCLK 100MHz AMD AMD 1066MHz SATA p A_SODIMM C 25MHz /x / 32.768K Hz CLK_48M_SD 48MHz 100MHz // m CLK_PCIE_WWAN CLK_PCIE_MINI1 100MHz CLK_PCIE_LAN WWAN Mini PCI Socket WLAN Mini PCI Socket ht CardReader RTS5137 : B B 100MHz GbE LAN BCM 57780 A A Compal Secret Data Security Classification 2010/04/12 Issued Date 2010/10/12 Deciphered Date Title CLOCK DISTRIBUTION THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom PEW/76/86/96 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev B LA-6552P Thursday, July 22, 2010 Sheet of 45 A B C D SIGNAL STATE Voltage Rails SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock HIGH HIGH HIGH HIGH ON ON ON ON Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF B+ AC or battery power rail for power circuit N/A N/A N/A +CPU_CORE Core voltage for CPU (1.375-1.5V) ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF +CPU_CORE_NB Voltage for On-die Northbridge of CPU(0.8-1.1V)ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF Full ON +CPU_VDDR 1.05V switched power rail ON OFF OFF +0.75V 0.75V switched power rail for DDR terminator ON ON OFF +1.1VS 1.1V switched power rail for NB VDDC & VGA ON OFF OFF +1.5V 1.5V power rail for CPU VDDIO and DDR ON ON OFF Vcc Ra/Rc/Re 1.5V power rail for MINI Card ON OFF OFF Board ID 1.8V switched power rail ON OFF OFF OFF +2.5VS 2.5V for CPU_VDDA ON OFF 3.3V always on power rail ON ON ON* +3VS 3.3V switched power rail ON OFF OFF +3V_LAN 3.3V power rail for LAN ON ON ON +5VALW 5V always on power rail ON ON ON* +5VS 5V switched power rail ON OFF OFF +VSB VSB always on power rail ON ON ON* +RTCVCC RTC power ON ON ON 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC 2 BTO Option Table p Interrupts V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V BTO Item PCB Revision EVT / PVT stage (w/ pach code) BOM Structure Bluetooth Vari-Bright No Vari-Bright HDMI BT@ VB@ UNVB@ HDMI@ EC SM Bus1 address // m yc REQ#/GNT# Board ID om External PCI Devices IDSEL# V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V BOARD ID Table Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF Device V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V /x / +1.5VS +1.8VS +3VALW Board ID / SKU ID Table for AD channel su E EC SM Bus2 address Address HEX Smart Battery 0001 011X b 16H Device Address ADI ADM1032 (CPU) 1001 100X b 98H 98H ht SB-Temp Sensor HEX : Device Project ID Table SB820 SM Bus address SB820 SM Bus address Device Address HEX Clock Generator (SILEGO SLG8SP626) 1101 001Xb D2 DDR DIMM1 1001 000Xb 90 DDR DIMM2 1001 010Xb 94 Device Board ID PCB Revision PEW76/86/96 Address Mini card 4 2010/04/12 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/10/12 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Notes List Document Number PEW/76/86/96 LA-6552P Thursday, July 22, 2010 Sheet E of 45 Rev B AMD CPU S1G4 +CPU_CORE BATTERY 12.6V BATT+ PU5 CHARGER ISL6261AHAZ-T PU15 ISL6265IRZ-T PU16 APL5508-25DC AC ADAPTOR 19V 90W +CPU_CORE 0.7~1.3V VDD CORE 36A +CPU_CORE_NB 0.8~1.2V VDDNB 4A 2.5V VDDA 250mA 1.5V VDDIO 3A 1.05V VDDR 1.5A 1.1V VLDT 1.5A +CPU_CORE_NB +2.5VS +1.05VS +1.05VS PU12 APL5915 VIN +1.1VS D D RAM DDRIII SODIMMX2 +1.5V PU7 RT8209BGQW B+ +1.5V 1.5V VDD_MEM 4A 0.75V VTT_MEM 0.5A +0.75VS PU10 APL5913 NorthBridge AMD RS880M +1.1VALW +1.1VALW +1.5V C VDDHTRX+HT 0.68A VDDPCIE 1.1A VDDHTTX 0.68A PLLs 0.23A 1.8V_S0 VDDA18 0.64A VDDG18 0.005A VDDLT18 0.22A PLLs 0.1A 3.3V_S0 VDDG33 0.06A AVDD 0.125A VDDLT33 0A No Use VDD18_MEM 1.8V 0.005A VDD_MEM 1.8V 0.23A +1.1VS C p U35 SI4800BDY +VDDCI om +GPU_CORE U36 SI4800BDY +1.5VS PU19 TSP51117RGYR PU17 APW7138NITRL VDDC 1.0V-1.1V 7.6A 1.1V_S0 +1.1VS /x / PU6 RT8209BGQW 1.0~1.1V +NB_CORE su PU8 RT8209BGQW VGA ATI Madison / Park 0.85~1.1V +1VSG PU10 APL5913 +1.8VS PU11 MP2121DQ +1.8VSP2 +1.8VSP1 +INVPWR_B+ // m +3VALW PU4 SN0806081 RHBR +5VALW LCD panel 15.6" PCIE_VDDC A DP[F:A]_VDD10 230 mA DPLL_VDDC 125 mA SPV10 100 mA 1.5V VDDR1 TBD A 1.8V PCIE_PVDD 40 mA PCIE_VDDR 400 mA TSVDD mA VDDR4 TBD mA VDD_CT 17 mA DP[F:A]_PVDD 20 mA DP[F:A]_VDD18 330 mA AVDD 70 mA VDD1DI 45 mA A2VDDQ 1.5 mA VDD2DI 50 mA DPLL_PVDD 75 mA MPV18 150 mA SPV18 50 mA U37 SI1800BDY 3.3V VDDR3 60 mA A2VDD 130 mA +3VS Delay +3VS_DELAY U34 SI4800BDY +5VS B+ 300mA FAN Control APL5607 1.1V_S0 +1.1VALW 1.1V_S5 +5VS 500mA 3.3V_S0 +3VALW U25/U40 TPS2061DRG4 +USB_VCCA 3.3V_S5 +USB_VCCB Audio AMP TPA6017A2 A USB X3 +5V Dual+1 2.5A +5V 25mA SATA Audio Codec ALC272X +5V 3A +5V 45mA +3.3V +3.3VS 25mA Realtek RTS5137 EC ENE KB926 +3.3VS 300mA +3.3VALW 30mA +3.3VS 3mA LAN BCM57780 ICS9LPRS488B +3.3VALW 750mA +3.3V 400mA Mini Card No Use RTC Bettary +1.5VS 500mA +3.3VS 1A +3.3VALW 330mA +1.1V Issued Date B 2.5~3.6V BAT VDDCR_11 1.1V 0.5A VDDAN_11_PCIE 1A VDDAN_11_SATA 0.8A VDDAN_11_CLK 0.4A VDDCR_11_S 113mA VDDAN_11_USB_S 200mA VDDCR_11_USB_S 197mA VDDPL_11_SYS_S VDDIO_33_PCIGP 0.020A VDDPL_33_PCIE 0.030A VDDPL_33_SATA 0.020A VDDPL_33_SYS VDDIO_33_S VDDPL_33_USB_S VDDAN_33_USB_S 0.2A VDDAN_33_S VDDXL_33_S VDDIO_AZ_S VDDCR_11_GBE_S VDDRF_GBE_S VDDIO_33_GBE_S VDDIO_GBE_S VDDIO_18_FC 2010/04/12 Deciphered Date 2010/10/12 Title POWER DELIVERY CHART Date: A VDDBT_RTC_G THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom PEW/76/86/96 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 2.4 A Compal Secret Data Security Classification 1.5V SouthBridge AMD SB820M ht +3.3 350mA VRAM 1GB 64Mx16 (K4B1G1646E) * +1.5VS : B 1.0V yc PU14 APL5913 VDDC 29 A VDDCI A Rev B LA-6552P Sheet Thursday, July 22, 2010 of 45 A B C D E 1 VLDT CAP +1.1VS 250 mil H_CADOP[0 15] H_CADIN[0 15] H_CADON[0 15] +1.1VS JCPU1A L0_CADIN_H0 L0_CADIN_L0 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H15 L0_CADIN_L15 AE2 AE3 AE4 AE5 L0_CADOUT_H0 L0_CADOUT_L0 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H15 L0_CADOUT_L15 AD1 AC1 AC2 AC3 AB1 AA1 AA2 AA3 W2 W3 V1 U1 U2 U3 T1 R1 AD4 AD3 AD5 AC5 AB4 AB3 AB5 AA5 Y5 W5 V4 V3 V5 U5 T4 T3 H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1 J3 J2 J5 K5 L0_CLKIN_H0 L0_CLKIN_L0 L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKOUT_H0 L0_CLKOUT_L0 L0_CLKOUT_H1 L0_CLKOUT_L1 Y1 W1 Y4 Y3 H_CTLIP0 H_CTLIN0 H_CTLIP1 H_CTLIN1 N1 P1 P3 P4 L0_CTLIN_H0 L0_CTLIN_L0 L0_CTLIN_H1 L0_CTLIN_L1 L0_CTLOUT_H0 L0_CTLOUT_L0 L0_CTLOUT_H1 L0_CTLOUT_L1 R2 R3 T5 R5 10U_0805_10V4Z H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7 H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15 ht 1 C2 10U_0805_10V4Z C3 0.22U_0603_16V4Z C4 0.22U_0603_16V4Z C5 180P_0402_50V8J C6 180P_0402_50V8J Near CPU Socket p E3 E2 E1 F1 G3 G2 G1 H1 J1 K1 L3 L2 L1 M1 N3 N2 E5 F5 F3 F4 G5 H5 H3 H4 K3 K4 L5 M5 M3 M4 N5 P5 VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3 10U_0805_10V4Z om VLDT_A0 VLDT_A1 VLDT_A2 VLDT_A3 C1 yc H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15 C7 HT LINK D1 D2 D3 D4 : TBD H_CADON[0 15] su +1.1VS H_CADOP[0 15] // m H_CADIN[0 15] H_CADIP[0 15] /x / H_CADIP[0 15] H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1 H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1 FOX_PZ63823-284S-41F_Champlian 4 2010/04/12 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/10/12 Deciphered Date Title AMD CPU S1G4 HT I/F THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D PEW/76/86/96 LA-6552P Thursday, July 22, 2010 Sheet E of 45 Rev B A B C D E Processor DDR3 Memory Interface JCPU1C DDRB_SDQ[63 0] MEM:DATA +1.5V R1 1K_0402_1% C8 1000P_0402_50V7K C11 A11 A14 B14 G11 E11 D12 A13 A15 A16 A19 A20 C14 D14 C18 D18 D20 A21 D24 C25 B20 C20 B24 C24 E23 E24 G25 G26 C26 D26 G23 G24 AA24 AA23 AD24 AE24 AA26 AA25 AD26 AE25 AC22 AD22 AE20 AF20 AF24 AF23 AC20 AD20 AD18 AE18 AC14 AD14 AF19 AC18 AF16 AF15 AF13 AC12 AB11 Y11 AE14 AF14 AF11 AD11 MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63 DDRB_SDM0 DDRB_SDM1 DDRB_SDM2 DDRB_SDM3 DDRB_SDM4 DDRB_SDM5 DDRB_SDM6 DDRB_SDM7 A12 B16 A22 E25 AB26 AE22 AC16 AD12 MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7 DDRB_SDQS0 DDRB_SDQS0# DDRB_SDQS1 DDRB_SDQS1# DDRB_SDQS2 DDRB_SDQS2# DDRB_SDQS3 DDRB_SDQS3# DDRB_SDQS4 DDRB_SDQS4# DDRB_SDQS5 DDRB_SDQS5# DDRB_SDQS6 DDRB_SDQS6# DDRB_SDQS7 DDRB_SDQS7# C12 B12 D16 C16 A24 A23 F26 E26 AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12 MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7 +CPU_VDDR +CPU_VDDR JCPU1B DDRA_ODT0 DDRA_ODT1 DDRA_SCS0# DDRA_SCS1# DDRA_CKE0 DDRA_CKE1 DDRA_CLK0 DDRA_CLK0# DDRA_CLK1 DDRA_CLK1# DDRA_SMA[15 0] DDRA_SBS0# DDRA_SBS1# DDRA_SBS2# DDRA_SRAS# DDRA_SCAS# DDRA_SWE# DDRA_ODT0 DDRA_ODT1 DDRA_SCS0# DDRA_SCS1# DDRA_CKE0 DDRA_CKE1 DDRA_CLK0 DDRA_CLK0# W17 MEM_VREF MB_RESET_L B18 MEM_MB_RST# MB0_ODT0 MB0_ODT1 MB1_ODT0 W26 W23 Y26 DDRB_ODT0 DDRB_ODT1 MB0_CS_L0 MB0_CS_L1 MB1_CS_L0 V26 W25 U22 DDRB_SCS0# DDRB_SCS1# MB_CKE0 MB_CKE1 J25 H26 DDRB_CKE0 DDRB_CKE1 DDRB_CLK0 DDRB_CLK0# T19 V22 U21 V19 MA0_ODT0 MA0_ODT1 MA1_ODT0 MA1_ODT1 T20 U19 U20 V20 MA0_CS_L0 MA0_CS_L1 MA1_CS_L0 MA1_CS_L1 J22 J20 MA_CKE0 MA_CKE1 MEMVREF Y10 VTT_SENSE N19 N20 E16 F16 Y16 AA16 P19 P20 MA_CLK_H5 MA_CLK_L5 MA_CLK_H1 MA_CLK_L1 MA_CLK_H7 MA_CLK_L7 MA_CLK_H4 MA_CLK_L4 MB_CLK_H5 MB_CLK_L5 MB_CLK_H1 MB_CLK_L1 MB_CLK_H7 MB_CLK_L7 MB_CLK_H4 MB_CLK_L4 P22 R22 A17 A18 AF18 AF17 R26 R25 DDRA_SMA0 DDRA_SMA1 DDRA_SMA2 DDRA_SMA3 DDRA_SMA4 DDRA_SMA5 DDRA_SMA6 DDRA_SMA7 DDRA_SMA8 DDRA_SMA9 DDRA_SMA10 DDRA_SMA11 DDRA_SMA12 DDRA_SMA13 DDRA_SMA14 DDRA_SMA15 N21 M20 N22 M19 M22 L20 M24 L21 L19 K22 R21 L22 K20 V24 K24 K19 MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15 MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8 MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15 P24 N24 P26 N23 N26 L23 N25 L24 M26 K26 T26 L26 L25 W24 J23 J24 DDRB_SMA0 DDRB_SMA1 DDRB_SMA2 DDRB_SMA3 DDRB_SMA4 DDRB_SMA5 DDRB_SMA6 DDRB_SMA7 DDRB_SMA8 DDRB_SMA9 DDRB_SMA10 DDRB_SMA11 DDRB_SMA12 DDRB_SMA13 DDRB_SMA14 DDRB_SMA15 DDRA_SBS0# DDRA_SBS1# DDRA_SBS2# R20 R23 J21 MA_BANK0 MA_BANK1 MA_BANK2 MB_BANK0 MB_BANK1 MB_BANK2 R24 U26 J26 DDRB_SBS0# DDRB_SBS1# DDRB_SBS2# DDRA_SRAS# DDRA_SCAS# DDRA_SWE# R19 T22 T24 MA_RAS_L MA_CAS_L MA_WE_L MB_RAS_L MB_CAS_L MB_WE_L U25 U24 U23 DDRB_SRAS# DDRB_SCAS# DDRB_SWE# DDRA_CLK1 DDRA_CLK1# PAD p MA_RESET_L T1 om C95 @ 10U_0805_10V4Z MEM_MA_RST# 39.2_0402_1% MEMZP AF10 MEMZN AE10 39.2_0402_1% MEM_MA_RST# H16 VDDR: DDR3 under 1033MHz set to 0.9V to save power VDDR1 MEM:CMD/CTRL/CLK VDDR5 VDDR2 VDDR6 VDDR3 VDDR7 VDDR4 VDDR8 VDDR9 MEMZP MEMZN VDDR_SENSE W10 AC10 AB10 AA10 A10 MEM_MB_RST# DDRB_ODT0 DDRB_ODT1 DDRB_SCS0# DDRB_SCS1# DDRB_CKE0 DDRB_CKE1 DDRB_CLK0 DDRB_CLK0# DDRB_CLK1 DDRB_CLK1# DDRB_CLK1 DDRB_CLK1# DDRB_SDM[7 0] DDRB_SMA[15 0] : R4 1 R5 R410 0_0603_5% D10 C10 B10 AD10 ht +1.5V 1.5A yc Place them close to CPU within 1" // m AMD suggest su /x / C9 0.01U_0402_25V7K MEM_VREF R2 1K_0402_1% DDRB_SDQ0 DDRB_SDQ1 DDRB_SDQ2 DDRB_SDQ3 DDRB_SDQ4 DDRB_SDQ5 DDRB_SDQ6 DDRB_SDQ7 DDRB_SDQ8 DDRB_SDQ9 DDRB_SDQ10 DDRB_SDQ11 DDRB_SDQ12 DDRB_SDQ13 DDRB_SDQ14 DDRB_SDQ15 DDRB_SDQ16 DDRB_SDQ17 DDRB_SDQ18 DDRB_SDQ19 DDRB_SDQ20 DDRB_SDQ21 DDRB_SDQ22 DDRB_SDQ23 DDRB_SDQ24 DDRB_SDQ25 DDRB_SDQ26 DDRB_SDQ27 DDRB_SDQ28 DDRB_SDQ29 DDRB_SDQ30 DDRB_SDQ31 DDRB_SDQ32 DDRB_SDQ33 DDRB_SDQ34 DDRB_SDQ35 DDRB_SDQ36 DDRB_SDQ37 DDRB_SDQ38 DDRB_SDQ39 DDRB_SDQ40 DDRB_SDQ41 DDRB_SDQ42 DDRB_SDQ43 DDRB_SDQ44 DDRB_SDQ45 DDRB_SDQ46 DDRB_SDQ47 DDRB_SDQ48 DDRB_SDQ49 DDRB_SDQ50 DDRB_SDQ51 DDRB_SDQ52 DDRB_SDQ53 DDRB_SDQ54 DDRB_SDQ55 DDRB_SDQ56 DDRB_SDQ57 DDRB_SDQ58 DDRB_SDQ59 DDRB_SDQ60 DDRB_SDQ61 DDRB_SDQ62 DDRB_SDQ63 DDRB_SBS0# DDRB_SBS1# DDRB_SBS2# DDRB_SRAS# DDRB_SCAS# DDRB_SWE# DDRB_SDQS0 DDRB_SDQS0# DDRB_SDQS1 DDRB_SDQS1# DDRB_SDQS2 DDRB_SDQS2# DDRB_SDQS3 DDRB_SDQS3# DDRB_SDQS4 DDRB_SDQS4# DDRB_SDQS5 DDRB_SDQS5# DDRB_SDQS6 DDRB_SDQS6# DDRB_SDQS7 DDRB_SDQS7# MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8 MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63 G12 F12 H14 G14 H11 H12 C13 E13 H15 E15 E17 H17 E14 F14 C17 G17 G18 C19 D22 E20 E18 F18 B22 C23 F20 F22 H24 J19 E21 E22 H20 H22 Y24 AB24 AB22 AA21 W22 W21 Y22 AA22 Y20 AA20 AA18 AB18 AB21 AD21 AD19 Y18 AD17 W16 W14 Y14 Y17 AB17 AB15 AD15 AB13 AD13 Y12 W11 AB14 AA14 AB12 AA12 DDRA_SDQ0 DDRA_SDQ1 DDRA_SDQ2 DDRA_SDQ3 DDRA_SDQ4 DDRA_SDQ5 DDRA_SDQ6 DDRA_SDQ7 DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ12 DDRA_SDQ13 DDRA_SDQ14 DDRA_SDQ15 DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ20 DDRA_SDQ21 DDRA_SDQ22 DDRA_SDQ23 DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQ26 DDRA_SDQ27 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQ30 DDRA_SDQ31 DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ36 DDRA_SDQ37 DDRA_SDQ38 DDRA_SDQ39 DDRA_SDQ40 DDRA_SDQ41 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDQ46 DDRA_SDQ47 DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ52 DDRA_SDQ53 DDRA_SDQ54 DDRA_SDQ55 DDRA_SDQ56 DDRA_SDQ57 DDRA_SDQ58 DDRA_SDQ59 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQ62 DDRA_SDQ63 MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7 E12 C15 E19 F24 AC24 Y19 AB16 Y13 DDRA_SDM0 DDRA_SDM1 DDRA_SDM2 DDRA_SDM3 DDRA_SDM4 DDRA_SDM5 DDRA_SDM6 DDRA_SDM7 MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7 G13 H13 G16 G15 C22 C21 G22 G21 AD23 AC23 AB19 AB20 Y15 W15 W12 W13 DDRA_SDQS0 DDRA_SDQS0# DDRA_SDQS1 DDRA_SDQS1# DDRA_SDQS2 DDRA_SDQS2# DDRA_SDQS3 DDRA_SDQS3# DDRA_SDQS4 DDRA_SDQS4# DDRA_SDQS5 DDRA_SDQS5# DDRA_SDQS6 DDRA_SDQS6# DDRA_SDQS7 DDRA_SDQS7# DDRA_SDQ[63 0] DDRA_SDM[7 0] DDRA_SDQS0 DDRA_SDQS0# DDRA_SDQS1 DDRA_SDQS1# DDRA_SDQS2 DDRA_SDQS2# DDRA_SDQS3 DDRA_SDQS3# DDRA_SDQS4 DDRA_SDQS4# DDRA_SDQS5 DDRA_SDQS5# DDRA_SDQS6 DDRA_SDQS6# DDRA_SDQS7 DDRA_SDQS7# FOX_PZ63823-284S-41F_Champlian FOX_PZ63823-284S-41F_Champlian 4 2010/04/12 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/10/12 Deciphered Date Title AMD CPU S1G4 DDRIII I/F THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D PEW/76/86/96 LA-6552P Thursday, July 22, 2010 Sheet E of 45 Rev B B C FBMA-L11-201209-221LMA30T_0805 + C11 VDDA=0.25A 3300P_0402_50V7K 4.7U_0805_10V4Z C12 220U_6.3V_M LDT_RES# / MEMHOT# no support in S1g4 C13 2 +1.5V C14 0.22U_0603_16V4Z 1 R6 10K_0402_5% +2.5VS E Champlain: C1E C1E: LDT_REQ# no connect CLMC: LDT_REQ# connect to NB +2.5VDDA L1 D R7 1K_0402_5% B JCPU1D 2 A R10 169_0402_1% T2 R15 R16 +1.1VS LDT_RST# C17 0.01U_0402_25V4Z @ 2 VDD0_FB_H VDD0_FB_L VDDIO_FB_H VDDIO_FB_L W9 Y9 VDD1_FB_H VDD1_FB_L VDDNB_FB_H VDDNB_FB_L H6 G6 CPU_VDDNB_FB_H CPU_VDDNB_FB_L DBREQ_L E10 CPU_DBREQ# TDO AE9 CPU_TDO CPU_DBRDY CPU_TMS CPU_TCK CPU_TRST# CPU_TDI G10 AA9 AC9 AD9 AF9 CPU_TEST23 AD7 CPU_TEST18 CPU_TEST19 H10 G9 CPU_TEST25H CPU_TEST25L C18 0.01U_0402_25V4Z @ H_PWRGD C19 0.01U_0402_25V4Z @ R24 CPU_TEST21 CPU_TEST20 CPU_TEST24 CPU_TEST22 CPU_TEST12 CPU_TEST27 AB8 AF7 AE7 AE8 AC8 AF8 0_0402_5% C2 AA6 C21 @ U1 1 VDD THERMDA_CPU D+ THERMDC_CPU D- 100P_0402_50V8J THERM# EC_SMB_CK2 SDATA EC_SMB_DA2 ALERT# GND SCLK TEST23 TEST28_H TEST28_L TEST18 TEST19 TEST25_H TEST25_L TEST21 TEST20 TEST24 TEST22 TEST12 TEST27 TEST9 TEST6 Address 1001 100X b CPU internal thermal sensor C22 R41 0.1U_0402_16V4Z R42 31.6K_0402_1% FDV301N, the Vgs is: = 0.65V Typ = 0.85V Max = 1.5V For PVT G D7 E7 F7 C7 TEST7 TEST10 C3 K8 TEST8 C4 TEST29_H TEST29_L C9 C8 RSVD10 RSVD9 RSVD8 RSVD7 RSVD6 1.607V for Gate H_PROCHOT# R13 0_0402_5% H_PROCHOT_R# PROCHOT: Input: For HTC Function Output: Over Temperature Condition T4 T11 CPU_VDDNB_FB_H CPU_VDDNB_FB_L +1.5V CPU_SVC CPU_TEST17 CPU_TEST16 CPU_TEST15 CPU_TEST14 PAD PAD PAD PAD T5 T6 T7 T8 R19 R20 CPU_SVD 1K_0402_5% 1K_0402_5% +1.5V CPU_TEST29_H_FBCLKOUT_P CPU_TEST29_L_FBCLKOUT_N R25 CPU_TEST25H R22 R23 CPU_TEST25L R26 R27 80.6_0402_1% H18 H19 AA7 D5 C5 @ @ 510_0402_5% 510_0402_5% +1.5V 510_0402_5% 510_0402_5% +1.5V CPU_TEST27 R28 1K_0402_5% EC_SMB_CK2 For SCAN connect use EC_SMB_DA2 CPU_TEST12 CPU_TEST18 CPU_TEST19 +1.5V CPU_TEST20 CPU_TEST21 @ @ @ @ EC_SMB_DA2 CPU_TEST22 CPU_TEST24 CPU_TEST23 R29 R30 R31 R32 R33 R34 R35 R265 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% JP2 D S 11 13 15 17 19 21 23 Q2 MAINPWON @ 300_0402_5% J7 H8 CPU_DBREQ# CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO 1 TEST17 TEST16 TEST15 TEST14 R11 FOX_PZ63823-284S-41F_Champlian BSH111, the Vgs is: = 0.4V Typ = 1.0V Max = 1.3V 30K_0402_5% CPU_SID RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 ht ADM1032ARMZ_MSOP8 +3VS // m @ C20 @ DBRDY TMS TCK TRST_L TDI PAD PAD : 0.1U_0402_16V4Z E9 E8 A3 A5 B3 B5 C1 T3 CPU_VDD1_FB_H Y6 CPU_VDD1_FB_L AB6 +3VS THERMDC_CPU THERMDA_CPU CPU_VDD1_FB_H CPU_VDD1_FB_L yc R21 300_0402_5% HT_REF0 HT_REF1 W7 W8 F6 E6 LDT_STOP# R6 P6 THERMDC THERMDA CPU_VDD0_FB_H CPU_VDD0_FB_L R18 300_0402_5% +1.5VS LDT_STOP# SIC SID ALERT_L CPU_VDD0_FB_H CPU_VDD0_FB_L +1.5VS H_PWRGD 44.2_0402_1% CPU_HTREF0 44.2_0402_1% CPU_HTREF1 1 AF4 AF5 AE6 PAD 220_0402_5% R36 220_0402_5% R37 220_0402_5% R38 300_0402_5% R39 300_0402_5% R40 R17 300_0402_5% LDT_RST# 2 1K_0402_5% 1K_0402_5% 0_0402_5% CPU_THERMTRIP#_R H_PROCHOT# AF6 AC7 AA8 THERMTRIP_L PROCHOT_L MEMHOT_L H_THERMTRIP# R9 10 12 14 16 18 20 22 24 26 R43 @ 0_0402_5% +3VS +1.5VS 1 +1.5V U2 HDT_RST# A LDT_RST# SB_PWRGD NC7SZ08P5X_NL_SC70-5 G CONN@ SAMTEC_ASP-68200-07 B Y @ FDV301N_NL_SOT23-3 P R12 R14 CPU_SVC CPU_SVD G +1.5V +1.5V PAD CPU_SIC CPU_SID 0_0402_5% MMBT3904_NL_SOT23-3 CPU_SVC CPU_SVD 3900P_0402_50V7K RESET_L PWROK LDTSTOP_L LDTREQ_L A6 A4 1 R8 /x / SVC SVD su C15 B7 A7 F10 C6 VSS RSVD11 p CLK_CPU_BCLK# CLKIN_H CLKIN_L om LDT_RST# H_PWRGD LDT_STOP# VDDA1 VDDA2 A9 A8 C C16 CPU_CLKIN_SC_P CPU_CLKIN_SC_N 3900P_0402_50V7K CPU_THERMTRIP#_R M11 W18 Q1 E CLK_CPU_BCLK F8 F9 CPU_SIC EC_SMB_CK2 2010/04/12 Issued Date FDV301N_NL_SOT23-3 Compal Electronics, Inc Compal Secret Data Security Classification D S Q3 2010/10/12 Deciphered Date Title AMD CPU S1G4 CTRL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D PEW/76/86/96 LA-6552P Thursday, July 22, 2010 Sheet E of 45 Rev B A B C D E JCPU1F VDD(+CPU_CORE) decoupling JCPU1E +CPU_CORE +CPU_CORE 1 + + C23 + C24 1 + C25 + C27 @ 330U_D2_2V_Y C26 330U_D2_2V_Y 330U_D2_2V_Y 330U_D2_2V_Y 330U_D2_2V_Y Near CPU Socket Change as SGA19331D10 (ESR9 ohm) for PVT +CPU_CORE +CPU_CORE +CPU_CORE_NB C29 22U_0805_6.3V6M C30 22U_0805_6.3V6M C35 22U_0805_6.3V6M C31 22U_0805_6.3V6M 2 +CPU_CORE C33 22U_0805_6.3V6M 4A C34 22U_0805_6.3V6M +1.5V +CPU_CORE C36 0.22U_0603_16V4Z C37 0.01U_0402_25V4Z 1 C38 180P_0402_50V8J C39 0.22U_0603_16V4Z C40 0.01U_0402_25V4Z C41 180P_0402_50V8J Under CPU Socket VDDIO decoupling +CPU_CORE_NB C45 22U_0805_6.3V6M 1 C46 0.22U_0603_16V4Z 2 C47 0.22U_0603_16V4Z C48 C50 180P_0402_50V8J 180P_0402_50V8J 2 C42 22U_0805_6.3V6M Athlon 64 S1 Processor Socket +1.5V +CPU_VDDR : C56 + 220U_6.3V_M ht C67 0.1U_0402_16V7K C68 180P_0402_50V8J 2 C55 22U_0805_6.3V6M 2 2 @ +CPU_VDDR @ @ @ Reserve for EMI C69 180P_0402_50V8J C57 4.7U_0805_10V4Z C58 4.7U_0805_10V4Z +1.5V @ 0.1U_0402_16V7K C355 0.22U_0603_16V4Z @ Near Power Supply C96 C66 0.1U_0402_16V7K FOX_PZ63823-284S-41F_Champlian C101 0.1U_0402_16V7K C65 0.01U_0402_25V4Z C49 22U_0805_6.3V6M VDDR decoupling 180PF Qt'y follow the distance between CPU socket and DIMM0 0.1U_0402_16V7K C64 0.01U_0402_25V4Z 2 C354 0.22U_0603_16V4Z Athlon 64 S1 Processor Socket C100 0.1U_0402_16V7K +1.5V C54 0.22U_0603_16V4Z FOX_PZ63823-284S-41F_Champlian C99 +1.5V C53 0.22U_0603_16V4Z +1.5V TBD 0.1U_0402_16V7K C52 0.22U_0603_16V4Z Y25 V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18 0.1U_0402_16V7K C51 0.22U_0603_16V4Z C43 22U_0805_6.3V6M VDDIO27 VDDIO26 VDDIO25 VDDIO24 VDDIO23 VDDIO22 VDDIO21 VDDIO20 VDDIO19 VDDIO18 VDDIO17 VDDIO16 VDDIO15 VDDIO14 VDDIO13 J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 AC6 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 C98 +1.5V VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12 P8 P10 R4 R7 R9 R11 T2 T6 T8 T10 T12 T14 U7 U9 U11 U13 U15 V6 V8 V10 V12 V14 W4 Y2 AC4 AD2 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 C97 Between CPU Socket and DIMM H25 J17 K18 K21 K23 K25 L17 M18 M21 M23 M25 N17 VDD1_1 VDD1_2 VDD1_3 VDD1_4 VDD1_5 VDD1_6 VDD1_7 VDD1_8 VDD1_9 VDD1_10 VDD1_11 VDD1_12 VDD1_13 VDD1_14 VDD1_15 VDD1_16 VDD1_17 VDD1_18 VDD1_19 VDD1_20 VDD1_21 VDD1_22 VDD1_23 VDD1_24 VDD1_25 VDD1_26 36A decoupling // m Under CPU Socket 1 yc om +CPU_CORE_NB +1.5V C44 22U_0805_6.3V6M VDDNB_1 VDDNB_2 VDDNB_3 VDDNB_4 VDDNB_5 p K16 M16 P16 T16 V16 su C32 22U_0805_6.3V6M /x / C28 22U_0805_6.3V6M VDD0_1 VDD0_2 VDD0_3 VDD0_4 VDD0_5 VDD0_6 VDD0_7 VDD0_8 VDD0_9 VDD0_10 VDD0_11 VDD0_12 VDD0_13 VDD0_14 VDD0_15 VDD0_16 VDD0_17 VDD0_18 VDD0_19 VDD0_20 VDD0_21 VDD0_22 VDD0_23 1 G4 H2 J9 J11 J13 J15 K6 K10 K12 K14 L4 L7 L9 L11 L13 L15 M2 M6 M8 M10 N7 N9 N11 AA4 AA11 AA13 AA15 AA17 AA19 AB2 AB7 AB9 AB23 AB25 AC11 AC13 AC15 AC17 AC19 AC21 AD6 AD8 AD25 AE11 AE13 AE15 AE17 AE19 AE21 AE23 B4 B6 B8 B9 B11 B13 B15 B17 B19 B21 B23 B25 D6 D8 D9 D11 D13 D15 D17 D19 D21 D23 D25 E4 F2 F11 F13 F15 F17 F19 F21 F23 F25 H7 H9 H21 H23 J4 +CPU_CORE C59 0.22U_0603_16V4Z C60 0.22U_0603_16V4Z C61 1000P_0402_50V7K C62 1000P_0402_50V7K C63 180P_0402_50V8J C70 180P_0402_50V8J Near CPU Socket Right side Change as SGA19331D10 (ESR9 ohm) for PVT +CPU_VDDR 1 C71 4.7U_0805_10V4Z C72 4.7U_0805_10V4Z C73 4.7U_0805_10V4Z + C74 4.7U_0805_10V4Z C75 330U_D2_2V_Y C76 4.7U_0805_10V4Z C77 4.7U_0805_10V4Z C78 0.22U_0603_16V4Z C79 0.22U_0603_16V4Z C80 1000P_0402_50V7K C81 1000P_0402_50V7K C82 180P_0402_50V8J C83 180P_0402_50V8J 4 Near CPU Socket Left side 2010/04/12 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/10/12 Deciphered Date Title AMD CPU S1G4 PWR & GND THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D PEW/76/86/96 LA-6552P Thursday, July 22, 2010 Sheet E of 45 Rev B A B +VREF_DQ +1.5V C D E +1.5V JDIMM1 DDRA_SDQS2# DDRA_SDQS2 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ24 DDRA_SDQ25 DDRA_SDM3 DDRA_SDQ26 DDRA_SDQ27 DDRA_SDM[0 7] DDRA_SMA[0 15] DDRA_SDQ12 DDRA_SDQ13 DDRA_SMA[0 15] DDRA_SDM1 MEM_MA_RST# MEM_MA_RST# DDRA_SDQ14 DDRA_SDQ15 DDRA_SDQ20 DDRA_SDQ21 DDRA_SDM2 DDRA_SDQ22 DDRA_SDQ23 DDRA_SDQ28 DDRA_SDQ29 +VREF_CA +VREF_DQ DDRA_SDQS3# DDRA_SDQS3 DDRA_SDQ30 DDRA_SDQ31 DDRA_SWE# DDRA_SCAS# DDRA_SCS1# DDRA_SWE# DDRA_SCAS# DDRA_SMA13 DDRA_SCS1# DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQS4# DDRA_SDQS4 DDRA_SDQS4# DDRA_SDQS4 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ40 DDRA_SDQ41 DDRA_SDM5 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQS6# DDRA_SDQS6 DDRA_SDQS6# DDRA_SDQS6 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ56 DDRA_SDQ57 DDRA_SDM7 DDRA_SDQ58 DDRA_SDQ59 R50 10K_0402_5% +3VS R51 +3VS 10K_0402_5% C90 2.2U_0805_10V6K C91 DDRA_SMA2 DDRA_SMA0 DDRA_CLK1 DDRA_CLK1# DDRA_CLK1 DDRA_CLK1# DDRA_SBS1# DDRA_SRAS# DDRA_SBS1# DDRA_SRAS# DDRA_SCS0# DDRA_ODT0 DDRA_SCS0# DDRA_ODT0 DDRA_ODT1 DDRA_SDQ38 DDRA_SDQ39 DDRA_SDQ44 DDRA_SDQ45 1 C85 C10 R49 1K_0402_1% C235 @ 2 C351 C680 R315 1K_0402_1% +1.5V DDRA_SDQS5# DDRA_SDQS5 0.1U_0402_16V4Z 2 C87 0.1U_0402_16V4Z 2 C643 0.1U_0402_16V4Z C88 0.1U_0402_16V4Z 2 C644 0.1U_0402_16V4Z C640 C645 0.1U_0402_16V4Z 0.1U_0402_16V4Z C641 0.1U_0402_16V4Z C646 0.1U_0402_16V4Z C642 0.1U_0402_16V4Z C647 DDRA_SDQS5# DDRA_SDQS5 +0.75VS DDRA_SDQ46 DDRA_SDQ47 0.1U_0402_16V4Z 2 DDRA_SDQ52 DDRA_SDQ53 C665 0.1U_0402_16V4Z DDRA_SDM6 C664 1 C961 4.7U_0805_10V4Z Place near DIMM1 DDRA_SDQ54 DDRA_SDQ55 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQS7# DDRA_SDQS7 DDRA_SDQS7# DDRA_SDQS7 +1.5V DDRA_SDQ62 DDRA_SDQ63 +1.5V PAD C690 T9 SB_SMDAT0 SB_SMCLK0 @ +0.75VS +0.75VS C691 C692 C693 1 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.01U_0402_16V7K 0.01U_0402_16V7K FOX_AS0A626-U8SN-7F CONN@ 0.1U_0402_16V4Z DIMM_A STD H:8mm 2010/04/12 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/10/12 Deciphered Date Title DDRIII SO-DIMM THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A 1 2 DDRA_ODT1 +VREF_CA DDRA_SDM4 C84 @ 1000P_0402_50V7K su 206 DDRA_SMA6 DDRA_SMA4 DDRA_SDQ36 DDRA_SDQ37 0.01U_0402_25V7K G2 4.7U_0805_10V4Z G1 DDRA_SMA11 DDRA_SMA7 p 205 DDRA_CKE1 DDRA_SMA15 DDRA_SMA14 om DDRA_SBS0# DDRA_SMA10 DDRA_SBS0# DDRA_CKE1 yc DDRA_CLK0 DDRA_CLK0# DDRA_CLK0 DDRA_CLK0# 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 C89 1000P_0402_50V7K DDRA_SMA3 DDRA_SMA1 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 // m DDRA_SMA8 DDRA_SMA5 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 : DDRA_SMA12 DDRA_SMA9 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 ht DDRA_SBS2# DDRA_SBS2# +VREF_CA 0.01U_0402_25V7K DDRA_CKE0 DDRA_CKE0 R310 1K_0402_1% R48 1K_0402_1% +VREF_DQ +1.5V +1.5V DDRA_SDQS3# DDRA_SDQS3 DDRA_SDQS2# DDRA_SDQS2 DDRA_SDQ[0 63] DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQ[0 63] DDRA_SDM[0 7] DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQS0# DDRA_SDQS0 DDRA_SDQ6 DDRA_SDQ7 DDRA_SDQS1# DDRA_SDQS1 DDRA_SDQS1# DDRA_SDQS1 DDRA_SDQS0# DDRA_SDQS0 1000P_0402_50V7K DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQ4 DDRA_SDQ5 4.7U_0805_10V4Z 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 DDRA_SDQ2 DDRA_SDQ3 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 DDRA_SDM0 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 /x / 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 DDRA_SDQ0 DDRA_SDQ1 B C D PEW/76/86/96 LA-6552P Sheet Thursday, July 22, 2010 E 10 of 45 Rev B A B GAIN0 GAIN1 AV(inv) 6dB 0 10dB 1 15.6dB 1 21.6dB Ri 90k 70k 45k 25k C D E +5VAMP 0.1U_0402_16V4Z C959 10U_0805_10V4Z Int Speaker Conn C960 2 +5VAMP 16 15 0.47U_0603_10V7K R828 AMP_C_LEFT 0_0603_5% EC_MUTE# 19 SPKL+ LOUT- SPKL- LIN- @ R825 100K_0402_5% NC 12 10 SHUTDOWN JSPK1 SPKR+ SPKR- Keep 10 mil width GND5 GND1 GND2 GND3 GND4 C956 0.47U_0603_10V7K 21 20 13 11 1 R831 R832 0_0603_5% 0_0603_5% SPK_R+ SPK_R- 2 D41 G1 G2 PJDLC05C_SOT23-3 Right ACES_88266-02001 CONN@ yc om TPA6017A2_TSSOP20 C779 330P_0402_50V7K HP_LEFT R686 56.2_0603_1% HPOUT_L_1 HP_RIGHT R685 56.2_0603_1% HPOUT_R_1 L94 L93 2 C774 Headphone Out 330P_0402_50V7K JHP1 HPOUT_L_2 FBMA-L11-160808-700LMT_2P HPOUT_R_2 FBMA-L11-160808-700LMT_2P // m HP_PLUG# HP_PLUG# SINGA_2SJ-0960-C01 CONN@ MIC_PLUG# : HP_PLUG# MIC1_R R695 MIC1_L_1 1K_0603_1% MIC1_R_1 1K_0603_1% 2 4.7K_0402_5% MIC1_R_R C780 220P_0402_50V7K JMIC1 MIC1_L_R L89 FBMA-L11-160808-700LMT_2P L90 FBMA-L11-160808-700LMT_2P 3 R694 MIC JACK R693 R692 4.7K_0402_5% MIC1_L @ D24 PJDLC05C_SOT23-3 D42 CH751H-40PT_SOD323-2 1 D43 CH751H-40PT_SOD323-2 2 ht MIC1_VREFO MIC1_VREFO 1 R826 100K_0402_5% 20mil BYPASS Left G1 G2 LOUT+ ROUT- SPKR- SPKR+ 18 14 ROUT+ LIN+ EC_MUTE# GAIN1 ACES_88266-02001 CONN@ C971 0.47U_0603_10V7K GAIN1 AMP_LEFT RIN- /x / C955 AMP_C_RIGHT 17 0_0603_5% GAIN0 GAIN0 su R830 PJDLC05C_SOT23-3 2 p 0.47U_0603_10V7K RIN+ D39 C957 SPK_L+ SPK_L- 1 AMP_RIGHT 0.47U_0603_10V7K 0_0603_5% 0_0603_5% @ R829 100K_0402_5% C958 R834 R833 20mil R827 100K_0402_5% VDD PVDD1 PVDD2 U83 JSPK2 SPKL+ SPKL- 10 dB 1 C781 220P_0402_50V7K @ D29 MIC_PLUG# MIC_PLUG# PJDLC05C_SOT23-3 4 SINGA_2SJ-A960-C01 CONN@ 2010/04/12 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/10/12 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Amplifier & Audio Jack Document Number PEW/76/86/96 LA-6552P Thursday, July 22, 2010 Sheet E 31 of 45 Rev B ON/OFF switch FAN1 Conn R494 @ 10K_0603_5% R495 100K_0402_5% Bottom Side U35 C823 10U_0805_10V4Z ON/OFF C825 1000P_0402_50V7K G1 G2 CONN@ ACES_85204-03001 Q27 10K_0402_5% 2010/04/12 H23 H_4P2 H17 H_3P0X3P5N H22 H_4P2 1 H10 H_3P0 1 H21 H_4P2 H20 H_4P2 H13 H_3P0N FD4 FD3 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 Compal Electronics, Inc Compal Secret Data Security Classification H8 H_3P0 1 : ht FD2 H7 H_3P0 H24 H_3P0 H18 H_3P4 FD1 Issued Date H19 H_3P0 // m H11 H_3P0 H5 H_3P0 1 H4 H_3P0 yc om p S 2N7002_SOT23 1 D G R496 su FAN_SPEED1 1000P_0402_50V7K EC_ON EC_ON JFAN1 C773 R568 10K_0402_5% +VCC_FAN1 Change to SC600000B00 ON/OFFBTN# C824 1000P_0402_50V7K 40mil 51ON# DAN202UT106_SC70-3 +3VS APL5607KI-TRG_SO8 0.01U_0402_25V4Z ON/OFFBTN# C822 @ GND GND GND GND /x / 0_0402_5% EN VIN VOUT VSET D12 1 @ SW3 SMT1-05-A_4P @ D26 BAS16_SOT23-3 2 D25 1SS355_SOD323-2 @ +VCC_FAN1 R567 @ 10K_0603_5% 10U_0805_10V4Z 2 R493 R566 0_0603_5% @ EN_DFAN1 +3VALW TOP Side +5VS +5VS C821 Power Button Deciphered Date 2010/10/12 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: FAN & Screw Hole & PBTN Document Number PEW/76/86/96 LA-6552P Thursday, July 22, 2010 Sheet 32 of 45 Rev B A B C +5VALW TO +5VS E +5VALW +1.1VALW TO +1.1VS +5VS +1.1VALW +5VALW D +1.1VS R570 100K_0402_5% U36 Q48 @ 2N7002_SOT23 D G Q34 S 2N7002_SOT23 D S // m ACIN G VLDT_EN C835 S D S Q40 2N7002_SOT23 G R584 10K_0402_5% 0.1U_0603_25V7K Q49 @ 2N7002_SOT23 +5VALW R587 100K_0402_5% VGA_ON# VGA_ON D S Q42 2N7002_SOT23 G R586 10K_0402_5% +5VS D VLDT_EN# G Q69 2N7002_SOT23 VLDT_EN# R605 470_0603_5% D VGA_ON# G Q46 2N7002_SOT23 S S VGA_ON# G Q32 2N7002_SOT23 2 ht 1 D VLDT_EN# G Q56 2N7002_SOT23 S +1.5V R592 470_0603_5% S S R610 470_0603_5% D SUSP G 2N7002_SOT23 Q45 +1.8VS 1 R604 470_0603_5% 1 D SUSP G Q44 2N7002_SOT23 D R591 470_0603_5% +NB_CORE 2 2 1 R590 470_0603_5% S +CPU_VDDR D : R583 100K_0402_5% C848 0.22U_0603_16V4Z2 @ 470_0603_5% yc R503 47K_0402_5% +5VALW R572 1 VGA_ON# +0.75VS 2 10U_0805_10V4Z 1.5VSG_GATE 100K_0402_5% R575 C833 10U_0805_10V4Z Q35 2N7002_SOT23 R580 10K_0402_5% su 0.1U_0603_25V7K 10U_0805_10V4Z 2 1U_0402_6.3V4Z p C843 +VSB +2.5VS C832 SI4800BDY_SO8 om 2 S S S G S D D D D R596 C831 S 1 D G U37 SUSP G Q36 2N7002_SOT23 C830 D +1.5VS +1.5V D S SUSP Q38G 2N7002_SOT23 +1.5V to +1.5VS R579 470_0603_5% 3VS_GATE 200K_0402_5% 510K_0402_5% 10U_0805_10V4Z 2 10U_0805_10V4Z R582 C836 10U_0805_10V4Z 2 1U_0402_6.3V4Z C842 SI4800BDY_SO8 +VSB /x / 2 1 C841 S S S G SUSP SUSP SUSP# 1 C840 D D D D R576 100K_0402_5% U39 0.1U_0603_25V7K S ACIN G ACIN +3VALW +5VALW C844 D 1 @ S S Q30 2N7002_SOT23 R573 100K_0402_5% VLDT_EN# G Q37 2N7002_SOT23 D G VLDT_EN# Q39G 2N7002_SOT23 SYSON S R595 D 510K_0402_5% 0.1U_0603_25V7K +3VALW TO +3VS +3VS 1.1VS_GATE 47K_0402_5% 2 R581 S +VSB SYSON# SYSON# 470_0603_5% D C834 1 10U_0805_10V4Z D SUSP G Q31 2N7002_SOT23 R578 SUSP Q33G 2N7002_SOT23 S 1 5VS_GATE 100K_0402_5% R574 C839 10U_0805_10V4Z 2 1U_0402_6.3V4Z C838 SI4800BDY_SO8 D R577 C837 1K_0402_5% R571 470_0603_5% 10U_0805_10V4Z 2 10U_0805_10V4Z S S S G 1 C829 10U_0805_10V4Z 2 1U_0402_6.3V4Z D D D D C827 SI4800BDY_SO8 +VSB U38 S S S G C828 D D D D 1 C826 SYSON# G Q57 2N7002_SOT23 C972 C973 1 C974 C975 C976 C977 C978 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 4 2010/04/12 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/10/12 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D DC Interface Document Number PEW/76/86/96 LA-6552P Thursday, July 22, 2010 Sheet E 33 of 45 Rev B A B C D 1 DC-IN cable: DC301009W00 (Yellow) VIN SP02000GC00 ACES_50305-00441-001 PC5 100P_0402_50V8J PC6 1000P_0402_50V7K su /x / PC4 100P_0402_50V8J PC3 1000P_0402_50V7K 2 PJP1 PL1 SMB3025500YA_2P DC_IN_S1 1 GND GND yc om p 2 // m VIN 51ON# +3VALW +1.8VSP 1 2 +1.8VS (3A,120mils ,Via NO.=6) PJ26 +5VALW +1.1VALWP 1 2 +1.1VALW JUMP_43X118 JUMP_43X118 (5A,200mils ,Via NO.= 10) (7A,280mils ,Via NO.=14) PJ11 PJ5 +VSBP JUMP_43X118 2 +VSB +0.75VSP 1 2 +0.75VS JUMP_43X118 JUMP_43X39 (3A,120mils ,Via NO.=6) (120mA,40mils ,Via NO.= 2) PJ6 PJ8 VS +NB_COREP +1.5VP +NB_CORE 1 +1.5V JUMP_43X118 JUMP_43X118 2 PR14 22K_0402_1% PC13 0.22U_0603_25V7K PR13 100K_0402_1% 1 PJ22 PJ3 +5VALWP ht BATT+ PQ1 TP0610K-T1-E3_SOT23-3 N1 (3.9A,160mils ,Via NO.= 8) PR11 68_1206_5% PD3 RLS4148_LL34-2 : PR10 68_1206_5% JUMP_43X118 1 PD2 RLS4148_LL34-2 PJ1 +3VALWP PJ19 PC14 0.1U_0603_25V7K 1 2 JUMP_43X118 (7.09A,300mils ,Via NO.=16) (8.1A,320mils ,Via NO.=17) PJ9 +2.5VSP 1 2 +2.5VS +CPU_VDDR JUMP_43X39 +3VLP PJ21 +CHGRTC +CPU_VDDRP PR16 0_0603_5% 1 JUMP_43X39 (1.5A,40mils ,Via NO.= 3) 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/04/12 Deciphered Date 2010/10/12 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C DCIN & DETECTOR Rev B PEW96 LA-6552P Sheet Thursday, July 22, 2010 D 34 of 45 A B C D PH1 under CPU botten side : Not SPEC, reference only! CPU thermal protection at 92 degree C Recovery at 56 degree C VL PR32 100_0402_1% OT1 TMSNS2 OT2 RHYST2 @PR169 @ PR169 47K_0402_1% G718TM1U_SOT23-8 PR261 1K_0402_5% su PH2 @ 100K_0402_1%_NCP15WF104F03RC yc om p BATT_TEMP 100K_0402_1%_NCP15WF104F03RC PR33 1K_0402_1% PH1 +3VALWP PC26 0.1U_0402_10V7K /x / MAINPWON PR24 6.49K_0402_1% 1 2 1 EC_SMB_CK1 PC19 0.01U_0402_25V7K GND RHYST1 PC20 1000P_0402_50V7K VCC TMSNS1 @PR21 @ PR21 100K_0402_1% PR30 9.53K_0402_1% 2 BATT+ 1 PL2 SMB3025500YA_2P BATT_S1 EC_SMB_DA1 PC22 1U_0402_6.3V6K CONN@ PU3 PJP2 SUYIN_200275GR008G13GZR PR28 21K_0402_1% PR27 10K_0402_1% VMB PC21 0.1U_0402_10V7K PR29 100_0402_1% 2 EC_SMCA TH PI VL EC_SMDA 10 1 GND GND 1 2 PR36 22K_0402_1% PR39 1K_0402_5% D S PQ4 2N7002W-T/R7_SOT323-3 G // m 1U_0402_6.3V6K 1 SPOK PR38 100K_0402_1% PC25 0.1U_0603_25V7K : 2 VL +VSBP ht PR34 100K_0402_1% 1 B+ PC24 0.22U_0603_25V7K PQ3 TP0610K-T1-E3_SOT23-3 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/04/12 Deciphered Date 2010/10/12 Title BATTERY CONN / OTP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C Rev B PEW96 LA-6552P Sheet Thursday, July 22, 2010 D 35 of 45 Note: Use TPS51125 IC can remove RTC refernece LDO Use TPS51427 IC must keep RTC refernece LDO PC344 1U_0603_10V6K 2VREF_8205 RT8205_B+ PL36 FBMA-L11-322513-151LMA50T_1210 PR267 20K_0402_1% G MAINPWON PC23 1U_0402_6.3V6K PC363 2.2U_0603_10V7K S PR278 40.2K_0402_1% D G PQ64 PDTC115EU_SOT323 PR288 200K_0402_1% 20 LX_5V LGATE2 LGATE1 19 LG_5V 2 PQ62 AO4712_SO8 RT8205_B+ 2VREF_8205 PC360 4.7U_0805_10V6K VL Typ: 175mA +5VALWP PC356 220U_6.3V_M PC358 680P_0402_50V7K RT8205EGQW_WQFN24_4X4 PR273 4.7_1206_5% PL35 10UH_MSCDRI-104A-100M-E_4.6A_20% 18 NC VREG5 VIN 16 15 GND om SKIPSEL C PHASE1 13 PC350 2200P_0402_50V7K su p PC349 10U_1206_25V6M /x / ENTRIP1 ENTRIP1 FB1 REF ENTRIP2 UG_5V PHASE2 PC359 1U_0603_10V6K 1 FB2 22 21 S 1 PR276 100K_0402_1% PR277 100K_0402_1% PQ63B DMN66D0LDW-7_SOT363-6 PQ60 AO4466_SO8 SPOK BOOT1 ht PR279 0_0402_5% D 23 VFB=2.0V PC361 0.1U_0603_25V7K S VL : B PR275 100K_0402_1% ENTRIP2 PGOOD UGATE1 // m B+ VO1 24 UGATE2 BOOT2 EN PC357 680P_0402_50V7K PR274 499K_0402_1% D 12 RT8205_B+ PR269 154K_0402_1% PR271 PC354 2.2_0603_5% 0.1U_0603_25V7K BST_5V 2 yc G VREG3 14 LG_3V PQ61 AO4468_SO8 ENTRIP1 PQ63A DMN66D0LDW-7_SOT363-6 VO2 2 BST_3V 2.2_0603_5% UG_3V 10 PC353 0.1U_0603_25V7K LX_3V 11 + 17 PR270 PC355 220U_6.3V_M P PAD TONSEL 25 PR272 4.7_1206_5% 2 ENTRIP2 PC352 4.7U_0805_10V6K PU19 PC347 10U_1206_25V6M PQ59 AO4466_SO8 +3VALWP 1 PR266 20K_0402_1% PR268 137K_0402_1% PL34 4.7UH_SIL104R-4R7PF_5.7A_30% ACPRN PR265 30.9K_0402_1% +3VLP C VS PR264 13K_0402_1% Typ: 175mA PC348 2200P_0402_50V7K 1 PC351 1000P_0402_50V7K PC362 0.1U_0402_25V6 B+ D D + RT8205 TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP) (2)SMPS2=375KHZ(+3VALWP) B TPS51125A TONSEL=VREF (1)SMPS1=245KHZ (+5VALWP) (2)SMPS2=305KHZ(+3VALWP) 3.3VALWP Delta I = 1.902A (Freq=305KHz) Iocp = 6.1232A ~ 8.3291A 5VALWP Delta I = 3.199A (Freq=245KHz) Iocp = 8.74A ~ 10.16A +3.3VALWP Ipeak=5.629A ; Imax=3.940A Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) Vlimit=(10E-06 * 133K)/10=133mV Ilimit=133mV/(22m*1.2) ~ 133mV/(17.4m*1.2) =6.157A ~ 7.389A Iocp=Ilimit+Delta I/2 =6.931A ~ 8.162A Delta I=1.547A (Freq=375KHz) +5VALWP Ipeak=5.875A ; Imax=4.113A Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) Vlimit=(10E-06 * 154K)/10=154mV Ilimit=154mV/(18m*1.2) ~ 154mV/(15m*1.2) =7.14A ~ 8.56A Iocp=Ilimit+Delta I/2 =8.44A ~ 9.86A Delta I=2.613A (Freq=300KHz) PQ65 2N7002W-T/R7_SOT323-3 A EC_ON A PQ66 PDTC115EU_SOT323 2010/04/12 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2010/10/12 Title +5VALWP/+3VALWP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev B PEW96 LA-6552P Sheet Thursday, July 22, 2010 36 of 45 A B C D Iada=0~3.42A(65W/19V=3.421A) 1 PQ54 2N7002W-T/R7_SOT323-3 65W/90W# G D S ACLIM VDDP 15 11 VADJ LGATE 14 GND PGND PR283 VIN1 100K_0402_1% PC52 0.1U_0603_25V7K 1 26251VDD 1 BATT+ PR86 4.7_0603_5% PC64 4.7U_0805_6.3V6K ISL6251AHAZ-T_QSOP24 PR88 15.4K_0402_1% CP mode Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) where Vaclm=1.464V (90W), Iinput=4.03A PR84=12.1K;PR87=20K where Vaclm=0.391(65W), Iinput=2.91A PR84=12.1K;PR85=2.55K 13 6251VDD PR284 10K_0402_1% PR90 31.6K_0402_1% 1 CALIBRATE# PD12 RB751V-40TE17_SOD323-2 6251VDDP DL_CHG PQ57 AO4468_SO8 PC59 0.1U_0603_25V7K BST_CHGA 2 PC63 10U_1206_25V6M 16 CHLIM S PC68 10U_1206_25V6M BOOT 10 DH_CHG PR82 2.2_0603_5% BST_CHG 2 PQ24 2N7002W-T/R7_SOT323-3 PR80 4.7_1206_5% 17 D ACPRN G UGATE PACIN G @ PQ23 2N7002W-T/R7_SOT323-3 VREF 18 S @ PL5 PR78 10UH_PCMB104T-100MS_6A_20% 0.02_1206_1% CHG1 PHASE D PC128 680P_0402_50V7K ICM @PR67 @ PR67 200K_0402_1% VIN PQ55 AO4466_SO8 CSIP VCOMP 20 19 CSOP CSIN /x / ICOMP su 2 21 CSON PC53 0.047U_0603_16V7K PR73 20_0402_5% PR74 PC129 20_0402_5% 0.1U_0603_25V7K PR76 2_0402_5% LX_CHG : CP= 85%*Iada; CP=2.91A CSOP 12 ht Iada=0~3.42A(65W) CELLS // m 12.1K_0402_1% 1 6251aclim PR87 20K_0402_1% CP= 85%*Iada; CP=4.03A PR84 3 Iada=0~4.74A(90W) 22 @ PD17 BAS40CW_SOT323-3 ACOFF 2 PC57 2200P_0402_50V7K 2 1 0.1U_0402_16V7K 6251VREF 2 6251VREF PR83 100K_0402_1% PR77 100_0402_1% PC58 ACIN PR286 10K_0402_1% PR285 47K_0402_1% 1 PACIN PR287 14.3K_0402_1% CC=0.6~4.48A IREF=1.016*Icharge ACPRN PQ67 PDTC115EU_SOT323 PR81 80.6K_0402_1% 2 PC60 0.01U_0402_25V7K ACOFF PC55 0.01U_0402_25V7K ADP_I IREF CSON p S PR85 2.55K_0402_1% ACOFF PC54 6800P_0402_25V7K PR75 10K_0402_1% 2 PQ53 PDTC115EU_SOT323 EN VIN PR65 10K_0402_1% PQ20 PDTC115EU_SOT323 PR72 20_0402_5% 1 PR79 47K_0402_5% PACIN ACPRN PQ68B DMN66D0LDW-7_SOT363-6 S 23 D G ACSET ACPRN 3 PQ68A DMN66D0LDW-7_SOT363-6 G PR63 47K_0402_1% PR282 14.3K_0402_1% PC127 0.1U_0603_25V7K DCIN 2 3S/4S# D 24 6251_EN DCIN PQ35 PDTC115EU_SOT323 VDD PC364 1000P_0402_50V7K 1 PR69 150K_0402_1% 2 PR71 100K_0402_1% 1 ACSETIN PR281 10_1206_5% PU5 PR70 47K_0402_5% PR280 191K_0402_1% PD16 RB751V-40_SOD323-2 ACSETIN PR68 0_0402_5% FSTCHG 6251VDD PreCHG PC61 2200P_0402_50V7K VIN PC48 0.1U_0603_25V7K CSIP 47K PQ21 PDTC115EU_SOT323 CSIN om PR94 200K_0402_1% PQ16 AO4435L_SO8 PC51 10U_1206_25V6M PC49 2.2U_0603_6.3V6K 1 2 CHG_B+ PL37 FBMA-L11-322513-151LMA50T_1210 6251VDD VIN1 PQ19 PDTA144EU_SOT323-3 47K PC62 0.1U_0603_25V7K 1 PR62 200K_0402_1% PC50 10U_1206_25V6M 1 B+ PR61 0.02_2512_1% P3 PQ15 AO4407A_SO8 B+ yc P2 PQ14 AO4435L_SO8 VIN CP = 85%*Iada ; CP = 2.91A CP = 85%*Iada ; CP = 4.07A ADP_I = 19.9*Iadapter*Rsense PC56 5600P_0402_25V7K Iada=0~4.74A(90W/19V=4.736A) IREF=0.43V~3.24V 4 BATT Type Charging Voltage (0x15) CV mode 12600mV 12.60V Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Normal 3S LI-ON Cells 2010/04/12 Deciphered Date 2010/10/12 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC - Date: A B C CHARGER Rev B Sheet Thursday, July 22, 2010 D 37 of 45 A B C D PR96 255K_0402_1% 14 11 VDDP 10 LGATE DL_1.1VALW PR103 4.7K_0402_1% 2 p om PL32 FBMA-L11-322513-151LMA50T_1210 11 VDDP 10 PR112 18.2K_0402_1% DL_1.5V LGATE +5VALW PQ28 AO4712_SO8 S IC G5603RU1U TQFN 14P PWM Cout ESR=17 mohm Rdson(max)=18 mohm Rdson(typ)=15 mohm Ipeak=7A, Imax=8.4A, Iocp=13.2A Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=3.9A =>1/2Delta I=1.95A Vtripmax=Iocp*Rdson=16.2*5.6*1.3=0.118V Rcs=Vtrip/9uA=0.118V/9uA=13.1K choose Rcs=13K Iocpmax=((13K*11uA)/0.0045)+1.95A=32A Iocpmin=((13K*9uA)/(0.0056*1.3))+1.95A=18A Iocp=9.94A~13.2A +1.5VP 12 CS PR110 4.7_1206_5% + PC86 330U_6.3V_M PC88 680P_0603_50V7K PC90 4.7U_0805_10V6K PR113 10K_0402_1% PR114 10K_0402_1% VFB=0.75V Vo=0.75*(1+10K/10K)=1.5V Fsw=335KHz PHASE LX_1.5V 14 15 BOOT DH_1.5V PGOOD PGND FB 13 PL7 1.8UH_1164AY-1R8N=P3_9.5A_30% 2 VDD PC84 0.1U_0603_25V7K BST_1.5V-1 VOUT 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/04/12 Deciphered Date 2010/10/12 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B+ NC EN/DEM PR108 2.2_0603_5% BST_1.5V PQ27 AO4466_SO8 UGATE PC87 4.7U_0603_6.3V6K ht +5VALW TON GND PU7 PR111 100_0603_1% @PC85 @PC85 0.1U_0402_16V7K @PR109 @ PR109 30K_0402_5% : 1 PR105 0_0402_5% 2 PR106 226K_0402_1% 2 PC83 2200P_0402_50V7K // m yc 1.5V_B+ PC82 10U_1206_25V6M PR104 8.45K_0402_1% Cout ESR=15m ohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm Ipeak=7.42A, Imax=5.2A, Iocp=8.9A Delta I=((19-1.1)*(1.1/19))/(L*Fsw)=2.06A =>1/2Delta I=1.03A Vtripmax=Iocp*Rdson=8.9*5.6*1.3=0.065V Rcs=Vtrip/9uA=0.065V/9uA=7.2K choose Rcs=7.32K Iocpmax=((7.32K*11uA)/0.0045)+1.03A=19A Iocpmin=((7.32K*9uA)/(0.0056*1.3))+1.03A=10A Iocp=10A~19A PC78 680P_0603_50V7K 2 PC80 4.7U_0805_10V6K + PC76 330U_6.3V_M su S IC G5603RU1U TQFN 14P PWM PQ26 AO4456_SO8 PGND VFB=0.75V V=0.75*(1+4.7K/10K)=1.1V Fsw=280KHz PGOOD GND PC77 4.7U_0603_6.3V6K PR100 4.7_1206_5% +5VALW PR102 7.32K_0402_1% +1.1VALWP LX_1.1VALW 12 CS FB PHASE VDD 0.1U_0603_25V7K VOUT DH_1.1VALW 13 UGATE TON BOOT NC EN/DEM PL6 1.0UH_PCMC104T-1R0MN_20A_20% PC75 BST_1.1VALW-11 /x / PR101 100_0603_1% 15 PU6 2 @ PC74 @PC74 0.1U_0402_16V7K SYSON DCR= 7.5 mohm @ PR99 30K_0402_5% +5VALW PQ25 AO4466_SO8 PR98 2.2_0603_5% BST_1.1VALW SPOK B+ PR97 0_0402_5% 2 PL31 FBMA-L11-322513-151LMA50T_1210 PC72 10U_1206_25V6M PC139 2200P_0402_50V7K 1.1VALW_B+ B C 1.1VALWP/1.5VP Rev B PEW96 LA-6552P Sheet Thursday, July 22, 2010 D 38 of 45 A B C D PL33 FBMA-L11-322513-151LMA50T_1210 PR115 255K_0402_1% 14 su PGND +CPU_VDDRP PU16 APL5508-25DC-TRL_SOT89-3 OUT 1.05V PC114 1U_0402_6.3V6K +2.5VSP 1 LOW D GND IN VDDR_SW 0.9V PQ58 2N7002W-T/R7_SOT323-3 S @ PR153 @PR153 150_1206_5% 2 +3VS PR156 249K_0402_1% HIGH PC218 100U_25V_M 1 PC126 0.01U_0402_25V7K PR161 165K_0402_1% POWER_SEL 2 PC118 0.01U_0402_25V7K 1 2 1 PR154 31.6K_0402_1% G 1.1V PC113 4.7U_0805_6.3V6K VDDR_SW S PQ43 PR157 2N7002W-T/R7_SOT323-3 0_0402_5% 2 G PC119 22U_0805_6.3V6M 0.95V // m VIN APL5915KAI-TRL_SO8 @ PR152 @PR152 10K_0402_1% D 2 +5VALW HIGH LOW PR159 10K_0402_5% PC125 0.1U_0402_25V6 POWER_SEL PR131 10K_0402_1% ht FB VOUT PC97 680P_0603_50V7K PC99 4.7U_0805_10V6K PC116 4.7U_0805_6.3V6K PR188 @ 47K_0402_5% EN 1 : 1 PC121 0.1U_0402_16V7K 10K_0402_1% VIN VOUT @PR155 @ PR155 VLDT_EN POK PU12 VCNTL 10K_0402_1% GND VR_ON PC115 1U_0402_6.3V6K PR162 G S PR123 8.87K_0402_1% PJ24 @ JUMP_43X79 + PC95 330U_6.3V_M p D PQ44 2N7002W-T/R7_SOT323-3 PQ30 AO4456_SO8 +5VALW 1 yc PR158 11.8K_0402_1% +5VALW DL_NB_CORE S IC G5603RU1U TQFN 14P PWM om PR122 2.37K_0402_1% +1.5V LGATE Cout ESR=15m ohm Rdson(max)=18m Rdson(typ)=15m Ipeak=7.6A, Imax=5.4A, Iocp=9.2A Delta I=((19-1.1)*(1.1/19))/(L*Fsw)=2.06A =>1/2Delta I=1.03A Vtripmax=Iocp*Rdson=9.2*5.6*1.3=0.067V Rcs=Vtrip/9uA=0.067V/9uA=7.44K choose Rcs=7.5K Iocpmax=((7.5K*11uA)/0.0045)+1.03A=19.36A Iocpmin=((7.5K*9uA)/(0.018*1.3))+1.03A=10.3A Iocp=10.3A~19.36A PR121 7.5K_0402_1% +NB_COREP EN/DEM PGOOD GND PC96 4.7U_0603_6.3V6K VFB=0.75V V=0.75*(1+4.7K/10K)=1.1V Fsw=280KHz PR119 4.7_1206_5% +5VALW 1 VDDP BOOT 11 10 FB 12 CS LX_NB_CORE PHASE DH_NB_CORE 0.1U_0603_25V7K VDD 13 /x / VOUT NC UGATE FB1_NB_COREP TON PL8 1.0UH_PCMC104T-1R0MN_20A_20% PC93 BST_NB_CORE-1 2 PR120 100_0603_1% 15 PU8 PC94 0.1U_0402_16V7K 2 + DCR= 7.5 mohm @PR118 @ PR118 30K_0402_5% +5VALW 1 PQ29 AO4466_SO8 VLDT_EN PR117 2.2_0603_5% BST_NB_CORE B+ PR116 100K_0402_5% PC91 10U_1206_25V6M 1 PC140 2200P_0402_50V7K NB_CORE_B+ PR160 10K_0402_1% 2010/04/12 Deciphered Date 2010/10/12 Title NB_CORE/2.5VS/CPU_VDDRP Issued Date Compal Electronics, Inc Compal Secret Data Security Classification THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C Rev B PEW96 LA-6552P Sheet Thursday, July 22, 2010 D 39 of 45 PreCHG +1.5V VREF VCNTL VOUT NC TP +3VALW PC101 1U_0603_6.3V6M PR128 100K_0402_5% 2 PR130 1K_0402_1% D PR127 1K_1206_5% 2 PR129 100K_0402_5% 1 PR132 100K_0402_5% PQ33 DTC115EUA_SC70-3 PD18 +5VALWP Change 300K / 0.22u delay PQ34 DTC115EUA_SC70-3 BAS40CW_SOT323-3 su Ipeak=1A, Imax=0.7A ACOFF PC103 22U_0805_6.3V6M /x / S 2N7002W-T/R7_SOT323-3 +0.75VSP PR134 1K_0402_1% PC102 0.1U_0402_16V7K 1 D PC104 0.22U_0402_10V4Z PQ32 G PR133 300K_0402_5% SUSP UP7711U8 PSOP 8P NC B+ LL4148_LL34-2 NC GND VIN 2 PR126 1K_1206_5% PU9 PC100 4.7U_0805_6.3V6K PD13 1 PJ17 JUMP_43X79 D PQ31 TP0610K-T1-E3_SOT23-3 PR125 1K_1206_5% VIN PR124 1K_1206_5% C // m yc om p C B ht : B A A Compal Electronics, Inc Compal Secret Data Security Classification 2010/04/12 Issued Date Deciphered Date 2010/10/12 Title Precharge/+0.75VSP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Thursday, July 22, 2010 Rev B PEW96 LA-6552P Sheet 40 of 45 FB=0.6V Note:Iload(max)=3.5A D D /x / PR145 4.99K_0402_1% su 2 SY8033BDBC_DFN10_3X3 @ PC155 680P_0603_50V7K PC1026 0.1U_0402_10V7K PC156 0.22U_0603_25V7K PC124 22U_0805_6.3VAM NC NC TP FB_1.8V 1.8V_EN PR147 10K_0402_1% FB +1.8VSP PC117 22U_0805_6.3VAM PL9 2.2UH_MSCDRI-74A-2R2M-E_6.5A_20% PC1022 68P_0402_50V8J LX LX_1.8V EN 2 SVIN LX PG PVIN PR144 200K_0402_1% 11 VGA_ON PVIN PR143 4.7_1206_5% VGA_ON 10 PC157 22U_0805_6.3VAM PU11 +3VALW C // m yc om p C B ht : B A A 2010/04/12 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2010/10/12 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: +1.8VSP Rev B PEW96 LA-6552P Sheet Thursday, July 22, 2010 41 of 45 E F G 25 VSEN1 +CPU_CORE PC198 2200P_0402_50V7K PC197 0.01U_0402_25V7K PC223 4.7U_0805_25V6-K PC196 4.7U_0805_25V6-K /x / 2 2 UGATE1 +CPU_CORE_0 Design Current: 25A Max current: 35A OCP_min:42A PHASE1 PR243 2.2_0603_5% BOOT1 PL18 0.36UH_PCMC104T-R36MN1R17_30A_20% PR247 16.2K_0402_1% PC207 0.1U_0603_25V7K +CPU_CORE PR248 4.7_1206_5% PQ49 AON6704L_DFN8-5 4 @ PQ52 PR251 10_0402_5% DIFF_1 su p TP PQ51 AON6428L 1N DFN-8 49 ISN1 24 // m ISP1 ISP1 23 VW1 22 FB1 21 20 CPU_B+ BOOT1 CPU_VDD1_FB_H ht @ PR252 1K_0402_1% UGATE1 : 10_0402_5% RTN1 PR246 10K_0402_1% 19 14 0_0402_5% PR240 ISP0 26 BOOT1 PC201 LGATE0 AON6704L_DFN8-5 UGATE1 VW0 PC202 1U_0603_16V6K PC206 2200P_0402_50V7K COMP0 12 ISN1 11 COMP1 PHASE1 VDIFF1 FB0 PHASE1 PC205 0.01U_0402_25V7K 27 LGATE1 28 PR235 4.02K_0402_1% 0.1U_0402_16V7K PC208 680P_0603_50V7K 29 PGND1 @ PQ47 AON6704L_DFN8-5 PC200 680P_0603_50V7K LGATE1 10 PC219 2200P_0402_50V7K 2 ISL6265IRZ-T_QFN48_6X6~D VDIFF0 +CPU_CORE PR232 16.2K_0402_1% PR233 4.7_1206_5% OCSET +5VALW LGATE0 PL17 0.36UH_PCMC104T-R36MN1R17_30A_20% PQ48 AON6704L_DFN8-5 PC199 0.1U_0603_25V7K 30 om PVCC RBIAS PR229 2.2_0603_5% BOOT0 1 LGATE0 31 ENABLE UGATE0 yc 32 PQ46 AON6428L 1N DFN-8 PGND0 +VDDNB Design Current: 2.8A Max current: 4A OCP_min:5A UGATE_NB 37 38 39 LGATE_NB PHASE_NB 40 41 PGND_NB OCSET_NB 42 RTN_NB SVC RTN0 VW0 44 +1.5VS DIFF_0 43 33 CPU_VDD0_FB_L PR245 FSET_NB PHASE0 PR241 10_0402_5% CPU_VDD1_FB_L VSEN_NB 46 SVD VSEN0 +CPU_CORE 45 13 CPU_VDD0_FB_H FB_NB PHASE0 ISP0 ISN0 COMP_NB 47 VCC 48 VIN PR239 95.3K_0402_1% UGATE0 ISP0 BOOT0 34 VSEN1 0_0402_5% 35 UGATE0 RTN1 PR236 BOOT0 PWROK RTN0 CPU_SVC PGOOD VSEN0 0_0402_5% BOOT_NB 15 PR242 0_0402_5% 16 0_0402_5% PR244 17 0_0402_5% 18 PR250 PR234 36 PHASE0 BOOT_NB OFS/VFIXEN ISN0 CPU_SVD VR_ON PR238 21.5K_0402_1% CPU_VDDNB_FB_L PR237 0_0402_5% 2 PR231 0_0402_5% @ H_PWRGD_L PR226 10_0402_5% PC192 220U_D2_4VM CPU_B+ PC204 4.7U_0805_25V6-K 2 2 1 VGATE + LGATE_NB PR224 0_0402_5% PU15 2 UGATE_NB PR228 @ 105K_0402_1% 2 PR227 105K_0402_1% PC193 680P_0603_50V7K PHASE_NB PR225 @ 10K_0402_1% PHASE_NB PR223 @ 105K_0402_1% +CPU_CORE_NB PR217 4.7_1206_5% CPU_VDDNB_FB_H PR221 13.7K_0402_1% PR220 0_0402_5% PC194 0.1U_0603_16V7K 1 PR222 0_0402_5% LGATE_NB PR219 2_0603_5% +3VS +CPU_CORE_NB +5VS PL16 3.3UH_SIQB74B-3R3PF_5.9A_20% PQ70 AO4712_SO8 PR218 10_0402_5% +3VS + 2 PC191 0.1U_0603_25V7K PR216 22K_0402_1% 2 CPU_B+ PHASE_NB B+ 1 PC189 1000P_0402_50V7K PC190 0.1U_0603_16V7K UGATE_NB PR230 2.2_0603_5% BOOT_NB PC195 4.7U_0805_25V6-K PR215 2_0603_5% +5VALW PC184 1200P_0402_50V7K PC188 220U_25V_M PC203 4.7U_0805_25V6-K 1 PR214 44.2K_0402_1% 2 1 PL15 FBMA-L18-453215-900LMA90T_1812 PC187 2200P_0402_50V7K PQ69 AO4466_SO8 PC186 0.01U_0402_25V7K PC185 10U_1206_25V6M CPU_B+ PC183 33P_0402_50V8K H PC222 0.01U_0402_25V7K D PC221 0.01U_0402_25V7K C PC220 2200P_0402_50V7K B ISN0 A PR249 4.02K_0402_1% PC209 0.1U_0402_16V7K VW1 COMP0 PC211 180P_0402_50V8J PR255 1K_0402_5% PR256 PC216 2 PC212 1000P_0402_50V7K PR257 6.81K_0402_1% 2 COMP1 PC214 180P_0402_50V8J PR258 1K_0402_5% PR259 PC217 1 PC215 1000P_0402_50V7K PR260 6.81K_0402_1% 1 54.9K_0402_1% 1200P_0402_50V7K 54.9K_0402_1% 1200P_0402_50V7K ISN1 PR254 PC213 255_0402_1% 4700P_0402_25V7K FB_1 2 ISP1 LGATE1 PR253 PC210 255_0402_1% 4700P_0402_25V7K FB_0 2 PR263 @ 1K_0402_5% PR262 @ 1K_0402_5% 4 2010/04/12 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2010/10/12 Title +CPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D E F G Document Number Rev B NAV71 Thursday, July 22, 2010 Sheet 42 H of 45 Version change list (P.I.R List) Item Fixed Issue Reason for change Rev PG# D Modify List Page of for PWR Date Phase Add PR279,PR288,PC57 Change PR285 100K to 47K Change PR287 20K to 14.3K Change PQ67 2N7002 to PDTC115 Change PR62 47K to 200K Change PR79 22K to47K Change PR283 to 100K 2010 0528 PVT Change PJ30 to PL36, PJ23 to PL37 Add PC361,PC362 2010 0602 PVT Change PR265 from 30K to 30.9K 2010 0604 PVT D Modify Pre-charger Meet common rule HDMI test fail 5V voltage too low at test termial ESD test fail ESD solution Add PC22, PC23 2010 0608 PVT EMI test fail EMI solution Enable 3V,5V,1.1V,1.5V,NB_CORE,CPU snubber 2010 0608 PVT su /x / 36 C Costdown Costdown 38 10 For DDR voltage default/HW YC Aprove 200MHz~220MHz/EMI Chris DDR need 0.9V, DDR need 1.05V But DDR2 voltage is critical then DDR // m EMI solution Add a bypass path/ESD Chris ESD solution PVT 2010 0617 PVT 39 Disable PR152 Enable PR160 2010 0705 Pre MP 37 Enable PR80, PC128 Change PR82 from to 2.2 2010 0705 Pre MP Add PC26 near PC22 2010 0705 35 Pre MP ht 12 Change PQ28 from AO4456 to AO4712 Change PR112 from 13K to 18.2K Change PL7 from 1.0uH to 1.8uH Change PQ61 from AO4712 to AO4468 PR268 from 133K to 137K PQ57 from AO4466 to AO4468 2010 0609 B : B 11 Change PR144 from 22K to 200K Change PC156 from 0.47u to 0.22u p 41 om Power sequence tune yc C 13 14 15 A A 16 2010/04/12 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2010/10/12 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: PIR (PWR) Rev B PEW96 LA-6552P Sheet Thursday, July 22, 2010 43 of 45 Version change list (P.I.R List) Item Fixed Issue Reason for change Rev PG# Modify List Page of for PWR Date Phase D D /x / su C om p C yc // m 10 B : B 11 ht 12 13 14 15 A A 16 2010/04/12 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2010/10/12 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: PIR (PWR) Rev B PEW96 LA-6552P Sheet Thursday, July 22, 2010 44 of 45 05/10 First release Change Cardreader chip (RTS5137/RTS5138) ODD used to ODD sub/b RTC Battery change (w/o charge) D D 06/11 PVT P.28 Reserve R889 For EC_CLK, pop R851, unpop R852 For EC_SMBus leakage P.26 Remove R853 P.28 project ID >1 Board ID >1, unstuff KSI, KSO Cap P.8 Change R41 as 31.6k ohm and R42 as 30k ohm for TSI 07/05 Pre-MP P.19 Reserve R890 For MEM_1V5 /x / P.28 Change R419 as 10 ohm For EMI 07/20 P.29 Change R477, R499 as 750 ohm; change R478 as 3.01k ohm; change R498 as 3.3k ohm for LED light C // m yc om p su C B ht : B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/04/12 Deciphered Date 2010/10/12 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: HW PIR Document Number Rev B PEW/76/86/96 LA-6552P Thursday, July 22, 2010 Sheet 45 of 45 ... RJ45_MIDI0+ RJ45_MIDI0- LAN_MIDI1+ LAN_MIDI1- LAN_MIDI1+ LAN_MIDI1- TCT2 TD2+ TD2- MCT2 MX2+ MX2- 21 20 19 RJ45_MIDI1+ RJ45_MIDI1- LAN_MIDI2+ LAN_MIDI2- LAN_MIDI2+ LAN_MIDI2- TCT3 TD3+... B C E Danube Compal Confidential AMD S1G4 Processor PCB Model Name : PEW96 File Name : LA- 6552P P/N : DA60000IM10 D ZZZ Memory BUS(DDR3) uPGA-638 Package Champlain page 6,7,8,9 LA- 6552P MB Rev0:... WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: LAN Magnetic & RJ45 Document Number PEW/76 /86/ 96 LA- 6552P Thursday, July 22, 2010 Sheet 25 of 45 Rev B A B C D E Mini-Express Card for WLAN +3VS +1.5VS