Introduction to Testbenches Objectives After completing this module, you will be able to: • • • Define a testbench Describe behavioral modeling Write a simple testbench Introduction to Testbenches - - © 2007 Xilinx, Inc All Rights Reserved Outline • • • • • Introduction to Testbenches - - Testbench Concept Behavioral Coding Assertions Testbench Examples Summary © 2007 Xilinx, Inc All Rights Reserved Testbench Concept • A VHDL testbench is a virtual test bed – An upper-level hierarchical VHDL structure that applies input stimulus to a Unit Under Test (UUT) and monitors the output to verify functionality CNTR32_TB entity CNTR32 D_IN RST LOAD entity Q_OUT TC CLK Introduction to Testbenches - - © 2007 Xilinx, Inc All Rights Reserved Application of a Testbench Fewer details, verify design concept f Behavioral RTL AND_OR2 DFF Logic Technologyspecific details, slower design entry and simulation Introduction to Testbenches - - Layout © 2007 Xilinx, Inc All Rights Reserved CLB_ R5C5 CLB_ R5C6 Complete IEEE 1076 IEEE 1076 (Modeling) IEEE 1076 (Synthesis) Behavioral modeling in VHDL utilizes the broad capabilities of the language Introduction to Testbenches - - © 2007 Xilinx, Inc All Rights Reserved Simulation I/O Flexibility • VHDL provides considerable flexibility for declaring and accessing files, along with various formats of data inputs and outputs TESTBENCH entity UUT entity • Text-based data operations are specified in the textio package Introduction to Testbenches - - © 2007 Xilinx, Inc All Rights Reserved Maintaining Consistency Ideally, the same testbench could be applied at each stage of verification VITAL • VHDL modules Behavioral/RTL simulation: Execute RTL source code Synthesis Post-synthesis VHDL simulation: Execute structural VHD file Place & Route VHDL timing simulation: Execute post-layout structural VHD and SDF file SDF and Structural VHD Introduction to Testbenches - - © 2007 Xilinx, Inc All Rights Reserved Outline • • • • • Introduction to Testbenches - - Testbench Concept Behavioral Coding Assertions Testbench Examples Summary © 2007 Xilinx, Inc All Rights Reserved Behavioral Coding • A testbench (behavioral) description has advantages not available in RTL-level code or actual hardware – Values stored in signal signal RST: std_logic := ‘0’ ; – Model bus input and output D_IN