Concurrent and Sequential Statements Objectives After completing this module, you will be able to: • • • • • Write a VHDL process Define when signals are updated Differentiate between signal transactions and events Determine how and when signals are read within the process Build a register by using a clocked process Concurrent and Sequential Statements - 11 - © 2007 Xilinx, Inc All Rights Reserved Outline • • • • • • • Hardware Modeling Process Modeling Concurrency Transactions and Events Signal Declaration Signal Assignments Summary Concurrent and Sequential Statements - 11 - © 2007 Xilinx, Inc All Rights Reserved Hardware Modeling • • • To effectively model a hardware environment, VHDL utilizes both concurrent and sequential statements Concurrent statements are called concurrent because they are treated as simultaneous operations with respect to each other, although they may exist at different locations in the overall code Sequential statements are called sequential because they are treated in sequence, like conventional software – All statements within a process are treated sequentially Concurrent and Sequential Statements - 11 - © 2007 Xilinx, Inc All Rights Reserved Language Structure architecture RTL of ENTITY_1 is begin concurrent statements ; process begin • sequential statements ; end process ; concurrent statements ; • process begin sequential statements ; end process ; end architecture RTL ; Concurrent and Sequential Statements - 11 - Any statement outside of a process is inherently concurrent All processes are concurrent to each other © 2007 Xilinx, Inc All Rights Reserved Outline • • • • • • • Hardware Modeling Process Modeling Concurrency Transactions and Events Signal Declaration Signal Assignments Summary Concurrent and Sequential Statements - 11 - © 2007 Xilinx, Inc All Rights Reserved Process • A process contains statements that are executed sequentially – • The order of the statements impacts the final result Each process has a means for being triggered – By changes on signals into the process or specific conditions as expressed in a wait condition Concurrent and Sequential Statements - 11 - architecture RTL of MY_AND2 is begin process (A, B) begin C