VHDL Operators and Expressions Objectives After completing this module, you will be able to: • • • • Recognize standard expressions via VHDL operators Reference sub-bus structures by using array slices Make assignments by using the VHDL concatenation operator Apply the concept of operator overloading in VHDL VHDL Operators and Expressions - - © 2007 Xilinx, Inc All Rights Reserved Outline • • • • • • • • VHDL Operators and Expressions - - Overview Logical Operators Relational Operators Arithmetic Operators Shift Operators Concatenation Array Slice Summary © 2007 Xilinx, Inc All Rights Reserved Operators in VHDL • VHDL contains a wide variety of operators for modeling hardware • Note, however, that each operator is defined for specific data type(s) – • Most notably, arithmetic operators are not predefined for composite (bit_vector and std_logic_vector) data types because the array has no explicit numerical value Functions (subprograms) have been developed to compensate for cases such as this – – These are contained in so-called arithmetic packages The subprograms are overloaded to support a variety of arithmetic operations and data types that are not otherwise predefined in the language VHDL Operators and Expressions - - © 2007 Xilinx, Inc All Rights Reserved Outline • • • • • • • • VHDL Operators and Expressions - - Overview Logical Operators Relational Operators Arithmetic Operators Shift Operators Concatenation Array Slice Summary © 2007 Xilinx, Inc All Rights Reserved Logical Operators • Logical operators are predefined for bit, boolean, bit_vector, and std_logic_vector data types A Z B F Z