ĐIỆN tử VIỄN THÔNG 07a simulate intro khotailieu

VHDL Simulation and RTL Verification Lab Introduction Objectives After completing this lab, you will be able to: • • • • Create a VHDL testbench to verify the AND_OR hierarchical structure created in the previous lab exercise Use the testbench wizard in the ISE™ software Create basic input stimulus Run a simulation VHDL Simulation and RTL Verification Lab Intro - 7a - © 2007 Xilinx, Inc All Rights Reserved General Flow • • • Step 1: Create a testbench Step 2: Create simple input stimulus Step 3: Verify logic functionality VHDL Simulation and RTL Verification Lab Intro - 7a - © 2007 Xilinx, Inc All Rights Reserved