Memory and Record Lab Introduction Objectives After completing this lab, you will be able to: • • • • Use the record data type to create a user-defined synchronous RAM structure Create the first component for the Calculator module Combine various VHDL objects Verify the logic structure Memory and Record Lab Intro - 10a - © 2007 Xilinx, Inc All Rights Reserved General Flow • • Step 1: Create a package with a user-defined record data type Step 2: Create a synchronous RAM Memory and Record Lab Intro - 10a - © 2007 Xilinx, Inc All Rights Reserved