MOSFET MODELING FOR VLSI SIMULATION - Theory and Practice Episode 13 ppsx

456 9 Data Acquisition and Model Parameter Measurements LCR METER ".0-/ 0.5 CURVE 0'0-2 -1 GATE VOLTAGE V, (V) (b) Fig. 9.3 1 (a) Experimental setup for measuring gate-to-channel capacitance CGc. (b) C,, as a function of gate voltage V,, for 3 different substrate biases V,, = 0,l and 3 V. The dotted lines are inversion charge density Q, (= QJWL) calculated using Eq. (9.53) To measure gate to substrate capacitance C,,, the source and drain are connected to the ground, the substrate to the 'Lo' terminal of the capacitance meter and the gate to the 'Hi' terminal as shown in Figure 9.32a. Once C,, as a function of VgS is known, the Q, can be obtained using Eq. (9.54) using the same procedure as for calculating Qi. Figure 9.32b shows measured gate-to-bulk capacitance C,, of an nMOST (the device whose C,, is shown in Figure 9.31b) for three different V,, (= 0,l and 3 V). The corresponding Q, are shown as dotted lines. 9.10 Determination of Effective Channel Length and Width 457 3 0 '0, #I #2 E)dv\ 0 I-:) ; #3 -3 -1 1 3 gC I II .05 1.00 GATE VOLTAGE Vq (V) (b) Fig. 9.32 (a) Experimental setup for measuring gate-to-hulk capacitance CGB. (b) CGR as a function of gate voltage V,,, for 3 different substrate biases VAh = 0, 1 and 3 V. The dotted lines are hulk charge density QB (=Qb/WL) calculated using Eq. (9.54) 9.10 Determination of Effective Channel Length and Width The most basic parameters of a MOSFET are those which define the effective or electrical length Land width W of the transistors. These param- eters play an important role in governing the device characteristics of small geometry devices. The device L differs from the drawn channel length L, (physical mask dimensions) by a factor AL such that L= L, - AL [cf. Eq. (3.32)]. Similarly, the device W is generally smaller than the drawn device width W, (physical mask dimension) by a factor AW such that W = W,,, - A W [cf. Eq. (3.33)]. It is the L and W and not L, and W, which are used for modeling MOSFET devices (cf. section 3.7). This in turn requires AL and A W to be known. In this section we will discuss various methods of determining AL and A W of a MOSFET. 458 9 Data Acquisition and Model Parameter Measurements Basically, there are two methods of determining AL and A W. These are: Drain current method: [60]-[85] In this method, the drain current Id, is measured as a function of gate voltage V,, at a low drain voltage (Vds < 0.1 V) and fixed back bias V,,, generally zero volts. The low Vd, ensures device operation in the linear region. Capacitance method: [86]-[90] Here device gate-to-channel capacitance C,, is measured as a function of V,, at zero V,, with source and drain tied together. The drain current method is the most widely used for determining AL and AW because of its simplicity. It should be pointed out that either of the I-V or C-V methods of extracting AL(A W) results in the effective channel L(W) that is purely an electrical parameter, as discussed in section 3.7. 9.10.1 Drain Current Methods of Determining AL Various drain current methods, reported in the literature, to determine AL are based on the following drain current equation in the linear region [cf. Eq. (6.225)] (9.55) where Do = poCox WIL and we have assumed 9, to be zero. This assumption (of 0, = 0) is made for all methods of AL and A W extraction using Id, - Vgs data in the linear region [65]. It is a good approximation provided these parameters are extracted at zero back bias, which indeed is generally the case for AL and A W extraction. However, if V,, is not zero, then neglecting 8, will cause error in the extraction. Different drain current methods use Eq. (9.55), and its variation, to determine AL. Channel-Resistance Method. The one most commonly used method of AL extraction is the so called channel resistance method. In this method AL is extracted by measuring the response of the device channel resistance to the change in the gate voltage V,, or gate drive (V,, - Vth) at fixed V,b. The intrinsic channel resistance R,, of an MOSFET operating in the linear region is given by [cf. Eq. (6.52)] (9.56) The total resistance R, measured between the source and drain terminals is simply R, = R,, + Rr (9.57) 9.10 Determination of Effective Channel Length and Width 459 where R, is sum of the source and drain resistances. Combining Eqs. (9.56) and (9.57) we get r (9.58) which can be written as R, = A(L, - AL) + R, (9.59) where Physically, A is the channel resistance per unit length. To unambiguously determine AL from Eq. (9.59) it is important that (1) R, be independent of the external bias, and (2) A be independent of the channel length. If these two conditions are met then from Eq. (9.59) it is evident that at a given V,,, the plot of the measured R, against the drawn channel lengths L,,. for sets of adjacent transistors with the same channel widths, will be a straight line given by (9.60) R, = A.L, + B where the intercept B is B = R, - A'AL. (9.61) Repeating the plot for different gate voltages Vgs will result in a set of straight lines. In the ideal case, these different lines will all intersect at one point with the point of intersection giving Rr on the R, axis (y-axis) and AL on the L, axis(x-axis), as shown in Figure9.33. However, often R, versus L, lines fail to intersect at a common point. In that case the method is carried over one step further by using second linear regression of the plot of B versus A obtained from different gate voltages V,, [cf. Eq. (9.61)]. The slope and intercept of B versus A line gives AL and R,, respectively. To avoid any narrow width effect wide test transistors should be used. Further, since V,,, is channel length dependent, one should use higher gate biases (e.g. V,, > 4-5 V) in order to minimize the effect of short channel V,, fall off on the parameter A. Since VLSI circuits require smaller gate biases ( Vgs I 5 V), to minimize the effect of varying V,, the proper method would be to adjust V,, so that the effective gate drive V,,( = Vgs - Vt,) is equal for all transistors. This way, one can use lower VgS and also ensure that A is constant. The possible device to device variations of ,us, W and Cox, for the same die, are neglected in the analysis, although they can contribute to the error in the AL extraction. It has been pointed out that the method of determining V,, also affects the extracted AL and R,, particularly when using small gate drive, say V,, = 460 9 Data Acquisition and Model Parameter Measurements CHANNEL LENGTH L, (pm) Fig. 9.33 Measured output resistance R, versus drawn channel length L, for nMOST with to, = 300& Lines with different gate voltages intersect at one point from which AL and R, are derived 0.5V [67], 1681. The V,, determined from the constant current method, rather than the linear extrapolation method, was found to be more consistent. This is because the V,, measurement by linear extrapolation method is sensitive to the S/D resistance in series with the MOSFET channel resistance [67]. This method, first proposed by Terada and Muta 1601, was reformulated by Chern et al. [61] and later slightly modified by many others [62]-[68]. It is the most commonly used method for determining AL and has become widely established as an industry standard. This is probably because of its accuracy [62] and the fact that the method also gives source/drain resistance R, at no extra cost. The method is sensitive only to the measurement noise and does not respond to the device-to-device variation. The precision of the extracted AL is limited to the precision with which L, is known [63]. Thus, in this method, AL and R, are extracted using the following procedure: 1. Measure I,, at low V,, (typically 50mV) and zero Vsb, by sweeping Vgs in steps of 0.1 V (or 0.05 V), for a set of transistors having the same channel width W,,, but varying channel lengths L,. 2. Determine V,, for each device using data from step 1. 3. For a fixed gate drive V,,(= V,, - V,,), determine the device output resistance R,( = V,,/I,,,) for different mask length (L,) devices using data from steps (1) and (2). The measured R,, at fixed V,,, is plotted against 9.10 Determination of Effective Channel Length and Width 46 1 t / 1 4.0 0.0' ' ' ' *=rL " % ' " I' ' ' " 0.0 1.0 2.0 3.0 CHANNEL LENGTH, L,oJm) (a) 0.0 0.2 0.L 0.6 0.8 1.0 1.2 1.L 1.6 1.8 Ai (103n/cm) (b) Fig. 9.34 (a) Measured output resistance R, versus drawn channel length L, for nMOST with to, = 150 A. Lines with different gate drive voltage (V,, - V,,,) gives slope Ai and intercept Bi; (b) the plot of intercept Bi against slope Ai for different gate drives. The slope and intercept of this line yield AL and R, different L,. The linear regression of this line" gives slope A, and intercept B,. 4. Repeat step 3 for different gate drives Vqt in the range from 1.0 to say 5V, in a step of, say, 0.5V giving sets of Ai and B,. 5. The intercepts Bi, obtained from step 4, are then plotted against the corresponding slopes A,. The linear regression is applied again on B l1 A linear least square regression formula based on equation Y = AX + B is given in Appendix G. The regression not only gives the intercept and slope of the line, but will also yield correlation coefficient. 462 9 Data Acquisition and Model Parameter Measurements versus A line. The slope and intercept of this line give AL and R,, respectively. Figure 9.34a shows plots of the measured resistance R, versus drawn channel length L, = 1,1.5,2 and 3 pm and constant width W, = 12.5 pm for V,,(= Vgs- V,,) from 0.5V to 3V in steps of OSV. These are the n- channel conventional source/drain devices fabricated using a typical 1 pm CMOS technology, with to, = 150A and V,, = 0.5 V. The least square regression is applied to fit the straight line through the data for each specified gate drive (Figure 9.34a). A second regression is applied to Bi versus Ai data to find the slope and intercept giving AL and R,, respectively (see Figure 9.34b). Other Resistance Methods. The resistance method discussed above requires more than two devices with varying channel lengths. Various other resistance methods, based on Eq. (9.53, have been proposed which require only two devices that are identical except for the channel length. Rearranging Eq. (9.55) as [SO] (9.62) we plot the resistance R, against (Vq, - VtJ1 for each channel length as shown in Figure 9.35a. Note that R, varies linearly with (V,, - V[h)-' as suggested by Eq. (9.62). The nonlinearity near (V,, - V,,) = 0 results from the breakdown of the approximation used in arriving at Eq. (9.62). The v,h required is normally obtained by linear extrapolation of the Id, - Vgs curve. The slope of the straight line portion of the R, versus (Vqs - VJ' curve yields l/po and the intercept (to the R, axis) yields I9( = I9,/p0 + R,). Once 9 and Po are obtained for devices with different L, and fixed W,, AL can be obtained using the following equation (9.63) Figure 9.35b shows a plot of versus L,; the ratio of the intercept to the slope of this line gives AL. However, if we plot intercept 0 against slope 1/p0 for different L,, then the intercept of this second regression line gives R,. It is important to note that in this method only two transistors are sufficient to calculate AL. If two transistors have the same width, the following relationship between any pair of transistors can be obtained from Eq. (9.63) that is, (9.64) 9.10 Determination of Effective Channel Length and Width 1' - - CURVE METHOD - 463 L.o t N > 2.0 0 Q" 1.0 n.n 1 @ Moneda etal. @ Suciu etal. Eq. (9.62) Eq. (9.67) _- @ 9, Eq. (9.70) -1.0 ' 1 I' I' ' ' '1 '1 '1 ' 012345678 CHANNEL LENGTH L,(pm) (b) Fig. 9.35 (a) Measured output resistance R, versus (V,, - VJ1 with channel lengths L, as a parameter for nMOST with to, = 150 8, (W, = 12.5 pm). Slope of these lines yields p; ' for each length L,. (b) The plot of b; ' versus L, gives AL where L,, and L,, are drawn channel lengths for the two transistors and pol and Po, are their corresponding Po values. Rearranging this equation yields (9.65) 464 9 Data Acquisition and Model Parameter Measurements If one of the two transistors has a considerably longer channel length, the accuracy of the AL extraction is substantially increased. The advantage of this method is that it can be used to determine AL for a small device, provided we also have a large geometry device. Assuming do and R, are independent of channel length, the series resistance R, can be obtained from the following equation R, = 01 - 02 (9.66) where Q1 and d2 are the values for (do/po + R,) for the devices with channel length L,, and Lm2, respectively. In a method proposed by Suciu and Johnston [79], the quantity E, obtained by rearranging Eq. (9.55), defined as 2(801 - 802) (9.67) is plotted against (V,, - Vth) for each channel length L,, as shown in Figure 9.36. Note that E varies linearly with (V,, - V,,,) as suggested by Eq. (9.67). The extrapolation of the straight line portion of the E versus (VgS - Vth) curve to the E axis results in l/po and the slope gives O( = eo/Po + R,). Once Po for different lengths are known then AL can easily be calculated (see Figure 9.35b). As expected, results obtained from Eq. (9.62) and (9.67) are exactly the same as both methods are derived from the same basic equation. Note that the plot of the slope 8 vs. '/Po for different L, gives R,. I I I I 171 >" 0.8 I1 w 0.4 0.0 0.5 1.0 1.5 2.0 2.5 3.0 (Vgs-Vth) (V) Fig. 9.36 Variation of function E versus (V,. - Vth) with channel lengths L, as a parameter for nMOST with to, = l50A (W, = 12.5pm). The intercept (to E axis) yields pi' for each length L,. From the plot of /I; versus L, is derived AL. as shown in Figure 9.35b 9.10 Determination of Effective Channel Length and Width 465 Transconductance Method. Another method which is often used for AL extraction is based on the transconductance g, of the device. Differentiating Eq. (9.55) with respect to V,, yields (9.68) from which the maximum transconductance gm,max can be seen to be (9.69) provided maximum g, occurs at a point where Vg,= V,,. However, in practice, maximum gm occurs at a point slightly above the threshold voltage (obtained by the linear extrapolation method). Therefore, Eq. (9.69) is accurate only when R, can be neglected. Remembering that L = L, - AL, Eq. (9.69) can be rearranged as gm,max -' = A-'(L, - AL) (9.70) where A = Po Cox WVdS If we have devices with the same W, but different drawn channel lengths L,, then the plot of l/g,,,,, versus L, will be a straight-line, the extrapolation of which results in AL. In practice gm,ma, is determined from the point of maximum slope of the experimental Id, versus Vgs curve at small Vds. This method is referred to as the gm or 1/P method. Figure 9.333 shows a data plot for this method. Devices used are the same as in Figure 9.33. Note the difference between the gm method and the one based on Eqs. (9.62) or (9.67). While the gm method requires derivative of Id, to calculate Po, in the other methods Po is obtained from measured output resistance. The main drawback of this method is that it neglects the source/drain resistance R,. This results in data points not falling on a straight line when different device lengths are used. This nonlinearity introduces an error, which tends to underestimate AL. The higher the R,, the higher the error. This method is, therefore, not suitable for LDD devices, where R, is high. If R, is small compared to the channel resistance, as is usually the case with standard source/drain or long-channel devices, this method yields AL fairly close to the resistance method [cf. Eqs. (9.62) or (9.67)]. Also note that, unlike the resistance method, this method does not yield R,. Transresistance Method. The gm method requires more than two devices to determine AL. A method which requires only two devices and is based on both device transconductance gm and output conductance gd has recently [...]... (I,)) 1 0-1 / n+p DIODE lo-‘ U 103 1 0-4 F z- w 1 0-5 U U = I 0 I * = 4.53 x 1 0 - 1 4 ~ n = 1.119 1 0-6 u 8 lo-’ 1 0-8 / P F 1 0- Od.O ::0 014 d.6 018 1 I DIODE FORWARD VOLTAGE, V (V) d Fig 9.5 1 Diode saturation current measurement procedure showing measured (circles) and calculated (continuous line) diode current 9.14 MOSFET Source/Drain Diode Junction Parameters Table 9.3 Diode parameters I 1 49 1 and r... method is more useful when V,,,, is required for substrate current modeling 9.12 Measurement of MOSFET Intrinsic Capacitances Several methods have been developed to measure MOSFET intrinsic capacitances [loo ]-[ 1031 These methods can be broadly divided into two classes: ‘on-chip’ methods [loo ]-[ lo71 and ‘ofS-chip’ methods [108 ]-[ 113] In the so called ‘on-chip’ methods, a special measurement circuit... fringing fields between the gate and the side walls of the n- region This will cause C,,, and hence the effective channel length L, to be smaller (AL to be larger) than the actual value [89] It has been reported that there exists a fine structure (flat portion between - 0.6 V to - 1.1 V for n-channel device with W/L = 510.25 pm) in C-V data for short-channel devices [90] Therefore, one can use Eq (9.75)... true for standard source/drain junctions for large geometry devices.” For short channel devices or for LDD devices, the measured capacitance in accumulation becomes bias dependent, as can be seen from Figure 9.49 which is the plot of gate to S/D capacitance versus gate voltage for an n-channel (W,/L, = 50/1) LDD device (continuous line) For comparison, a device with the same W,/L, and Coxbut with standard... commonly used for intrinsic capacitance measurements 9.1 2.1 On-Chip Methods The first on-chip technique, proposed and implemented by Iwai and Kohyama [loo] and later improved by Oristian et al [ l o l l , is based on 478 9 Data Acquisition and Model Parameter Measurements I I N ON CHIP 1 Fig 9.44 Circuit schematic for on-chip open loop capacitance measurement technique a capacitance voltage divider formed... The experimental setup to measure gate-to-source or gate-to-drain overlap capacitance is the same as that shown in Figure 9.38a The gate of the MOSFET is connected to the ‘Hi’ terminal of the HP4275A LCR meter, whose ‘Lo’ terminal is connected to the shorted source and drain The bulk (substrate)is grounded 1911 However, one can also use the lock-in-amplifier 485 9 .13 Measurement of Gate Overlap Capacitance... voltage (2 0-3 0 mV peak-to-peak) of frequency 100 KHz is superimposed on the gate voltage, which is stepped from V,(max) (accumulation) to - V,(max) (inversion), and the corresponding gate capacitance C, is measured When the device (say p-channel) is biased in strong accumulation, a layer consisting of free electrons is formed under the gate, which is electrically disconnected from the p + source and drain... Therefore, a good least square fit alone can not be used to justify the accuracy of the measurement technique The value of AL = 1.54pm at Vgs= 0 V is within 4% of that determined by the resistance method Therefore, it has been suggested that for LDD n-channel devices one can use Vgs= 0 rather than Vgs= - 5 V (accumulation) for calculating C,, This is because in this case the n- region is not depleted and. .. the MOSFET terminals, while the gate bias is applied through the negative terminal of the op- 480 9 Data Acquisition and Model Parameter Measurements n (a) OP-AM I + I I I I L i "out I I ON CHIP (b) Fig 9.45 Circuit schematic for on-chip closed loop capacitance measurement method (a) switched capacitance AC gain stage (b) setup for measuring C,, amp A switch (pass transistor M 1) is required for. .. the op-amp Although the on-chip capacitance methods have good resolution, the requirement for the fabrication of a spccial on-chip circuit around the device of interest have prevented these methods from being widely adopted The technique requires dedicated masks for the fabrication of the test structures Moreover, a well-established fabrication process is required and the measurement circuit (op-amp) . structure (flat portion between - 0.6 V to - 1.1 V for n-channel device with W/L = 510.25 pm) in C-V data for short-channel devices [90]. Therefore, one can use Eq. (9.75) to. Length and Width 457 3 0 '0, #I #2 E)dv 0 I-:) ; #3 -3 -1 1 3 gC I II .05 1.00 GATE VOLTAGE Vq (V) (b) Fig. 9.32 (a) Experimental setup for measuring gate-to-hulk. [cf. Eq. (3.33)]. It is the L and W and not L, and W, which are used for modeling MOSFET devices (cf. section 3.7). This in turn requires AL and A W to be known. In this section