MOSFET MODELING FOR VLSI SIMULATION - Theory and Practice Episode 11 pdf

376 8 Modeling Hot-Carrier Effects I GATE \ ?O T "C 0 0- * A 5 U B S 1 RATE i fY Fig. 8.5 Electron injection in gate oxide showing lucky electron model electron arrives at location D, it will be swept toward the gate electrode by the aiding field. Since the processes are statistically independent, the resultant probability is the product of the probability for each individual event, i.e. [23] (8.22) where 2, is the redirectional scattering mean free path. The factor (dy/A,) can be interpreted as the probability of redirection over dy. PI is the prob- ability for acquiring sufficient kinetic energy and normal momentum, P, is the probability that a hot electron travels to the Si-SiO, interface without suffering any inelastic collision, and P, is the probability to suffer no collision in the oxide image-potential well. Thus, to calculate I,, we need to calculate the three probabilities P,, P, and P,. The essential processes involved for modeling channel hot-electron injection into the gate oxide is illustrated in Figure 8.6. In order for the hot electron to surmount the Si-SO, potential barrier Qb, its kinetic energy must be greater than qQb. To acquire kinetic energy qQb, the hot electron will have to travel a distance d = Qb/& assuming the electric field 6 along the channel to be constant. The probability of a channel electron to travel a distance d or more without suffering collision can be written as e-d/n, where A is the scattering mean free path of the hot electron [25]. Hence we can write e-Qb/B* as the probability that an electron will acquire a kinetic energy greater than the potential barrier Qb. Now if the electron is to move into the oxide, its momentum must be redirected towards the Si-SiO, interface by elastic scattering so as to have sufficiently large momentum component perpendicular to the interface. It has been shown that the probability of an electron acquiring the required kinetic energy and retaining the appropriate momentum after redirection is [23] (8.23) 8.2 Gate Current Model Pa : NO COLLISION BEFORE REACHING INTERFACE 371 Fig. 8.6 : GAINS ENOUGH ENERGY - 1 ' . *- >.: prP3 : NO COLLISION IN FIELD REVERSAL REGION BY GATE SILICON OXIDE METAL T L Q, E ox GATE OXIDE METAL L E ox SILICON Q, The energy system for the MOS structure showing essential processes in hot electron injection model. (After Tam et al. [23]) the channel Since the potential barrier Qb is lowered by the image force effect, the net barrier height is generally expressed as [22,23] (8.24) where Qb0 = 3.2eV is the Si-SiO, interface barrier for the electrons, €ox is the oxide field given by [cf. Eq. (6.195)] a+, = mbo - 2.59 x 10-4€;~ - a,€;? (8.25) *ox and a, is a constant whose value is obtained by fitting the experimental data; Ning et al. [22] have assumed a. = 1 x (cm), while Tam et al. [23] find a, = 4 x (cm) as a more appropriate value for their data. The second term in Eq. (8.24) represents the barrier lowering effect due to the image field, while the third term accounts phenomenologically for the finite probability of tunneling between the Si and SOz. According to Tam et al. [23], the probability P, is given by 5.66 x 10-6€ox P, % (1 + 80x/i.45 x 105) + 2.5 x lo-' (8.26) while the probability P, of colision-free travel in the oxide-image potential 1 X { 1 + 2 x exp( - $€,,to,)} 378 8 Modeling Hot-Carrier Effects well is given by where Lox = 3.2 nm is the electron mean free path in the oxide. Note that the product of P, and P, is essentially only a function of the gate oxide field &ox, therefore, it can be combined as P,P, = P(&ox). It is found that P(&J is a weak function of &ox; its value is maximum at the drain end corresponding to the oxide field given by Eq. (8.25). Since the probability PI depends exponentially on &, which in turn varies exponentially with y [cf. Eq. (6.201)a], the integrant in Eq. (8.22) is a sharply peaking function. Combining Eqs. (8.22)-(8.27) gives an approximate expression for the gate current as (8.28) where Ern is the maximum channel field and dbldx z bmm/lche is assumed to be constant over the length lche where CHE injection is significant. Since value for lche is not known, it can be treated as a fitting parameter; however, it can be replaced by to, without any loss of accuracy in the equation above [23]. The Eq. (8.28) can now be integrated to give a closed form expression for the gate current as (8.29) To a first order above equation can be written as [6] I, z c21dexp( - $) (8.29a) where C, is about 2 x for VgS > Vds. Note that the only fitting param- eters in Eq. (8.29) are L and A,. It was found that the gate current data is insensitive to the value of A, and has been chosen to be 61.6nm based on theoretical considerations [23]. The value of A which fits the data well is found to be 9.2 nm. It is worth noting that while the substrate current I, depends only on the channel electric jield &rn, the gate current I, is a function of both the channel jield &m and the normal oxide jield &ox. The gate current resulting from the channel hot-electrons in a nMOST is shown in Figure 8.7 where circles are experimental data points while continuous lines are calculated based on Eq. (8.29). Although the model is not very accurate near the peak current, it nonetheless does model the 8.2 Gate Current Model 379 Fig. 8.7 Gate current I, in an nMOST as a function of V,, at V,, = 10 V. (After Tam et al. [23]) general gate current behavior. The dependence of the gate current on the channel length is apparent. Reduction of the channel length reduces Vd,,,. Therefore, for the same vd, the channel electric field €,,,, and hence I,, is higher in shorter channel devices. The devices with thinner gate oxides have higher gate current because of higher €,,, and Figure 8.8 shows both gate and substrate current for an nMOST with to, = 200A and L = 1.1 pm. Note that peak gate current occurs at V,, z Vd, which is different from the peak of substrate current that occurs around Vgs z Vds/2. For a given V,,, the gate current I, increases with increas- ing V,, due to increasing €,,, until V,, = Vd,. For Vgs > Vd,, MOSFET is driven into the linear region of operation resulting in a reduction in &,,, and hence I,. The gate current shown in Figures 8.7 and 8.8 is due to CHE injection into the gate oxide. However, it has been observed experimentally that gate current in nMOST can also be generated by injection of hot holes into the oxide (particularly thin gate oxide, cox < 150A) (see section 8.4) [27]-[30] These holes are produced by impact ionization of the channel hot-electrons and are accelerated by the channel field. In order to evaluate this gate current component, the hole generation due to impact ionization and lucky electron probabilities for hole injection into the oxide must be modeled. 380 8 Modeling Hot-Carrier Effects t,,=~OO a I- '"0 2 L 6 8 10 12 GATE VOLTAGE, V,,(V) Fig. 8.8 Gate and substrate currents I, and I,, respectively, as a function of gate voltage V,, for different drain voltage V,, for a nMOST. (After Takeda et al. [26]) I I - p MOST L =O.LVrn t,,=105 A - - 0 - 0.0 2.5 GATE VOLTAGE,-Vg, (V) Fig. 8.9 Gate and substrate currents I, and I,, respectively, as a function of gate voltage V,, for different drain voltage V,, for a pMOST 8.2 Gate Current Model 38 1 The equivalent temperature model has also been used to model such hot- hole injection [28]. The gate current in a typical pMOST as a function of V,, and V,, is shown in Figure 8.9; for the sake of comparison the substrate current is also shown. Note that unlike in an nMOST, the peak of the gate current in a pMOST occurs at much lower gate voltage, similar to that for the substrate current. From the direction of the gate current measured at low and mid V,,, it is found that pMOST gate current is due to the avalanche hot-electrons (created by impact ionization ofholes) rather than the channel hot-holes [24], [31]-[33]. At higher I V,,l one expects the pMOST gate current to be composed of hot holes, but measurable channel hot-hole injection current in pMOST has not been reported. This is probably because of the large hole barrier height and much shorter mean free path for holes in the oxide. The electron gate current in pMOST is often larger than the corresponding nMOSTgate current, despite the fact that the number of available avalanche hot-electrons in pMOST's is several orders of magnitude smaller than in nMOST's. This happens because the direction of €ox is such that it aids electron injection in pMOST while it opposes electron injection in nMOST for V,,<< Vd,. For V,, > Vd,, is favorable but then its value is too small. Furthermore, pMOST can take twice as large channel field as nMOST before breakdown. The lucky electron model discussed earlier for the nMOST has also been used to model the gate current in pMOST's [24]. Since the source of hot electrons resulting in the gate current in pMOST is from impact ionization process which also produces substrate current I,, the pMOST gate current Fig. 8.10 Gate Circles are current Ig as a function of Vgs at different Vas for pMOST. Circles are experimental points 382 8 Modeling Hot-Carrier Effects can be expressed as and is obtained by replacing I, in Eq. (8.29) by I,. The pMOST gate current calculated using Eq. (8.30) is shown in Figure 8.10 as continuous lines, circules are measured data. The reasonable agreement between the model and data validates Eq. (8.30). 8.3 Correlation of Gate and Substrate Current Since the hot electrons responsible for the gate current and those responsible for the substrate current are heated by the same field, it is expected that the two currents will be correlated [34,35]. We can write Eq. (8.1 1) as (8.31) The above equation simply rewrites Bi = QJl, where A is the hot-electron mean free path. In analogy with Qb,Qi can be interpreted as the energy that an hot electron must have in order to create an electron-hole pair through impact ionization, and exp( - is the probability that an electron travel a distance d = Qi/&, to gain energy qQi or more without 1, /Id Fig. 8.11 Gate current I, against substrate current I, (both normalized to source current) for constant values of V,, - V,,, and therefore of &ox. (After Tam et al. [23]) 8.4 Mechanism of MOSFET Degradation 383 suffering collision. Eliminating &m from the exponential term in Eq. (8.29a) and (8.31) we get A= (?) I . (8.32) Such a power law relationship is indeed observed as shown in Figure 8.11. The slope of ln(I,/Id) versus ln(Ih/Id) gives the quantity cDh/BiA. Since B, and J. are independent of oxide field the slope can be used to find @h as a function of €ox. @b/B,1 Id 8.4 Mechanism of MOSFET Degradation The hot-carrier effects result from large electric field in the channel (parti- cularly near the drain end), which causes damage to the gate oxide (by charge trapping in the oxide) and/or to the Si-SiO, interface (by generating interface states). This leads to degradation of the n-channel MOSFET current drive capability and affects parameters such as the threshold voltage Vth, the linear region transconductance gm, the subthreshold slope S, and the satura- tion region drive current Idsat. Whether carrier (electron/hole) trapping or interface generation is primarily responsible for the degradation is still debated. But usually a net negative charge density is observed after long time stressing as is evidenced by a threshold voltage (VJ increase in nMOST's. Figure 8.12 shows typical linear region I,, - V,, characteristics, before and after stressing, which results in changes in vh and the peak transconductance gm (slope of the linear portion of the curve) [6]. The device was a 100/2 nMOST with gate oxide thickness to, = 358 A; and was stressed at V,, = 6 V, V,, = 7.5 V for 90 minute^.^ Notice that the drain current reduces after stressing and that the post-stress I-V characteristics are not symmetrical with respect to the source/drain terminal because the damage is localized at the drain end. This asymmetry is small in the linear region and is much larger in the saturation region. This can be seen from Figure 8.13 which shows typical I,, - V,, characteristics for a nMOST (L = 1.2 pm, to, = 200 A) before and after stress [24]. From this figure it is evident that the drain current reduction in saturation is much more severe in the reverse mode compared to the forward mode. Thus, device parameters change if the roles Note that device stressing is done at accelerated voltages rather than at the normal operating voltages. The underlying philosophy is that a phenomenon which occurs over a short period under the action of accelerating stresses is indicative of a similar phenomenon which will occur over a much longer period when the device is operating normally. Accelerated stressing is necessary to study degradation in a reasonably short time. 384 8 Modeling Hot-Carrier Effects 11' I 'I' I' I1 vss (V) Fig. 8.12 Degradation of nMOST linear region characteristics due to hot carrier injection before and after stress. (After Hu et al. [6]) "'"0.0 1.0 2.0 3.0 L-0 5.0 DRAIN VOLTAGE, V,, (V) Fig. 8.13 I,, - V,, characteristics of a nMOST (L = 1.2pm and to, = 200@ before and after stress. Stress voltages V,, = 7.5 V and V,, = 3 V. Stress time 5 min. (After Ong et al. [24]) of source and drain are reversed after stressing, a condition that occurs in transfer gates. An example of the degradation of a nMOST (L = 0.77 pm) on a log-log scale is shown in Figure 8.14 [40]. Here Agm = gm(0) - gm(t) is the difference between the device transconductance at times 0 and t. The devices are stressed at VgS = 3 V and V,, = 7 V that corresponds to stress- ing under peak substrate current condition. The classical interpretation of the device degradation in n-channel devices has been that only hot electrons can be injected into the gate oxide. How- 8.4 Mechanism of MOSFET Degradation 385 1 .o n MOST h 0 v E E zs, ," 0.1 a 0.01 103 104 105 TIME (sec) Fig. 8.14 The degradation of n-channel gm at different temperatures. (After Yao et al. [40]) ever, recent studies show that hot hole injection is also possible [29]-[30]. These holes are produced by impact ionization and accelerated by the channel field. This hole injection into the oxide is referred to as hole current and is usually very small, but it may have significant role in the degradation of the device characteristics especially when V,, 5 VdJ2 [41]. In fact, holes need not even overcome the barrier but their field assisted tunneling is adequate to cause serious damage to Si-SiO, interface. This is because once holes are injected into the oxide, they are more likely to get trapped than the electrons; the trapping efficiency of holes being close to 1, while for electrons it is less than The hot-carrier effect involves the generation, injection and trapping of carriers in the gate oxide. Currier injection is a localized phenomenon; it takes place over only a fraction of the total length of the channel. Four kinds of hot-carrier generation/injection mechanism have been reported for nMOST [25], [29], [37]. These are (a) Channel Hot Electrons (CHE) which are heated up in the channel particularly near the drain end with the MOSFET operated at V,, = V,,, called the lucky electrons. As shown in Figure 8.15a, lucky electrons are those flowing from source to drain gaining sufficient energy to surmount the Si-SiO, barrier without suffering an energy loosing collision in the channel, and thus move into the gate oxide resulting in the so called gate current I,. This injection of hot electrons into the oxide is referred to as channel hot electron (CHE) injection [37]. The gate currents shown in Figures 8.5- 8.6 are due to CHE injection. [...]... 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Mechanism of MOSFET Degradation 387 1 0-9 , 1 V& -7 v 1 0-1 0 ~~ L -0 .52 - 9 1 0-1 1 tox -1 051 - 0, n MOST z W u 3 0 1 0-1 4 +- 1 0-1 2 u: 1 0-1 3 Q 1 0-1 5 -~ c7 lg. A - - 0 - 0.0 2.5 GATE VOLTAGE,-Vg, (V) Fig. 8.9 Gate and substrate currents I, and I,, respectively, as a function of gate voltage V,, for different drain voltage V,, for. FZ 0. 5-0 .7 for devices with to, = 6 8-2 00 8, and L = 0.3 5-2 pm. On the other hand A, which represents the magnitude of degradation, is strongly dependent on Vd, [A K exp( - l/vds)].