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Cấu trúc

  • Course contents

  • Design of Combinatorial Circuits

  • Slide 3

  • Slide 4

  • Karnaugh map

  • Slide 6

  • Slide 7

  • Slide 8

  • Slide 9

  • Slide 10

  • Slide 11

  • Slide 12

  • Slide 13

  • Slide 14

  • Slide 15

  • Slide 16

  • Minimization with the Karnaugh map

  • Slide 18

  • Slide 19

  • Slide 20

  • Slide 21

  • Slide 22

  • Slide 23

  • Slide 24

  • Slide 25

  • Slide 26

  • Slide 27

  • Slide 28

  • Slide 29

  • Slide 30

  • Slide 31

  • Slide 32

  • Slide 33

  • Slide 34

  • Slide 35

  • Don’t care conditions

  • Slide 37

  • Slide 38

  • Slide 39

  • Slide 40

  • Slide 41

  • Slide 42

  • Slide 43

  • Slide 44

  • Slide 45

  • Slide 46

  • Slide 47

  • Slide 48

  • Slide 49

  • Slide 50

  • Slide 51

  • Quine-McCluskey

  • Slide 53

  • Slide 54

  • Technology Mapping: Gate Arrays

  • Slide 56

  • Slide 57

  • Slide 58

  • Slide 59

  • Slide 60

  • Slide 61

  • Slide 62

  • Slide 63

  • Slide 64

  • Technology Mapping: Custom Library

  • Slide 66

  • Slide 67

  • Slide 68

  • Slide 69

  • Technology Mapping: PLA

  • Slide 71

  • Technology Mapping: FPGA

  • Technology mapping: FPGA

  • Slide 74

  • Correct timing behavior: Hazard-free design

  • Slide 76

  • Slide 77

  • Slide 78

  • Slide 79

  • Slide 80

  • Slide 81

  • Slide 82

  • Ripple-carry adders

  • Slide 84

  • Slide 85

  • Slide 86

  • Slide 87

  • Carry-look-ahead adders

  • Slide 89

  • Adder-subtractors

  • Slide 91

  • Multipliers

  • Slide 93

  • Slide 94

  • Slide 95

  • Logic units

  • Slide 97

  • Slide 98

  • Slide 99

  • Arithmetic-logic units

  • Slide 101

  • Slide 102

  • Slide 103

  • Slide 104

  • Slide 105

  • Slide 106

  • Slide 107

  • Slide 108

  • Decoders

  • Slide 110

  • Slide 111

  • Selectors

  • Slide 113

  • Slide 114

  • Slide 115

  • Buses

  • Slide 117

  • Slide 118

  • Priority encoders

  • Slide 120

  • Slide 121

  • Slide 122

  • Magnitude comparators

  • Slide 124

  • Slide 125

  • Slide 126

  • Slide 127

  • Shifters and rotators

  • Slide 129

  • Slide 130

  • Slide 131

Nội dung

2/1 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Course contents • Digital design  Combinatorial circuits: without status • Sequential circuits: with status • FSMD design: hardwired processors • Language based HW design: VHDL 2/2 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Design of Combinatorial Circuits • Minimization of Boolean functions • Technology mapping • Correct timing behavior • Basic RTL building blocks (Adder, ALU, MUX, …) 2/3 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Design of Combinatorial Circuits • Minimization of Boolean functions  Karnaugh map  Minimization with the Karnaugh map  Don’t care conditions  Quine-McCluskey • Technology mapping • Correct timing behavior • Basic RTL building blocks (Adder, ALU, MUX, …) 2/4 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Design of Combinatorial Circuits • Minimization of Boolean functions  Karnaugh map  Minimization with the Karnaugh map  Don’t care conditions  Quine-McCluskey • Technology mapping • Correct timing behavior • Basic RTL building blocks (Adder, ALU, MUX, …) 2/5 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Karnaugh map • Motivation:  Assume: F=xy’z+xy’z’  Cost = Σ(fan-in) complete circuit = (2)+(3)+(3)+(2) = 10  Delay  Assume: relative gate delay NAND or NOR or NOT = 0.6 + fan-in * 0.4  Delay = Σ(gate-delay) critical path = 1 + (1.8+1) + (1.4+1) = 6.2 x y z F=xy’z+xy’z’ 2/6 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Karnaugh map • Motivation:  F=xy’z+xy’z’ =xy’(z+z’) =xy’ The value of z hence does not matter  Cost = Σ(fan-in) complete circuit = (1+2) = 3 i.o. 10  Delay  Assume: relative gate delay NAND or NOR or NOT = 0.6 + fan-in * 0.4  Delay = Σ(gate-delay) critical path = 1 + (1.4+1) = 3.4 i.o. 6.2 x y z F 2/7 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Karnaugh map • Minimization via manipulation of Boolean expressions is clumsy: no method exists to select the theorems such that we are sure to obtain the minimum cost • Is it possible to see in the truth table which input value does not matter? x y z F 0 0 0 0 - 0 0 1 0 - 0 1 0 0 - 0 1 1 0 - 1 0 0 1 xy’z’ 1 0 1 1 xy’z 1 1 0 0 - 1 1 1 0 - We indeed see easily that the value of F equals 1 for x=1 and y=0 irrespective of the value of z We however see this easily only for z, since only for z the lines z=0 and z=1 for equal x and y are consecutive 2/8 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Karnaugh map • A Karnaugh map contains the same information as a truth table (each square is a minterm), but… • neighboring squares differ only in the value of 1 variable!! x’ x x 0 1 x’y’ x’y xy’ xy x 0 1 y 0 1 x’y’z’ x’y’z xy’z’ xy’z x 0 1 yz 00 01 x’yz x’yz’ xyz xyz’ 11 10 x y z x’z (y does not matter) x’y’z x’yz xy’z’ xyz’ xz’ (y does not matter) xy’z’ xy’z xy’ (z does not matter) 2/9 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Karnaugh map m 0 m 1 x 0 1 m 0 m 1 m 2 m 3 x 0 1 y 0 1 0 1 4 5 x 0 1 yz 00 01 3 2 7 6 11 10 x y z 2/10 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 Karnaugh map 0 1 4 5 xy 00 01 zw 00 01 3 2 7 6 11 10 x z w 12 13 8 9 15 14 11 10 11 10 y x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 1 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 x y z w F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 Fill out from truth table

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