Hardware software co design implement two bit full adder on zybo zynq 7000 board by using verilog

The FPGA fabric can be programmed using the Verilog language, which is a popular hardware description language used for digital circuit design.A Full Adder circuit consists of three inpu

HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION

FACULTY OF HIGH QUALITY TRANING



Hardware/Software Co-design Implement Two-bit Full Adder on ZYBO ZYNQ-7000 board by

using Verilog.

Advisor: Phan Văn Ca, Assoc Prof

Trần Nguyễn Anh Khoa 20119188

Ho Chi Minh City, March 2023

Contents

Overview 3

1 Introduction 4

2 Methodology 4

2.1 Zynq-7000 SoC 4

2.2 Vivado 7

2.3 2-bit Full Adder 8

2.4 Code for module Full Adder in Verilog 11

2.5 Code for module 2 bit Full Adder in Verilog 12

3 Result from Simulation 13

4 Conclusion 14

5 References 14

The Zybo Zynq-7000 board is a powerful development platform that combines a high-performance ARM-based processor with programmable logic The board features a Xilinx Zynq-7000 All-Programmable System-on-Chip (SoC) that includes a dual-core ARM Cortex-A9 processor and an FPGA fabric The FPGA fabric can be programmed using the Verilog language, which is a popular hardware description language used for digital circuit design

A Full Adder circuit consists of three inputs: A, B, and Cin, and two outputs: S and Cout The output S represents the sum of the three inputs, while the output Cout represents the carry-out To implement a 2-bit Full Adder circuit, we need to cascade two Full Adder circuits together The first Full Adder takes inputs A0, B0, and Cin, and produces outputs S0 and C1 The second Full Adder takes inputs A1, B1, and C1, and produces outputs S1 and Cout To implement this circuit on the Zybo Zynq-7000 board, we will use the Verilog language Verilog is a hardware description language that allows us to describe the behavior of digital circuits We will use the Xilinx Vivado development environment to create a project, write the Verilog code, and simulate and synthesize the design We will also generate a bitstream file that can be programmed onto the FPGA fabric of the Zybo Zynq-7000 board

In the next sections, we will discuss the steps involved in implementing a 2-bit Full Adder circuit on the Zybo Zynq-7000 board using Verilog

1 Introduction

The Full Adder is a digital circuit that can perform the addition of three binary digits:

A, B, and Carry-in (Cin) to produce a Sum (S) and a Carry-out (Cout) Full Adder circuits are essential building blocks of digital systems and are widely used in arithmetic circuits, such as calculators, digital signal processors, and microprocessors

In this essay, we will discuss the implementation of a 2-bit Full Adder circuit on the Zybo Zynq-7000 board using the Verilog hardware description language We will explore the basic principles of Full Adder circuits, the features of the Zybo Zynq-7000 board, and the steps involved in implementing the circuit using Verilog

2 Methodology

2.1 Zynq-7000 SoC

The Zynq-7000 family offers the flexibility and scalability of an FPGA, while providing performance, power, and ease of use

typically associated with ASIC and ASSPs The range of devices in the Zynq-7000 family allows designers to target

cost-sensitive as well as high-performance applications from a single platform using industry-standard tools While each

device in the Zynq-7000 family contains the same PS, the PL and I/O resources vary between the devices As a result, the

Zynq-7000 and Zynq-7000S SoCs are able to serve a wide range of applications including:

• Automotive driver assistance, driver information, and infotainment

• Broadcast camera

• Industrial motor control, industrial networking, and machine vision

• IP and Smart camera

• LTE radio and baseband

• Medical diagnostics and imaging

• Multifunction printers

• Video and night vision equipment

The Zynq-7000 architecture enables implementation of custom logic in the PL and custom software in the PS It allows for

the realization of unique and differentiated system functions The integration of the PS with the PL allows levels of

performance that two-chip solutions (e.g., an ASSP with an FPGA) cannot match due

to their limited I/O bandwidth, latency,

and power budgets

Xilinx offers a large number of soft IP for the Zynq-7000 family Stand-alone and Linux device drivers are available for the

peripherals in the PS and the PL The Vivado® Design Suite development

environment enables a rapid product

development for software, hardware, and systems engineers Adoption of the ARM-based PS also brings a broad range of

third-party tools and IP providers in combination with Xilinx’s existing PL ecosystem The inclusion of an application processor enables high-level operating system support, e.g., Linux Other standard operating

systems used with the Cortex-A9 processor are also available for the Zynq-7000 family

The PS and the PL are on separate power domains, enabling the user of these devices

to power down the PL for power

management if required The processors in the PS always boot first, allowing a software centric approach for PL

configuration PL configuration is managed by software running on the CPU, so it boots similar to an ASSP

Figure 1 Architectural Overview Figure 1 illustrates the functional blocks of the Zynq-7000 SoC The PS and the PL are on separate power domains, enabling the user of these devices to power down the

PL for power management if required

The ZYBO (ZYnq BOard) is a feature-rich, ready-to-use, entry-level embedded software and digital circuit development platform built around the smallest member of the Xilinx Zynq-7000 family, the Z-7010 The Z-7010 is based on the Xilinx All Programmable System-on-Chip (AP SoC) architecture, which tightly integrates a dual-core ARM Cortex-A9 processor with Xilinx 7-series Field Programmable Gate Array (FPGA) logic When coupled with the rich set of multimedia and connectivity peripherals available on the ZYBO, the Zynq Z-7010 can host a whole system design The on-board memories, video and audio I/O, dual-role USB, Ethernet, and SD slot will have your design up-and-ready with no additional hardware needed Additionally, six Pmod ports are available to put any design on an easy growth path

Figure 2 DIGILENT ZYBO Zynq-7000

2.2 Vivado

Vivado is a software tool suite from Xilinx that is used for designing, synthesizing, and analyzing digital circuits for FPGA (Field Programmable Gate Array) and SoC (System-on-Chip) devices It provides a graphical user interface (GUI) for designing digital circuits and includes various tools for debugging, simulating, and

implementing designs on Xilinx FPGA and SoC devices Vivado is widely used in industries such as telecommunications, aerospace, defense, and automotive for developing digital circuits It supports a wide range of digital design languages such as VHDL, Verilog, and SystemVerilog, and includes advanced features such as high-level

synthesis (HLS) and partial reconfiguration Overall, Vivado is a powerful tool suite for designing complex digital circuits and is used by engineers and designers in many industries

2.3 2-bit Full Adder

 Full Adder is the adder that adds three inputs and produces two outputs The first two inputs are A and B and the third input is an input carry as C-IN The output carry is designated as C-OUT and the normal output is designated as S which is SUM A full adder logic is designed in such a manner that can take eight inputs together to create a byte-wide adder and cascade the carry bit from one adder to another we use a full adder because when a carry-in bit is available, another 1-bit adder must be used since a 1-bit half-adder does not take a carry-in bit A 1-bit full adder adds three operands and generates 2-bit results

Figure 3 Block diagram of Full Adder

Figure 4 Truth Table of Full Adder

 To design a 2-bit full adder, we can use two 1-bit full adders, one for the least significant bit (LSB) and one for the most significant bit (MSB) The input bits

of the two 1-bit full adders are the corresponding bits of the two 2-bit binary numbers being added, and the carry-in bit of the LSB full adder is the carry-in bit of the 2-bit full adder The output bits of the two 1-bit full adders are the corresponding bits of the 2-bit binary sum, and the carry-out bit of the MSB full adder is the carry-out bit of the 2-bit full adder The carry-out bit of the LSB full adder is connected to the carry-in input of the MSB full adder The

carry-out bit of the MSB full adder is the carry-out bit of the 2-bit full adder To combine the two carry-out bits, we use an OR gate The output of the OR gate

is the final carry-out bit of the 2-bit full adder Here's a schematic diagram of a 2-bit full adder:

Figure 5 Block diagram of 2-bit full adder circuit

Figure 6 Truth Table of 2 bit Full Adder

2.4 Code for module Full Adder in Verilog

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer:

//

// Create Date: 03/10/2023 04:03:27 PM

// Design Name:

// Module Name: fulladder

// Project Name:

// Target Devices:

// Tool Versions:

// Description:

//

// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

//////////////////////////////////////////////////////////////////////////////////

module fulladder(A,B,C,SUM,COUT

);

input A,B,C;

output SUM,COUT;

assign SUM = A^B^C;

assign COUT = (A&B)|(B&C)|(C&A);

endmodule

2.5 Code for module 2 bit Full Adder in Verilog

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer:

//

// Create Date: 03/10/2023 05:50:14 PM

// Design Name:

// Module Name: CRA2BITS

// Project Name:

// Target Devices:

// Tool Versions:

// Description:

//

// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

module CRA2BITS(a,b,c,sum,cout

);

input [1:0]a,b;

input c;

output [1:0]sum;

output cout;

wire c1;

fulladder uut(a[0],b[0],c,sum[0],c1);

fulladder uut1(a[1],b[1],c1,sum[1],cout);

endmodule

3 Result from Simulation

After simulating on Vivado, we got the signal waveforms illustrate all the state similar

to the Truth Table

Figure 7 Simulation 1

Figure 8 Simulation 2

Figure 9 Block Diagram taken from Vivado

4 Conclusion

In conclusion, implementing a two-bit full adder on the ZYBO ZYNQ-7000 board using Verilog is a complex yet rewarding task Through this project, we have learned how to design and simulate digital circuits using Verilog, and how to program and deploy them on a FPGA board We have also gained a deeper understanding of how a full adder works, and how it can be used to perform arithmetic operations on binary numbers

This project has also taught us the importance of testing and debugging in the design process, as even small errors in the Verilog code can lead to unexpected behavior in the circuit By carefully analyzing and correcting these errors, we were able to ensure that our two-bit full adder performed as expected

Overall, this project has been a valuable learning experience, and has given us the skills and knowledge necessary to design and implement more complex digital circuits

in the future We look forward to continuing to explore the world of digital design and FPGA programming, and to using these skills to solve real-world engineering problems

5 References

"Digital Design and Computer Architecture" by David Harris and Sarah Harris

"Verilog HDL: A Guide to Digital Design and Synthesis" by Samir Palnitkar

"Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL"

by Mohammed Ferdjallah

"Digital Design: With an Introduction to Verilog HDL" by M Morris Mano and Michael D Ciletti

"Zybo Z7-10 Reference Manual" by Digilent

"Zynq-7000 All Programmable SoC: Embedded Design Tutorial" by Xilinx

"FPGA Prototyping by Verilog Examples: Xilinx Spartan-3 Version" by Pong P Chu

"Vivado Design Suite User Guide" by Xilinx

"Vivado Design Suite Tutorial" by Xilinx