xu ly tin hieu so fpga hoang trang dsp fpga htrang chapter4 2slides per page cuuduongthancong com

4/2/2013 ĐẠI HỌC QUỐC GIA TP.HỒ CHÍ MINH TRƯỜNG ĐẠI HỌC BÁCH KHOA KHOA ĐIỆN-ĐIỆN TỬ BỘ MÔN KỸ THUẬT ĐIỆN TỬ XỬ LÝ TÍN HiỆU SỐ VỚI FPGA c om Chaper 4: Retiming (Tái định thì) GV: Hồng Trang Email: hoangtrang@hcmut.edu.vn mr.hoangtrang@gmail.com co ng Thank to: thầy Hồ Trung Mỹ Slide: from text book of Parhi TP.Hồ Chí Minh 01/2013 ng th an du o Thuật ngữ cu u English Pipelining Cutset Transposed SFG Data broadcast Parallel processing block processing communication bound BM Điện Tử-DSP-FPGA-chapter4 Vietnamses tạo đường ống tập cắt SFG chuyển vị truyền liệu khắp nơi, phát tán liệu xử lý song song xử lý khối giới hạn truyền thông thời gian trễ truyền thơng Hồng Trang 01/2013 CuuDuongThanCong.com https://fb.com/tailieudientucntt 4/2/2013 Outline • Retiming Introduction • Preliminaries c om – Quantitative Description – Properties of Retiming – Solving systems of inequalities • Special Cases – Cutset Retiming – Pipelining ng • Uses of Retiming Hoàng Trang 01/2013 ng th an BM Điện Tử-DSP-FPGA-chapter4 co – Retiming for Clock Period Minimization – Retiming for Register Minimization du o 4.1 INTRODUCTION cu u • Retiming is a transformation technique used to change the locations of delay elements in a circuit without affecting the input/output characteristics of the circuit • For example, consider the IIR filters in Fig 4.1(a) & (b) Although the filters in Fig 4.1(a) and Fig 4.1(b) have delays at different locations, these filters have the same input/output characteristics These filters can be derived from one another using retiming BM Điện Tử-DSP-FPGA-chapter4 Hoàng Trang 01/2013 CuuDuongThanCong.com https://fb.com/tailieudientucntt 4/2/2013 The filter in Fig 4.1(b) is described by Hoàng Trang 01/2013 ng th an BM Điện Tử-DSP-FPGA-chapter4 co ng The filter in Fig 4.1(a) is described by c om Example: du o Applications of Retiming u • Retiming has many applications in synchronous circuit design These applications include cu – – – – reducing the clock period of the circuit, reducing the number of registers in the circuit, reducing the power consumption of the circuit, and logic synthesis BM Điện Tử-DSP-FPGA-chapter4 Hoàng Trang 01/2013 CuuDuongThanCong.com https://fb.com/tailieudientucntt 4/2/2013 Applications of Retiming (cont’d) • Retiming can be used to increase the clock rate of a circuit by reducing the computation time of the critical path • For example: c om – The critical path of the filter in Fig 4.1(a) = TM +TA = u.t => this filter cannot be clocked with a clock period of less than u.t – The retimed filter in Fig 4.1(b) = TA+TA = u.t => this filter can be clocked with a clock period of u.t – By retiming the filter in Fig 4.1(a) to obtain the filter in Fig 4.1(b), the clock period has been reduced from u.t to u.t., or by 33% Hoàng Trang 01/2013 cu u du o ng th an BM Điện Tử-DSP-FPGA-chapter4 co ng • Retiming can be used to decrease the number of registers in a circuit The filter in Fig 4.1 (a) uses registers while the filter in Fig 4.1 (b) uses registers • Since retiming can affect the clock period and the number of registers, it is sometimes desirable to take both of these parameters into account BM Điện Tử-DSP-FPGA-chapter4 Hoàng Trang 01/2013 CuuDuongThanCong.com https://fb.com/tailieudientucntt 4/2/2013 Hoàng Trang 01/2013 Retiming du o ng th an BM Điện Tử-DSP-FPGA-chapter4 co ng c om Example: cu u • Generalization of Pipelining • Pipelining is Equivalent to Introducing Many delays at the Input followed by Retiming BM Điện Tử-DSP-FPGA-chapter4 Hoàng Trang 01/2013 10 CuuDuongThanCong.com https://fb.com/tailieudientucntt 4/2/2013 4.2 DEFINITIONS AND PROPERTIES 4.2.1 Quantitative Description of Retiming • Retiming maps circuit G to a retimed circuit Gr • Retiming solution characterized by a value r(V) for each node V in graph c om – Let w(e) denote weight of edge e of graph G, and wr(e) denote weight of edge e of graph Gr – Weight of edge rom U e V in the retimed graph is computed from weight of edge in original graph using wr(e) = w(e) + r(V) - r(U) co ng • Retiming solution is feasible if wr(e) >= for all edges 01/2013 Hoàng Trang 11 ng th an BM Điện Tử-DSP-FPGA-chapter4 Transfer delay through a node in DFG: u • du o Node Retiming cu 3D • • Retiming equation: v subject to wr(e) ≥ r(v) = v 2D e u D 2D v D • • 3D r(v) = # of delays transferred from out-going edges to incoming edges of node v w(e) = # of delays on edge e wr(e) = # of delays on edge e after retiming • wr (e) = w(e) + r (v) − r (u ) Let p be a path from v0 to vk v0 e0 v1 e1 k −1 ek p vk then wr ( p ) = ∑ wr (ei ) i =0 k −1 = ∑ ( w(ei ) + r (vi +1 ) − r (vi ) ) i =0 = w( p ) + r (vk ) − r (v0 ) CuuDuongThanCong.com https://fb.com/tailieudientucntt 4/2/2013 Invariant Properties Hoàng Trang 01/2013 ng cu u du o Example: th an BM Điện Tử-DSP-FPGA-chapter4 co ng c om Retiming does NOT change the total number of delays for each cycle Retiming does not change loop bound or iteration bound of the DFG If the retiming values of every node v in a DFG G are added to a constant integer j, the retimed graph Gr will not be affected That is, the weights (# of delays) of the retimed graph will remain the same BM Điện Tử-DSP-FPGA-chapter4 Hoàng Trang 01/2013 14 CuuDuongThanCong.com https://fb.com/tailieudientucntt 4/2/2013 T∞ = max {(1+2+1)/2, (1+2+1)/3} = Cr Path Delay = max{2,2,1+1} = t.u ng th an co T∞ = max {(1+2+1)/2, (1+2+1)/3} = Cr Path delay = 2+1 = t.u ng c om DFG Illustration of the Example du o 4.2.2 Properties of Retiming cu u • Weight of a path from node to node k is number of delays between those nodes • Computation time of a path between node to node k is the sum of computation times (adders, etc.) of each of the nodes • Properties: k −1 w( p ) = ∑ w(ei ) i =0 k t ( p ) = ∑ t (Vi ) i =0 – Retiming does not change number of delays in a cycle – Retiming does not alter iteration bound of DFG – Adding a constant value j to the retiming value of each node does not change the mapping from G to Gr BM Điện Tử-DSP-FPGA-chapter4 Hoàng Trang 01/2013 CuuDuongThanCong.com https://fb.com/tailieudientucntt Hoàng Trang 01/2013 17 ng th an BM Điện Tử-DSP-FPGA-chapter4 co ng c om 4/2/2013 4.3 Solving Systems of Inequalities du o • Shortest path algorithms (Appendix A of Parhi book) – Bellman-Ford – Floyd-Warshall cu u • Given a set of M inequalities and N variables, where each inequality has the form ri – rj 0, hence there is at least one negative cycle 10 CuuDuongThanCong.com https://fb.com/tailieudientucntt Hoàng Trang 01/2013 27 01/2013 28 cu u du o ng th an BM Điện Tử-DSP-FPGA-chapter4 co ng c om 4/2/2013 BM Điện Tử-DSP-FPGA-chapter4 Hoàng Trang 14 CuuDuongThanCong.com https://fb.com/tailieudientucntt Hoàng Trang 01/2013 29 01/2013 30 cu u du o ng th an BM Điện Tử-DSP-FPGA-chapter4 co ng c om 4/2/2013 BM Điện Tử-DSP-FPGA-chapter4 Hoàng Trang 15 CuuDuongThanCong.com https://fb.com/tailieudientucntt Hoàng Trang 01/2013 31 01/2013 32 cu u du o ng th an BM Điện Tử-DSP-FPGA-chapter4 co ng c om 4/2/2013 BM Điện Tử-DSP-FPGA-chapter4 Hoàng Trang 16 CuuDuongThanCong.com https://fb.com/tailieudientucntt co ng c om 4/2/2013 Hoàng Trang 01/2013 33 ng th an BM Điện Tử-DSP-FPGA-chapter4 cu u du o Pipelining (a) (b) (c) Fig 4.6 (a) The unretimed DFG with a cutset shown as a dashed line (b) The graphs G1 and G2 formed by removing the edges in the cutset (c) The graph obtained by cutset retiming with k = BM Điện Tử-DSP-FPGA-chapter4 Hoàng Trang 01/2013 34 17 CuuDuongThanCong.com https://fb.com/tailieudientucntt 4/2/2013 Hoàng Trang 01/2013 35 th an BM Điện Tử-DSP-FPGA-chapter4 co ng c om Lattice Filter ng N‐Slow Down cu u du o • Cutset retiming is often used in combination with slow-down • The procedure is to first replace each delay in the DFG with N delays to create an N -slow version of the DFG and then to perform cutset retiming on the N –slow DFG BM Điện Tử-DSP-FPGA-chapter4 Hoàng Trang 01/2013 36 18 CuuDuongThanCong.com https://fb.com/tailieudientucntt 4/2/2013 Time Scaling (Slow Down) y(3) y(2) y(1) + D × y(3) y(2) y(1) + 2D × cu u du o ng th an co ng c om • Transform each delay element x(3) x(2) x(1) (register) D to ND and reduce the sample frequency by N fold will slow down the computation N times • During slow down, the x(3) x(2) x(1) processor clock cycle time remains unchanged Only the sampling cycle time increased • Provides opportunity for retiming, and interleaving BM Điện Tử-DSP-FPGA-chapter4 Hoàng Trang 01/2013 38 19 CuuDuongThanCong.com https://fb.com/tailieudientucntt Hoàng Trang 39 01/2013 cu u du o ng th an BM Điện Tử-DSP-FPGA-chapter4 co ng c om 4/2/2013 BM Điện Tử-DSP-FPGA-chapter4 Hoàng Trang 01/2013 40 20 CuuDuongThanCong.com https://fb.com/tailieudientucntt Hoàng Trang 01/2013 41 01/2013 42 cu u du o ng th an BM Điện Tử-DSP-FPGA-chapter4 co ng c om 4/2/2013 BM Điện Tử-DSP-FPGA-chapter4 Hoàng Trang 21 CuuDuongThanCong.com https://fb.com/tailieudientucntt Hoàng Trang 01/2013 43 01/2013 44 cu u du o ng th an BM Điện Tử-DSP-FPGA-chapter4 co ng c om 4/2/2013 BM Điện Tử-DSP-FPGA-chapter4 Hoàng Trang 22 CuuDuongThanCong.com https://fb.com/tailieudientucntt 4/2/2013 Hoàng Trang 01/2013 45 ng th an BM Điện Tử-DSP-FPGA-chapter4 co ng c om Retiming of N‐Slow Down with Cutset Retiming du o 4.4.2 Retiming for Clock Period Minimization u • In previous lectures, we have learned to calculate the iteration bound of a DFG cu – Iteration bound determines the minimum clock period of a recursive DFG • Retiming for clock period minimization is the tool used to cause a recursive DFG to have a clock period to equal the iteration bound BM Điện Tử-DSP-FPGA-chapter4 Hoàng Trang 01/2013 23 CuuDuongThanCong.com https://fb.com/tailieudientucntt 4/2/2013 Retiming for Clock Period Minimization cont’d • Minimum feasible clock period is computation time of the critical path, which is the path with the longest computation time among all paths with no delays Minimum clock period is Φ(G) Φ (G ) = max{t ( p ) : w( p ) = 0} c om • Want to find a retiming solution Φ(Gr0)