xu ly tin hieu so fpga hoang trang dsp fpga htrang chapter1 2slides per page cuuduongthancong com

1/26/2013 ĐẠI HỌC QUỐC GIA TP.HỒ CHÍ MINH TRƯỜNG ĐẠI HỌC BÁCH KHOA KHOA ĐIỆN-ĐIỆN TỬ BỘ MÔN KỸ THUẬT ĐIỆN TỬ XỬ LÝ TÍN HiỆU SỐ VỚI FPGA c om Chaper 1: Introduction ng GV: Hoàng Trang Email: hoangtrang@hcmut.edu.vn mr.hoangtrang@gmail.com co Thank to: thầy Hồ Trung Mỹ TP.Hồ Chí Minh 01/2013 ng th an du o Content cu u + Tổng quan môn học + Phương pháp luận thiết kế giải pháp FPGA + Thiết kế giải thuật DSP với FPGA BM Điện Tử-DSP-FPGA-chapter1 Hoàng Trang 01/2013 CuuDuongThanCong.com https://fb.com/tailieudientucntt 1/26/2013 Outline: how to evaluate? How to evaluate? c om Quiz: 10% Homework (textbook) : 10% (team work) Project: 20% (team work) Mid-term: 20% Final exam: 40% Textbook: ng “VLSI Digital Signal Processing: Design and Implementation” Hoàng Trang 01/2013 du o ng th an BM Điện Tử-DSP-FPGA-chapter1 co Keshab K Parhi Outline cu u Hardware • DSP Systems, A/D and D/A converters • FPGA for signal processing (Altera, Xilinx), • Application domain specific instruction set processors • SoC, DSP Multiprocessors • Signal processing arithmetic units BM Điện Tử-DSP-FPGA-chapter1 Algorithm design and transformations • Scheduling, Resource Allocation, Synthesis • Finite-word length effects • Algorithmic transformations • FIR filter design • FFT design • IIR filter design • Adaptive filter design Hồng Trang 01/2013 CuuDuongThanCong.com https://fb.com/tailieudientucntt 1/26/2013 Course Conduct Hoàng Trang 01/2013 ng th an BM Điện Tử-DSP-FPGA-chapter1 co ng c om • Course notes will be posted on the course web page • Assignments with solutions will be provided and will not be graded • The exam will be prepared based on lecture slides, references and assignments du o Course Objectives … To cu u • Understand tradeoffs in implementing DSP algorithms • Know basic DSP architectures • Know some reduced complexity strategies for algorithms mainly on FPGA • Know about commercial DSP solution • Know and understand system-level design tools • Understand research topics related to algorithmic modifications and algorithm-architecture matching BM Điện Tử-DSP-FPGA-chapter1 Hoàng Trang 01/2013 CuuDuongThanCong.com https://fb.com/tailieudientucntt 1/26/2013 Why this course? There is the demand to derive more information per signal “More” means • Faster: Derive more information per unit time; c om – Faster hardware – Newer algorithms with fewer operations Hoàng Trang 01/2013 ng th an BM Điện Tử-DSP-FPGA-chapter1 co ng • Cheaper: Derive information at a reduced cost in processor size, weight, power consumption, or dollars; • Better: Derive higher quality information, (higher precision, finer resolution, higher SNR) du o Hardware and software elements cu u Progress in signal processing capability is the product of progress in IC devices, architectures, algorithms and mathematics BM Điện Tử-DSP-FPGA-chapter1 Hoàng Trang 01/2013 CuuDuongThanCong.com https://fb.com/tailieudientucntt 1/26/2013 Moore’s Law ng c om Predicts doubling of circuit density every 1.5 to years Hoàng Trang 01/2013 ng th an BM Điện Tử-DSP-FPGA-chapter1 co http://www.icknowledge.com/trends/uproc.html du o What is Signal Processing? • Types of processing: cu u • Ways to manipulate signal in its original medium or an abstract representation • Signal can be abstracted as functions of time or spatial coordinates – – – – – – – – – Transformation Filtering Detection Estimation Recognition and classification Coding (compression) Synthesis and reproduction Recording, archiving Analyzing, modeling 10 BM Điện Tử-DSP-FPGA-chapter1 Hoàng Trang 01/2013 10 CuuDuongThanCong.com https://fb.com/tailieudientucntt 1/26/2013 Digital Signal Processing • Signals generated via physical phenomenon are analog in that • Digital signal processing concerns processing signals using digital computers – A continuous time/space signal must be sampled to yield countable signal samples – The real-(complex) valued samples must be quantized to fit into internal word length Hoàng Trang 01/2013 11 ng th an BM Điện Tử-DSP-FPGA-chapter1 co ng c om – Their amplitudes are defined over the range of real/complex numbers – Their domains are continuous in time or space cu u du o Digital Signal Processing applications BM Điện Tử-DSP-FPGA-chapter1 Hoàng Trang 01/2013 12 CuuDuongThanCong.com https://fb.com/tailieudientucntt 1/26/2013 Signal Processing Systems Digital Signal Processing A/D D/A co ng c om The task of digital signal processing (DSP) is to process sampled signals (from A/D analog to digital converter), and provide its output to the D/A (digital to analog converter) to be transformed back to physical signals Copied from [Hu04-Slides] Design and Implementation of Signal Processing Systems: An Introduction Hoàng Trang 01/2013 13 ng th an BM Điện Tử-DSP-FPGA-chapter1 cu u du o Typical DSP Application BM Điện Tử-DSP-FPGA-chapter1 Hoàng Trang 01/2013 14 CuuDuongThanCong.com https://fb.com/tailieudientucntt 1/26/2013 Stratix DSP Development Board Nios Expansion Prototype Connector MAX 7000 Device Prototyping Area D/A Converters Mictor-Type Connectors for HP Logic Analyzers c om A/D Converters [AlteraDSP] Hoàng Trang 40-Pin Connectors for Analog Devices 01/2013 15 ng th an BM Điện Tử-DSP-FPGA-chapter1 co Texas Instruments Connectors on Underside of Board ng Analog SMA Connectors du o Example DSP Applications… COMMUNICATIONS cu u Echo Cancellation Digital PBXs Line Repeaters Modems Global Positioning Sound/Modem/Fax Cards Cellular Phones Speaker Phones Video Conferencing ATMs VOICE/SPEECH PRO AUDIO PRO Speech Recognition Speech Processing/Vocoding Speech Enhancement Text-to-Speech Voice Mail AV Editing Digital Mixers Home Theater Pro Audio CONSUMER Radar Detectors Power Tools Digital Audio / TV Music Synthesizers Toys / Games Answering Machines Digital Speakers DSP INSTRUMENTATION Spectrum Analyzers Seismic Processors Digital Oscilloscopes Mass Spectrometers INDUSTRIAL/CONTROL Robotics Numeric Control Power Line Monitors Motor/Servo Control MILITARY MEDICAL Secure Communications Sonar Processing Image Processing Radar Processing Navigation, Guidance Patient Monitoring Ultrasound Equipment Diagnostic Tools Fetal Monitors Life Support Systems Image Enhancement www.analog.com/dsp BM Điện Tử-DSP-FPGA-chapter1 Hoàng Trang 01/2013 16 CuuDuongThanCong.com https://fb.com/tailieudientucntt 1/26/2013 Implementation of DSP Systems • Platforms: • Requirements: – Native signal processing (NSP) with general purpose processors (GPP) – Real time • Processing must be done before a pre-specified deadline • Multimedia extension (MMX) instructions – Streamed numerical data – Programmable digital signal processors (PDSP) – Application-Specific Integrated Circuits (ASIC) – Field-programmable gate array (FPGA) c om • Sequential processing • Fast arithmetic processing – High throughput Hồng Trang 01/2013 17 ng th an BM Điện Tử-DSP-FPGA-chapter1 co ng • Fast data input/output • Fast manipulation of data du o How Fast is Enough for DSP? • Real time requirements: cu u – Example: data capture speed must match sampling rate Otherwise, data will be lost – Processing must be done by a specific deadline • Different throughput rates for processing different signals – – – – Throughput ∝sampling rate CD music: 44.1 kHz Speech: 8-22 kHz Video (depends on frame rate, frame size, etc.) range from 100s kHz to MHz Example: Processor clocked at 120 MHz and can perform 120MIPS + Sampling rate = 48KHz (Digital Audio Tape - DAT) number of instructions per sample = (120 x 106)/(48 x 103) = 2500 + Sampling rate = 8KHz (voice-band, telephony) number of instructions per sample = 15000 + Sampling rate = 75MHz (CIF 360x288 Video at 30 frames per second) number of instructions per sample = 1.6 BM Điện Tử-DSP-FPGA-chapter1 Hoàng Trang 01/2013 18 CuuDuongThanCong.com https://fb.com/tailieudientucntt 1/26/2013 ASIC: Application Specific ICs Hoàng Trang 01/2013 19 ng th an BM Điện Tử-DSP-FPGA-chapter1 co ng c om • Custom or semi-custom IC chip or • ASIC becomes popular due to availability of IC foundry chip sets developed for specific services Fab-less design functions houses turn innovative design • Suitable for high volume, low cost into profitable chip sets using productions CAD tools • Example: MPEG codec, 3D graphic • Design automation is a key enabling technology to chip, etc facilitate fast design cycle and shorter time to market delay du o Programmable Digital Signal Processors (PDSPs) cu u • Micro-processors designed for signal processing applications • Special hardware support for: – – – – – Multiply-and-Accumulate (MAC) ops Saturation arithmetic ops Zero-overhead loop ops Dedicated data I/O ports Complex address calculation and memory access – Real time clock and other embedded processing supports BM Điện Tử-DSP-FPGA-chapter1 • PDSPs were developed to fill a market segment between GPP and ASIC: – GPP flexible, but slow – ASIC fast, but inflexible • As VLSI technology improves, role of PDSP changed over time Hoàng Trang – Cost: design, sales, maintenance/upgrade – Performance 01/2013 20 10 CuuDuongThanCong.com https://fb.com/tailieudientucntt 1/26/2013 Arithmetic Operations for Fixed-Point Numbers Normalized fixed-point numbers Scaling all the numbers involved in computation by a factor K such that all the numbers are within the range from to Fixed-point number after normalization Addition/Subtraction n bits +/- = n bits n bits Addition/Subtraction n bits = n bits ng × co n bits Hoàng Trang n bits truncated 01/2013 13-81 ng th an BM Điện Tử-DSP-FPGA-chapter1 c om n bits du o Representation of Negative Numbers cu u Signed-magnitude numbers S Normalized magnitude Sign bit: for positive number and for negative number 2’s complementary numbers S Normalized 2’s complementary number Sign bit: for positive number and for negative number BM Điện Tử-DSP-FPGA-chapter1 Hoàng Trang 01/2013 13-82 41 CuuDuongThanCong.com https://fb.com/tailieudientucntt 1/26/2013 Floating-Point Numbers Scientific Notation 6.02 x 1023 radix (base) decimal point c om Binary Floating-Point Numbers Mantissa Hoàng Trang 01/2013 13-83 ng th an BM Điện Tử-DSP-FPGA-chapter1 radix (base) co “binary point” ng 1.0two x 2-1 du o Floating-Point Representation • Normal format: +1.xxxxxxxxxxtwo*2yyyytwo S Exponent cu u Significand S represents Sign - (1 for negative number and for positive number) Exponent represents yyyy - (It is a biased number, is is also called as excess-bias number E.g if a number A is a excess-8 coding, the real value of the number is A-8) Significand represents xxxxxxxxx (-1)S * (1 + Significand) * 2(Exponent - Bias) BM Điện Tử-DSP-FPGA-chapter1 Hoàng Trang 01/2013 13-84 42 CuuDuongThanCong.com https://fb.com/tailieudientucntt 1/26/2013 Arithmetic Operations of Floating-Point Numbers Assume number X = X M • X E Y = YM • 2YE Addition/Subtraction: X ± Y = ( X M • X E −YE ± YM ) • 2YE Where XE < YE Compute YE-XE, a fixed-point subtraction Right shift XM by YE-XE bits to obtain XM•2Xe-Ye Compute XM•2Xe-Ye±YM, a fixed-point addition or subtraction Multiplication: ng X • Y = ( X M • YM ) • X E +YE c om Compute XM•YM, a fixed-point multiplication Compute XE+YE, a fixed-point addition co Hoàng Trang 01/2013 13-85 ng th an BM Điện Tử-DSP-FPGA-chapter1 du o DSP Applications Common DSP Functions that are implemented using VLSIs Filters (FIR, IIR) cu u Fast Fourier Transform (FFT) Direct Cosine Transform (DCT) Encoder/decoder and error correction/detection functions ••••• FIR (Finite Impulse Response) Filter y[n] = a0 • x[n] + a1 • x[n − 1] + ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ + ak • x[n − k ] Y[n] is the output at nth clock cycle; X[n] is the input at nth clock cycle a0, a1, ak-1 are filter coefficients IIR (Infinite Impulse Response) Filter y[n] = a0 • x[ n] + ⋅ ⋅ ⋅ + ak • x[n − k ] + b1 • y[ n − 1] + ⋅ ⋅ ⋅ + bm • y[ n − m] BM Điện Tử-DSP-FPGA-chapter1 Hoàng Trang 01/2013 13-86 43 CuuDuongThanCong.com https://fb.com/tailieudientucntt 1/26/2013 FIR Filter Implementation Example: y[n] = a0 • x[n] + a1 • x[n − 1] + a2 • x[n − 2] + a3 • x[n − 3] Tap This is a 4-tap FIR filter Canonic form implementation: a0 D D a1 × × D × a2 a3 c om x[n] × y[n] f clk ≤ + • tadder tmult + ng + co Clock frequency + 01/2013 Hoàng Trang 13-87 ng th an BM Điện Tử-DSP-FPGA-chapter1 du o FIR Filter Implementation Pipelined implementation 1: cu u x[n] a0 D D a1 × D D D × a2 × + D + D a3 × y[n-3] D Clock frequency BM Điện Tử-DSP-FPGA-chapter1 f clk ≤ t mult D + + t adder Hoàng Trang 01/2013 13-88 44 CuuDuongThanCong.com https://fb.com/tailieudientucntt 1/26/2013 FIR Filter Implementation Pipelined implementation 2: a0 D D a1 × D × D × a2 D D × a3 D D c om x[n] y[n-3] + D f clk ≤ tmult (assume tmult > tadd) co Clock frequency 01/2013 Hoàng Trang 13-89 ng th an BM Điện Tử-DSP-FPGA-chapter1 + D ng + D du o FIR Filter Implementation Pipelined implementation (inverted form): cu u x[n] a3 a2 × × a1 × + D + a0 × y[n] D Clock frequency BM Điện Tử-DSP-FPGA-chapter1 f clk ≤ t mult D + + t adder Hoàng Trang 01/2013 13-90 45 CuuDuongThanCong.com https://fb.com/tailieudientucntt 1/26/2013 FIR Filter Implementation Pipelined implementation 4: x[n] a2 × D × × a1 D × a0 D D c om a3 y[n-1] + D f clk ≤ tmult (assume tmult > tadd) co Clock frequency 01/2013 Hoàng Trang 13-91 ng th an BM Điện Tử-DSP-FPGA-chapter1 + D ng + D du o FIR Filter Implementation Pipelined implementation 5: cu u x[n] a0 D D a1 × D × D a2 D × a3 D D + + D D + × f clk ≤ t mult (assume tmult > tadd) y[n-2] Difficult to layout BM Điện Tử-DSP-FPGA-chapter1 Hoàng Trang 01/2013 13-92 46 CuuDuongThanCong.com https://fb.com/tailieudientucntt 1/26/2013 FIR Filter Implementation Parallel implementation 1: x[n+1] x[n+2] x[n] a3 a2 tmult × x[n-1] D f clk ≤ a0 × a3 + t adder × + × a0 Hồng Trang a1 × + y[n] 01/2013 13-93 ng th an BM Điện Tử-DSP-FPGA-chapter1 y[n+1] × a1 + D co x[n+3] × × + ng a2 + D c om + du o FIR Filter Implementation Parallel implementation 2: cu u + D a2 x[n+3] x[n+1] x[n+2] x[n] D × × t mult a3 a0 + + D D × a1 y[n-1] × x[n-1] D f clk ≤ D a2 × D If tmult > tadder BM Điện Tử-DSP-FPGA-chapter1 a3 × a0 D + D Hoàng Trang × a1 × D D + + y[n-2] 01/2013 13-94 47 CuuDuongThanCong.com https://fb.com/tailieudientucntt 1/26/2013 FIR Filter Implementation Parallel implementation 3: + × × D a1 a2 x[n+3] x[n+1] D D x[n+2] x[n] D D a0 × a1 D × a3 D × D + co D Hồng Trang a3 × D D + y[n-6] 01/2013 13-95 ng th an BM Điện Tử-DSP-FPGA-chapter1 × D D D + D × a2 y[n-5] c om a0 D + D ng D + D du o FIR Filter Implementation Serial implementation: x[n-1] x[n-2] x[n-3] cu u x[n] a0 a1 a2 a3 × D Multiplier accumulator (MAC) + D y[n] BM Điện Tử-DSP-FPGA-chapter1 Hoàng Trang 01/2013 13-96 48 CuuDuongThanCong.com https://fb.com/tailieudientucntt 1/26/2013 FIR Filter Implementation Implementation of FIR filters with large number of taps — Examples: implementation of a 16-tap FIR filter Xk-13 Xk-9 Xk-5 Xk-1 a13 a9 a5 a1 Xk-14 Xk-10 Xk-6 Xk-2 a14 a10 a6 a2 Xk-15 Xk-11 Xk-7 Xk-3 × × × × D D D D + + D D 15 + + ng y[ k ] = ∑ • x[ k − i ] i =0 D co D Hoàng Trang 01/2013 13-97 ng th an BM Điện Tử-DSP-FPGA-chapter1 a15 a11 a7 a3 c om Xk-12 a12 Xk-8 a8 Xk-4 a4 Xk a0 du o IIR Filter Implementation Example: u y[n] = b0 • x[n] + b1 • x[n − 1] + a1 • y[n − 1] + a2 • x[n − 2] cu Direct Implementation: x[n] D × b0 b1 D × a2 + Clock frequency BM Điện Tử-DSP-FPGA-chapter1 × a1 + f clk ≤ tmult D × + y[n] + • tadder Hồng Trang 01/2013 13-98 49 CuuDuongThanCong.com https://fb.com/tailieudientucntt 1/26/2013 IIR Filter Implementation Pipelined Implementation 1: x[n] D D a2 D + D D + + D tmult y[n-3] co (assume tmult > tadd) Hoàng Trang 01/2013 13-99 ng th an BM Điện Tử-DSP-FPGA-chapter1 × a1 D f clk ≤ Clock frequency × c om × b1 ng × b0 du o IIR Filter Implementation Pipelined Implementation 2: b0 + D × a1 b1 × × + cu u x[n] y[n-1] D + D a2 × BM Điện Tử-DSP-FPGA-chapter1 f clk ≤ Hoàng Trang tmult + • tadder 01/2013 13-100 50 CuuDuongThanCong.com https://fb.com/tailieudientucntt 1/26/2013 LUT-Based Multiplier In many DSP circuits, multipliers always have one constant input Ci (constant) × x[n] y[n] For the above multiplier, y[n] purely depends on x[n] Thus, address y[n] For example, a 256×16 bit memory can be used to implement a 8-bit multiplier if one of its input is always constant Hoàng Trang 01/2013 13-101 ng th an BM Điện Tử-DSP-FPGA-chapter1 co ng ••• X[n] c om a look-up table (LUT) can be used to implement the multiplier du o Distributed Arithmetic cu u Multiplication by using shift-and-add technique BM Điện Tử-DSP-FPGA-chapter1 Hoàng Trang 01/2013 13-102 51 CuuDuongThanCong.com https://fb.com/tailieudientucntt 1/26/2013 Distributed Arithmetic Hoàng Trang 01/2013 13-103 ng th an BM Điện Tử-DSP-FPGA-chapter1 co ng c om Calculate A•Y0 + B•Y1 + C•Y2 + D•Y3 du o Distributed Arithmetic cu u Serial Distributed Arithmetic for Computing A•Y0 + B•Y1 + C•Y2 + D•Y3 BM Điện Tử-DSP-FPGA-chapter1 Hồng Trang 01/2013 13-104 52 CuuDuongThanCong.com https://fb.com/tailieudientucntt 1/26/2013 Distributed Arithmetic Hoàng Trang 01/2013 13-105 01/2013 13-106 ng th an BM Điện Tử-DSP-FPGA-chapter1 co ng c om LUT-Based SDA for Computing A•Y0 + B•Y1 + C•Y2 + D•Y3 du o Distributed Arithmetic cu u LUT Technique for Distributed Arithmetic BM Điện Tử-DSP-FPGA-chapter1 Hoàng Trang 53 CuuDuongThanCong.com https://fb.com/tailieudientucntt 1/26/2013 Distributed Arithmetic Hoàng Trang 01/2013 13-107 01/2013 13-108 ng th an BM Điện Tử-DSP-FPGA-chapter1 co ng c om SDA 16-MAC Circuit du o Distributed Arithmetic cu u SDA 16-Tap FIR Filter BM Điện Tử-DSP-FPGA-chapter1 Hoàng Trang 54 CuuDuongThanCong.com https://fb.com/tailieudientucntt 1/26/2013 Hoàng Trang 01/2013 13-109 cu u du o ng th an BM Điện Tử-DSP-FPGA-chapter1 co ng c om Parallel Distributed Arithmetic END chapter BM Điện Tử-DSP-FPGA-chapter1 Hoàng Trang 01/2013 110 55 CuuDuongThanCong.com https://fb.com/tailieudientucntt ... Introduction Hoàng Trang 01/2013 13 ng th an BM Điện Tử -DSP -FPGA- chapter1 cu u du o Typical DSP Application BM Điện Tử -DSP -FPGA- chapter1 Hoàng Trang 01/2013 14 CuuDuongThanCong. com https://fb .com/ tailieudientucntt... Currently, FPGAs are widely used in implementing communication systems, configurable computers, and DSP applications BM Điện Tử -DSP -FPGA- chapter1 Hoàng Trang 01/2013 1-56 28 CuuDuongThanCong. com https://fb .com/ tailieudientucntt... extremely fast turn-out time since FPGA devices has been fabricated BM Điện Tử -DSP -FPGA- chapter1 Hoàng Trang 01/2013 1-52 26 CuuDuongThanCong. com https://fb .com/ tailieudientucntt 1/26/2013 Comparison