Strain engineering for advanced silicon transistors

... STRAIN ENGINEERING FOR ADVANCED SILICON TRANSISTORS DING YINJIE (B.Eng.(Hons.)), NUS A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING ... 1.2   Strained Si Transistor Technology 3  1.3   Strain Effects on Carrier Mobility 6  1.4   Strain Engineering for Advanced Transistor Architectures 16  1.4.1   Strain...

Ngày tải lên: 10/09/2015, 09:26

... STRAIN ENGINEERING FOR ADVANCED SILICON, GERMANIUM AND GERMANIUM- TIN TRANSISTORS CHENG RAN (B ENG (HONS.)), NUS A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY ... Transistors 69 4.1.2 Strain Engineering for Ge P-channel MOSFETs (pMOSFETs) 71 4.2 4.3 Key Concept: Exploiting Ge2Sb2Te5 for Strain Engineering 73 Stress Simulation and ... Ge Trimmi...

Ngày tải lên: 09/09/2015, 11:28

... STRAIN ENGINEERING FOR ADVANCED TRANSISTOR STRUCTURE TAN KIAN MING (B ENG (HONS.)), NUS (M ENG.), NUS A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY ... can induce strain in the transistor channel [2.2], and the localized strain could be exploited to enhance the performance of aggressively scaled transistors While many approaches to strained-Si ... to investigat...

Ngày tải lên: 14/09/2015, 14:13

... ADVANCED SOURCE AND DRAIN CONTACT ENGINEERING FOR MULTIPLE- GATE TRANSISTORS RINUS TEK PO LEE A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILIOSOPHY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING ... 161 vi Abstract Advanced Source and Drain Contact Engineering for Multiple- Gate Transistors by Rinus Tek Po Lee Doctor of Philosophy − Electric...

Ngày tải lên: 15/09/2015, 21:48

... Abstract Contact and Source/ Drain Engineering for Advanced III- V Field- Effect Transistors By Kong Yu Jin, Eugene Doctor of Philosophy – Electrical and Computer Engineering National University ... metallization V Voltage Vd Voltage or bias applied to the drain of a MOSFET Vdd Supply voltage Vg Voltage or bias applied to the gate of a MOSFET Vt,sat Saturation thr...

Ngày tải lên: 30/09/2015, 05:43

... etch recipes for poly Si gate etch (main etch for removing poly Si in planar region) and poly Si spacer removal etch (over etch step) The poly Si over etch recipe employs HBr and smaller power to ... compares material characteristics of potential channel materials for future CMOS applications, showing 10 Table 1.1 Material characteristics of potential channel materials for...

Ngày tải lên: 08/09/2015, 17:50

... ADVANCED CONTACT ENGINEERING FOR SILICON, GERMANIUM, GERMANIUM- TIN DEVICES TONG YI (M Eng.), NUS A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL AND COMPUTER ... on contact engineering for Si, Ge, and GeSn devices Low contact resistance is needed for advanced Si based devices and also new generation of Ge or GeSn base...

Ngày tải lên: 09/09/2015, 11:07

... used for metallisation of HET cells [38] Metallisation technologies for Si wafer solar cells (including HET cells) are discussed further in Section 2.6 Screen printing for HET cells and plating for ... technologies for silicon wafer solar cell metallisation The metallisation technologies are applied to silicon homojunction and amorphous silicon/ crystalli...

Ngày tải lên: 09/09/2015, 08:11

... SCHOTTKY BARRIER ENGINEERING FOR CONTACTS IN ADVANCED CMOS TECHNOLOGY PHYLLIS LIM SHI YA (B ENG (HONS.)), NATIONAL UNIVERSITY OF SINGAPORE A THESIS SUBMITTED FOR THE DEGREE OF ... in CMOS technology 14 1.6 Modulation of Schottky barrier height 16 1.6.1 S/D material engineering 16 1.6.2 Dopant segregation engineering 17 1.6.3 Interface engineering ... of Ge...

Ngày tải lên: 09/09/2015, 10:21

... SOURCE AND DRAIN EXTERNAL RESISTANCE REDUCTION FOR ADVANCED TRANSISTORS KOH SHAO MING A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL AND COMPUTING ... Publications 157 References 161 iv Abstract Source and Drain External Resistance Reduction for Advanced Transistors by Koh Shao Ming Doctor of Philosophy – Electrical...

Ngày tải lên: 09/09/2015, 17:56

... DEFECT ENGINEERING IN THE FORMATION OF ULTRA- SHALLOW JUNCTIONS FOR ADVANCED NANO- METAL- OXIDESEMICONDUCTOR TECHNOLOGY YEONG SAI HOOI (B Eng (Hons.), NUS) A THESIS SUBMITTED FOR THE DEGREE OF ... USJs for the application in nano- CMOS devices through the understanding and maneuvering of dopant -defect interactions, known as defect engineering T...

Ngày tải lên: 11/09/2015, 09:58

... Schottky Barrier Engineering for Contact Resistance Reduction in Nanoscale CMOS Transistors by Mantavya Sinha Doctor of Philosophy – Electrical and Computer Engineering National University of Singapore ... is on Schottky barrier engineering for contact resistance reduction in CMOS FETs Various material and process innovations are explored for the lo...

Ngày tải lên: 14/09/2015, 08:26

... ADVANCED SOURCE AND DRAIN CONTACT ENGINEERING FOR LOW PARASITIC SERIES RESISTANCE KOH TIAN YI, ALVIN (B.ENG (HONS.), NUS) A THESIS SUBMITTED FOR THE DEGREE OF MASTER ENGINEERING DEPARTMENT ... Annealing on Silicon-Carbon Source/ Drain in MuGFETs 5.2 83 84 Future Work 85 Appendix A: Publication List 86 v Advanced Source/ Drain Contact Engineering For Lo...

Ngày tải lên: 26/09/2015, 11:07

Ngày tải lên: 06/08/2013, 01:25

... acceleration a ball- screw can use with out getting ball skid? A: A general rule of thumb is to calculate the ball nut critical speed based on dN = 3000 for inch series ball nuts and dN = 140,000 for metric ... What are the key design criteria to establish a servo drive driven ball screw assembly for stiffness? The ball screw drive has been the largest "spring element" when...

Ngày tải lên: 13/12/2013, 01:16