Strain engineering for advanced silicon, germanium and germanium tin transistors

STRAIN ENGINEERING FOR ADVANCED SILICON, GERMANIUM AND GERMANIUMTIN TRANSISTORS CHENG RAN NATIONAL UNIVERSITY OF SINGAPORE 2014 STRAIN ENGINEERING FOR ADVANCED SILICON, GERMANIUM AND GERMANIUM-TIN TRANSISTORS CHENG RAN (B. ENG. (HONS.)), NUS A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2014 DECLARATION I hereby declare that the thesis is my original work and it has been written by me in its entirety. I have duly acknowledged all the sources of information which have been used in the thesis. This thesis has also not been submitted for any degree in any university previously. _________________ CHENG Ran 29 Jan, 2014 i Acknowledgements The journey towards a Ph. D degree is never easy. I would like to take this opportunity to give my sincere gratitude and appreciations to people who helped me once and all along the way. My first and foremost appreciation is given to my supervisor, Prof. Yeo Yee Chia, who provides me a lot of technical, financial and mental supports during my research course. His comprehensive knowledge, his creative yet rigorous thinking, as well as his passion and diligence in research, inspire me to always pursue the truth behind the unknowns. My Ph.D candidature could never be easier without his strict training and heartfelt support. In addition, as a successful professional in his career, Prof. Yeo also showcases to me how to deal with stress, relationships, frustrations and success, all of which are invaluable for my future career. I should also give the great thankfulness to my lovely seniors and peers. At the initial stage of my Ph.D study, my seniors offered me a lot of personal guidance and trainings, which helped me to be on the right track of research quickly. I would like to express my tremendous appreciation to Dr. LIU Bin for his patient training and thoughtful encouragement, which benefits me through and beyond my Ph. D candidature. Additional thanks would be given to Dr. TAN Kian Ming and Dr. KOH Shao Ming for providing some of the resources for strain engineering and carrier transport experiments. I am so blessed to work in a lab with warmth and cheerfulness. My fellow lab mates in Silicon Nano Device Laboratory (SNDL) brought me a lot ii of happiness and inspirations. It is impossible to enumerate all, but I cannot fail to mention these knowledgeable and passionate Drs. and Drs. to be: YANG Yue, Pengfei, Yinjie, WANG Wei, GONG Xiao, ZHOU Qian, Genquan, Xingui, TONG Xin, Phyllis, Eugene, Lanxiang, TONG Yi, DONG Yuan, Xu Xin, and many others for their useful suggestions, assistance, and friendships. I wish them a continuous success in their future endeavours. I would also like to acknowledge the strong technical and administrative support from the technical staffs in SNDL, specifically Mr O YAN Wai Linn and Patrick TANG. Special thanks also go to staffs from Institute of Materials Research, and Engineering (IMRE): Mr. CHUM Chan Choy and Ms. TEO Siew Lang for their strong support on EBL, and HUI Hui Kim for TEM support. My overseas collaborators Dr. Nicolas Daval and Bich-Yen Nguyen of Soitec and Dr. AUGENDRE Emmanuel of Cea-Leti also contributed to this work by supporting me with technical resources and giving valuable inputs. I owe big thanks to them. At the end, I would like to express my gratitude towards my extended families, my encouraging mother, father, my sweet little brother, Totoron, Mathew, Lily, and my considerate parents-in-law. My last appreciation gives to my closest friend and life partner, ZHOU Fang, for all the love, care, understanding, patience, flexibility etc. he offered to me. Life is a one-time journey and I am so grateful that he could experience all these happy and difficult moments, together with me. iii Table of Contents DECLARATION . i Acknowledgements ii Summary vii List of Tables x List of Figures . xi List of Symbols xxiii List of Abbreviations xxviii Chapter Introduction . 1.1 Background . 1.2 Strained Technology for Si CMOS 1.2.1 Strain-enhanced Electron Mobility . 1.2.2 Strain-enhanced hole mobility 1.3 Strain Technology for High Mobility Ge Transistors . 11 1.3.1 Development of Ge multi-gate field-effect transistors (MuGFETs) . 12 1.3.2 Strain engineering for Ge MuGFETs 15 1.4 High Mobility Channel Material – GeSn Alloy 17 1.5 Thesis Outline and Original Contributions 18 Chapter Carrier Transport in Strained P-channel Field-Effect Transistors (P-FETs) with Diamond-like Carbon (DLC) Liner Stressor 20 2.1 Background . 20 2.1.1 Diamond-like Carbon (DLC) Liner Stressor 20 2.1.2 Carrier Backscattering for Nanoscale MOSFETs . 21 2.2 2.3 2.4 Temperature Dependent Backscattering Model 23 Experiments . 25 Results and Discussion 26 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 I-V characteristics of p-FETs with DLC liner stressor 26 Extraction of Temperature Dependent Parameters α and η 29 Investigation of λo/lo, rsat, and Bsat . 34 Enhancement of Carrier Injection Velocity υinj 37 Enhancement of Carrier Mobility µ 39 2.5 Summary 41 Chapter GeTe Liner Stressor featuring Phase-Change Induced Volume-Contraction for Strain Engineering of Sub-50 nm pChannel FinFETs: Simulation and Electrical Characterization . 42 3.1 Background . 42 3.2 Concept and Material Selection . 44 3.3 Stress Simulation and Valence Band Structure Calculation . 47 3.3.1 Stress Simulation 47 iv 3.3.2 Valence Band Structure Calculation . 50 3.4 Device Fabrication and Integration Of GeTe Liner Stressor . 54 3.5 Electrical Results and Discussion 57 3.6 Summary 68 Chapter Asymmetrically Strained High Performance Germanium Gate-all-around Nanowire p-FETs Featuring 3.5 nm Wire Width and Contractible Phase Change Liner Stressor (Ge2Sb2Te5) 69 4.1 Background . 69 4.1.1. High Mobility Ge Gate-all-around (GAA) Nanowire (NW) Transistors 69 4.1.2. Strain Engineering for Ge P-channel MOSFETs (pMOSFETs) 71 4.2 4.3 Key Concept: Exploiting Ge2Sb2Te5 for Strain Engineering 73 Stress Simulation and Valence Band Structure Calculation . 75 4.3.1 Strain Simulation 75 4.3.2 Valence Band Structure Calculation . 77 4.4 Experiments . 81 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 4.4.7 4.5 Ge Trimming and n-well Formation . 83 Ge Fin Pattering and Formation 85 Formation of Ge Nanowires 86 Gate Stack Formation . 87 Gate Patterning and Formation . 88 Formation of Self-aligned Metallic Schottky-Barrier (SB) Source/Drain . 89 Integration of GST Liner Stressor on Ge NW p-FETs 91 Results and Discussion 93 4.5.1 4.5.2 4.5.3 4.5.5 TEM Characterization . 93 Electrical Characteristics of Ge GAA NW FET . 94 Integration of GST Liner Stressor on Ge GAA NW FETs 98 Benchmarking of Ge p-channel MuGFETs and NW FETs 104 4.6 Summary 107 Chapter Relaxed and Strained Patterned Germanium-Tin Structures: A Raman Scattering Study . 108 5.1 Background . 108 5.2 Experiments . 110 5.2.1 H2O2-Based Wet Etch . 110 5.2.2 Fabrication of Fully-Relaxed GeSn Patterns 114 5.3 Results and Discussion 115 v 5.3.1 5.3.2 5.3.3 XRD Characteristics . 115 Raman Peak Shift due to Alloy Disorder Δωalloy and Strain Δωstrain . 117 Study on Tensile Strained Ge1-xSnx Structure . 135 5.4 Summary 138 Chapter Conclusions and Future Work . 140 6.1 Conclusions and Contributions of This Thesis . 140 6.1.1 6.1.2 6.1.3 6.1.4 Carrier Transport Study for Si p-channel FETs (p-FETs) with Diamond-like Carbon (DLC) Liner Stressor 140 Investigation of Compressively Strained Si p-channel FinFETs (p-FinFETs) with Phase Change (GeTe) Liner Stressor 141 High Performance of Ge Gate-all-around (GAA) Nanowire (NW) FET with Phase Change Liner Stressor (Ge2Sb2Te5) . 142 Realization of Relaxed and Tensile Strained GeSn Alloys 144 6.2 Future Directions 145 REFERENCES . 149 Appendices 185 A. B. C. A Detailed Derivation of Eq. (2.7) . 185 Calculation of the lattice constants of Ge1-xSnx:  || Bulk aGe , aGe1 xSn x and aGe1 xSn x 188 1 xSn x List of Publications . 189 vi Summary The continuously scaled silicon (Si) complementary metal-oxidesemiconductor (CMOS) field-effect transistor technology reduces the cost per function but also introduces several technical issues like mobility degradation and increased off-state leakage. To address some of the technical issues, this thesis provides both the short-term and long-term solutions to increase the drive current IDsat of metal-oxide-semiconductor field-effect transistors (MOSFETs) in the future technology nodes. Improvement in the transistor drive current has traditionally been realized by device miniaturization. Since 90 nm technology node, strain engineering has been adopted as an additional performance booster to increase the transistor mobility and IDsat. The carrier transport characteristics of compressively strained p-channel FETs (p-FETs) with Diamond-like carbon (DLC) liner stressor were investigated. DLC liner stressor induces large compressive strain in the transistor channel, leading to significant IDsat enhancement. For nanoscale transistors operating in quasi-ballistic regime, two factors determine the intrinsic drive current (external resistance is not considered), i.e., injection velocity υinj and scattering coefficient rsat. A temperature dependent channel backscattering model was employed to extract rsat, and υinj. The impact of highly compressive strain due to DLC over carrier transport parameters was compared for p-FETs with and without DLC liner stressor. Correlation between carrier mobility and ballistic efficiency Bsat will also be discussed. vii Due to the aggressive gate pitch reduction, the effective channel stress induced by the current SiN stress liner decreases, making the SiN liner technology less effective in boosting device performance. A new strain engineering concept involving volume contraction of the liner material was introduced. Phase change material GeTe was used as a liner stressor, exploiting its property of volume contraction when phase-changed from the amorphous state (α-GeTe) to the polycrystalline state (c-GeTe). Simulation and experimental demonstration of strained p-channel FinFETs with GeTe liner stressor were documented. A finite element method simulation followed by a k·p calculation was performed to study the impact of GeTe-induced strain on the Si valence band structure. GeTe liner stressor results in reduction in hole effective mass and the band dispersion between HH and LH near Γ point. Electrical characterization of Si p-FinFETs with and without GeTe liner stressor were carried out. Significant IDsat enhancement was observed for FinFETs with c-GeTe liner stressor over the control devices. Germanium (Ge) exhibits very high electron and hole bulk mobilities, and is considered as one of the promising channel materials to replace Si in the sub-10 nm technology node. Since 22 nm technology node, transistors with multi-gate structures (MuGFETs or FinFETs) have been used for high volume CMOS production as the additional gates provide better control of short channel effects (SCEs). Strain engineering could further increase the device drive current in Ge MuGFETs or gate-all-around (GAA) nanowire (NW) FETs . The first integration of Ge2Sb2Te5 (GST) liner stressor with Ge GAA NW FETs formed on GeOI substrates is documented in this thesis. Ge NWs with ultra- viii [150] T. Hanrath and B. A. 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Michel, “High phosphorous doped germanium: Dopant diffusion and modeling,” Journal of Applied Physics, vol. 112, p. 034509, 2012. [210] J. Kim, S. W. Bedell, and D. K. Sadana, “Improved germanium n+/p junction diodes formed by coimplantation of antimony and phosphorus,” Applied Physics Letters, vol. 98, p. 082112, 2011. 184 Appendices A. A Detailed Derivation of Eq. (2.7) According to Eqs. (2.4) and (2.6), υinj and lo are temperature dependent and can be expressed in another form as: 2k B T  c1T 0.5 , * πm  inj  lo  (A.1) k BT  c 2T , q (0  ) (A.2) Therefore, the λo/lo ratio can be expressed as: o lo  2k BT q inj c 2T  2k B 2k B ,  q injc qc1 c T 0.5 (A.3) where the low-field carrier mobility μ is also temperature dependent and can be expressed as:   c3T 1.5 . (A.4) In the above equations, c1, c2 and c3 are proportionality constant. Substituting Eq. (A.4) to (A.3), the λo/lo ratio can be written as: o lo  2c 3T 1.5 k B qc1 c T 0.5  AT  , where A  (A.5) 185 2c k B . qc1 c The inversion layer charge QINV is proportional to the gate overdrive and can be expressed as: QINV  (VGS  VTsat )  c4 (VGS  VTsat ) , (A.6) Therefore, by substituting Eqs. (A.1), (A.5) and (A.6) to Eq. (2.3), we can get I Dsat  Wc1c AT 1.5 (VGS  VTsat )  AT 2 . (A.7) Differentiating (4-7) with respect to temperature, we can get: dI Dsat Wc1c AT 1.5 (VGS  VTsat )  dT  AT    dVGS dVTsat  1.5    T    dT  0.5    dT  2.5  Wc1c A  (VGS  VTsat )T  . 2 2 2  2 (2  AT )   AT   AT      The temperature dependent parameter α can be obtained by normalizing the above equation with respect to IDsat, which is:  I Dsat I Dsat T 186   dVGS dVTsat  1.5    T    dT  0.5    dT  2.5 Wc1c A  (VGS  VTsat )T   2 2 2  2 (2  AT )   AT   AT     Wc1 c AT 1.5 (VGS  VTsat )  AT  1  1   T 2   l o o    dVGS dVTsat     dT   dT  . VGS  VTsat (A.8) As VGS was not changed throughout the temperature dependent I-V measurement, dVGS /dT = 0. Eq. (A.8) can therefore be written as: 1 2     1 VDsat  , where   . T  T  o l o  VGS  VTsat 187 B.  || Calculation of the lattice constants of Ge1-xSnx: aGe1 xSn x , aGe1 xSn x and Bulk aGe 1 xSn x  For (001) Ge1-xSnx, the out-of-plane lattice constant aGe1 xSn x can be expressed as  aGe  1 xSn x 2 , sin  004 (B.1) where λ = 1.5406 Å, and θ004 is the Bragg angle of the Ge1-xSnx alloy in (004) || diffraction order. The in-plane lattice constant a Ge can be calculated as 1 xSn x aG|| e1 xSn x     16    d  224 aGe1 xSn x       1/ , (B.2) where the inter-plane distance dhkl is calculated as λ/(2sinθhkl). Therefore, the bulk Ge1-xSnx lattice constant can be calculated as     2c12  || c11 Bulk aGe1 xSn x   aGe1 xSn x , aGe   1 xSn x  c11  2c12   c11  2c12  (B.3) and the elastic constant cij  (1  x)cij ,Ge  xcij ,Sn . cij,Ge and cij,Sn are the elastic constants for Ge and Sn, respectively. 188 C. List of Publications Journal Publications [1] R. Cheng, B. Liu, and Y.-C. Yeo, “Carrier transport in strained pchannel field-effect transistors with diamond-like carbon liner stressor,” Applied Physics Letters, vol. 96, no. 9, 092113, Mar. 2010. [2] R. Cheng, W. Wang, X. Gong, L. Sun, P. Guo, H. Hu, Z. Shen, G. Han, and Y.-C. Yeo, “Relaxed and strained patterned germanium-tin structures: A Raman scattering study,” ECS Journal of Solid State Science and Technology, vol. 2, no. 4, pp. P138 - P145, Jan. 2013. [3] R. Cheng, Y. Ding, S.-M. Koh, F. Bai, B. Liu, and Y.-C. Yeo, “GeTe Liner Stressor featuring Phase-Change Induced Volume-Contraction for Strain Engineering of Sub-50 nm p-Channel FinFETs: Simulation and Electrical Characterization,” Accepted manuscript by Trans. Elec. Dev., 2014. [4] Y. Ding, R. Cheng, A. Du, and Y.-C. Yeo, “Lattice strain analysis of silicon fin field-effect transistor structures wrapped by Ge2Sb2Te5 liner stressor,” J. Applied Physics, vol. 113, no. 7, 073708, Feb. 2013. [5] Y. Ding, R. Cheng, Q. Zhou, A. Du, N. Daval, B.-Y. Nguyen, and Y.C. Yeo, “Strain engineering of ultra-thin silicon-on-insulator structures using through-buried-oxide ion implantation and crystallization,” SolidState Electronics, vol. 83, pp. 37 - 41, Feb. 2013. [6] X. Gong, G. Han, F. Bai, S. Su, P. Guo, Y. Yang, R. Cheng, D. Zhang, G. Zhang, C. Xue, B. Cheng, J. Pan, Z. Zhang, E. S. Tok, D. Antoniadis, and Y.-C. Yeo, “Germanium-tin (GeSn) p-channel MOSFETs fabricated on (100) and (111) surface orientations with sub-400 °C Si2H6 passivation,” IEEE Electron Device Letters, vol. 34, no. 3, pp. 339 - 341, Mar. 2013. [7] B. Liu, C. Zhan, Y. Yang, R. Cheng, P. Guo, Q. Zhou, N. Daval, C. Veytizou, D. Delprat, B.-Y. Nguyen, and Y.-C. Yeo, “Germanium multiple-gate field-effect transistor with in situ boron doped raised source/drain,” IEEE Trans. Electron Devices, vol. 60, no. 7, pp. 2135 2141, Jul. 2013. [8] Y. Ding, R. Cheng, S.-M. Koh, B. Liu, and Y.-C. Yeo, “Phase-change liner stressor for strain engineering of p-channel FinFETs,” IEEE Trans. Electron Devices, vol. 60, no. 9, pp. 2703 - 2711, Sep. 2013. Conference Publications [9] Y. Ding, R. Cheng, S.-M. Koh, B. Liu, A. Gyanathan, Q. Zhou, Y. Tong, P. S.-Y. Lim, G. Han, and Y.-C. Yeo, “A new Ge2Sb2Te5 (GST) liner stressor featuring stress enhancement due to amorphous-crystalline 189 phase change for sub-20 nm p-channel FinFETs,” IEEE International Electron Device Meeting 2011, Washington, DC, USA, Dec. - 7, 2011, pp. 833 - 836. [10] R. Cheng, Y. Ding, and Y.-C. Yeo, “Modeling of a new liner stressor comprising Ge2Sb2Te5 (GST): Amorphous-crystalline phase change and stress induced in FinFET channel,” International Semiconductor Device Research Symposium, (ISDRS), College Park, MD, USA, Dec. - 9, 2011. [11] X. Gong, Z. Zhu, E. Kong, R. Cheng, S. Subramanian, K. H. Goh, and Y.-C. Yeo, “Ultra-thin-body In0.7Ga0.3As on nothing N-MOSFET with Pd-InGaAs S/D contacts enabled by a new self-aligned cavity formation technology,” International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr. 23-25, 2012. [12] Y. Ding, R. Cheng, Q. Zhou, A. Du, N. Daval, B.-Y. Nguyen, and Y.C. Yeo, “Strain engineering of ultra-thin silicon-on-insulator structures using ion implant,” 6th International SiGe Technology and Device Meeting (ISTDM), Berkeley, CA, USA, June 4-6, 2012, pp. 84 - 85. [13] R. Cheng, Y. Ding, S.-M. Koh, A. Gyanathan, F. Bai, B. Liu, and Y.-C. Yeo, “A new liner stressor (GeTe) featuring stress enhancement due to very large phase-change induced volume contraction for p-channel FinFETs,” Symp. on VLSI Tech. 2012, Honolulu HI, USA, Jun. 12 - 14, 2012, pp. 93 - 94. [14] R. Cheng, X. Gong, P. Guo, F. Bai, Y. Yang, B. Liu, K. H. Goh, S. Su, G. Zhang, C. Xue, B. Cheng, G. Han, and Y.-C. Yeo, “Top-down GeSn nanowire formation using F-based dry etch and H2O2-based wet etch,” 43rd Semiconductor Interface Specialist Conference, San Diego, CA, USA, Dec. - 8, 2012. [15] G. Han, X. Gong, F. Bai, R. Cheng, P. Guo, K. H. Goh, S. Su, G. Zhang, C. Xue, B. Cheng, and Y.-C. Yeo, “(111)-oriented strained GeSn channel pMOSFET with low temperature Si2H6 surface passivation,” 43rd Semiconductor Interface Specialist Conference, San Diego, CA, USA, Dec. - 8, 2012. [16] P. Guo, C. Zhan, Y. Yang, X. Gong, B. Liu, R. Cheng, W. Wang, J. Pan, Z. Zhang, E. S. Tok, G. Han, and Y.-C. Yeo, “Germanium-tin (GeSn) nchannel MOSFETs with low temperature silicon surface passivation,” International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr. 22-24, 2013. [17] X. Gong, G. Han, S. Su, R. Cheng, P. Guo, F. Bai, Y. Yang, Q. Zhou, K. H. Goh, G. Zhang, C. Xue, B. Cheng, and Y.-C. Yeo, “Uniaxially strained germanium-tin (GeSn) gate-all-around nanowire PFETs enabled by a novel top-down nanowire formation technology,” Symp. on VLSI Tech. 2013, Kyoto, Japan, Jun. 11 - 13, 2013, pp. T34 - T35. 190 [18] Y.-C. Yeo, X. Gong, P. Guo, Y. Yang, L. Wang, Y. Tong, K. L. Low, C. Zhan, R. Cheng, B. Liu, W. Wang, Q. Zhou, X. Xu, and Y. Dong, “Application of germanium-tin (GeSn) in field-effect transistors,” IEEE Nanotechnology Materials and Devices Conference(NMDC), Taiwan, Taiwan, Oct. - 9, 2013. [19] R. Cheng, B. Liu, P. Guo, Y. Yang, Q. Zhou, X. Gong, D. Yuan, K. Bourdelle, N. Daval, D. Delprat, B.-Y. Nguyen, and Y.-C. Yeo, “Asymetrically strained high performance germanium gate-all-around nanowire p-FET featuring 3.5 nm wire width and contractable phase change liner stressor (Ge2Sb2Te5),” IEEE International Electron Device Meeting 2013, Washington, DC USA, Dec. - 11, 2013. [20] B. Liu, X. Gong, R. Cheng, P. Guo, Q. Zhou, M. H. S. Owen, C. Guo, L. Wang, W. Wang, Y. Yang, Y.-C. Yeo, C.-T. Wan, S.-H. Chen, C.-C. Cheng, Y.-R. Lin, C.-H. Wu, C.-H. Ko, and C. H. Wann, “High performance Ge CMOS with novel InAlP-passivated channels for future sub-10 nm technology node applications,” IEEE International Electron Device Meeting 2013, Washington, DC USA, Dec. - 11, 2013. [21] P. Guo, R. Cheng, W. Wang, Z. Zhang, J. Pan, E. S. Tok, and Y.-C. Yeo, “Silicon-passivated germanium-tin: An angle-resolved X-ray photoelectron spectroscopy study of surface segregation effects,” 44th IEEE Semiconductor Interface Specialists Conference, Arlington, VA USA, Dec. - 7, 2013. [22] X. Gong, Y. Yang, P. Guo, W. Wang, R. Cheng, L. Wang, E. S. Tok, and Y.-C. Yeo, “Germanium-tin p-channel field-effect transistor with low-temperature Si2H6 passivation,” 226th Electrochemical Society Meeting, Cancun, Mexico, Oct. - 10, 2014, ECS Transactions. 191 [...]... (a) and (b) show the 3-D equi-energy surfaces (E = 30 meV) of the Si topmost valence bands with no strain and strain induced by the GeTe stressor, respectively (c) and (d) are the 2-D equi-energy contours of the Si topmost valence band with no strain and strain induced by the GeTe stressor, respectively (e) and (f) are the corresponding E-k diagrams of the unstrained and GeTe-linerstrained Si The strain. .. effective mass and/ or the scattering rate For electrons, reduction in both m* and τ-1 are major contributors for mobility enhancement [19] However for holes, the (b) (a) Kz Kz ml mt Δ2 Kx Ky Kx Ky Δ4 Unstrained Si Strained Si Fig 1.3 Equi-energy surfaces for the 6 degenerate conduction band valleys for unstrained (a) and strained (b) Si Application of strain splits the energy levels to be 2 Δ2 (red) and 4 Δ4... valence bands with no strain and asymmetric strain induced by the GST stressor, respectively (c) and (d) are the corresponding E-k diagrams The strain- induced band warping leads to the heavy-hole (HH) subband to be ligh-hole (LH) like, resulting in a reduced hole meff In addition, the asymmetric strain increases the separation between HH and LH subbands near Γ point, therefore, decreasing the interband... Bulk aGe Lattice constant of bulk germanium Bulk aGe1 xSn x Lattice constant of bulk germanium- tin Bulk aSn Lattice constant of bulk tin || aGe1 xSn x In-plane lattice constant of bulk germanium- tin  aGe1 xSn x Out-of-plane lattice constant of bulk germanium- tin as Uniaxial phonon deformation parameter av, b, d valence band deformation potentials b Coefficient for strain- induced Raman peak shift... degenerate conduction band valleys for unstrained (a) and strained (b) Si Application of strain splits the energy levels to be 2 Δ2 (red) and 4 Δ4 valleys (blue) 4 Fig 1.4 (a)-(c) 3-D equi-energy surfaces (E = 25 meV) for the top most valence band of Si with (a) no stress, (b) 1 GPa biaxial tensile stress, and (c) uniaxial compressive stress in [110] direction (d)-(f) E-k diagrams for Si with no stress,... from the calculation of meff µB and µB’ refer to xvi the ballistic mobility for Ge without and with strain, respectively 81 Fig 4.7 Top-down process for fabricating Ge gate-all-around (GAA) Nanowire (NW) p-FETs 3-D schematics and the corresponding 2D illustrations cut along AA’ plane of the structure (a) after fin patterning and etching, and (b) after the formation of the Ge NW (c) GAA... performance GeSn n-MOSFETs as well as for direct-bandgap photonic applications The first realization of fully-released and relaxed Ge1-xSnx structures on Ge substrate is documented in this thesis Raman characterization is performed on relaxed and tensile strained Ge1-xSnx structures to extract the coefficients of Raman peak shift a and b due to the alloy disorder and strain, respectively To lower the Sn... observed for the strained device, as compared with the unstrained one 99 Fig 4.24 Extrinsic Gm,sat-VGS plot of of the same GAA FET with GST liner stressor before (unstrained) and after (strained) anneal, measured at VDS = -1 V A peak Gm,sat enhancement of 34% could be observed 100 xviii Fig 4.25 Peak intrinsic GM,lin (VDS = -50 mV) and GM,sat (VDS = -0.95 V) were extracted and compared... Fig 3.16 DIBL and SS are plotted as a function of LG Comparable DIBL and SS are observed at each gate length for the control and strained FinFETs 63 xv Fig 3.17 Plot of IDsat versus DIBL showing significant enhancement in IDsat for strained p-FinFETs over the control devices IDsat is defined at VGS – VT = −1.1 V and VDS = -1.2 V The devices have LG in the range of 15 – 55 nm and WFin in the... vertical field Eeff for Intel process technologies [2] Eeff is defined as (VGS + VT)/6TOX [8] As TOX scales down, Eeff increases, resulting in more surface scattering and therefore decreasing the carrier mobility [9] 3 1.2 Strained Technology for Si CMOS Since the 90 nm technology node, SiGe source/drain (S/D) stressor for p- channel MOSFETs (p-MOSFETs) and SiN contact etch-stop layer (CESL) for nchannel . STRAIN ENGINEERING FOR ADVANCED SILICON, GERMANIUM AND GERMANIUM- TIN TRANSISTORS CHENG RAN NATIONAL UNIVERSITY OF SINGAPORE 2014 STRAIN ENGINEERING FOR ADVANCED. (NW) Transistors 69 4.1.2. Strain Engineering for Ge P-channel MOSFETs (p- MOSFETs) 71 4.2 Key Concept: Exploiting Ge 2 Sb 2 Te 5 for Strain Engineering 73 4.3 Stress Simulation and Valence. resulting in more surface scattering and therefore decreasing the carrier mobility [9]. 3 Fig. 1.3. Equi-energy surfaces for the 6 degenerate conduction band valleys for unstrained (a) and strained