SOURCE AND DRAIN EXTERNAL RESISTANCE REDUCTION FOR ADVANCED TRANSISTORS

SOURCE AND DRAIN EXTERNAL RESISTANCE REDUCTION FOR ADVANCED TRANSISTORS KOH SHAO MING NATIONAL UNIVERSITY OF SINGAPORE 2012 SOURCE AND DRAIN EXTERNAL RESISTANCE REDUCTION FOR ADVANCED TRANSISTORS KOH SHAO MING A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL AND COMPUTING ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2012 Acknowledgements First and foremost, I would like to express my sincere gratitude to my PhD supervisors, Prof. Yeo Yee-Chia and Prof. Ganesh Samudra for their patience and support throughout my time here at National University of Singapore (NUS). Their technical guidance and insights from our countless discussions has been invaluable. They are instrumental in instilling a strong work ethic and shaping my career goals. I am also very thankful for their time and efforts in guiding this dissertation. I would like to thank GLOBALFOUNDRIES Singapore and Economic Board of Singapore for funding my graduate studies through a graduate scholarship award. I am grateful to Dr. Lap Chan from Singapore University of Technology and Design and Dr. Ng Chee Mang from GLOBALFOUNDRIES Singapore for their discussions and trust in me. Their personal and professional advice has been invaluable. I have benefited greatly from their vast experience in the field of semiconductor technologies. I would also like to thank Prof. Chor Eng Fong and Prof. Hong Minghui for serving on my qualifying examination committee, both of whom have provided valuable feedback. I would like to acknowledge the technical staffs in Silicon Nano Device Laboratory (SNDL) specifically Mr Yong Yu Fu, Mr O Yan, Patrick and Boon Teck in providing technical and administrative support and keeping the cleanroom and lab running smoothly. Besides SNDL, a huge portion of my research and experiments were also conducted over at Institute of Microelectronics (IME), Institute of Materials Research and Engineering (IMRE) and Singapore Institute of Manufacturing Technology (SIMTech). I appreciate the support extended by the staffs at IME, IMRE and SIMTech. I would particularly like to thank Dr. Wang Xincai from SIMTech for all his support and assistance in laser annealing. Thanks also go out to Doreen and Poh Chong from IMRE for their help in SIMS and XRD characterization, respectively. Additionally, I would like to extend my appreciation to Dr. Thirumal Thanigaivelan, Dr. Todd Henry, Dr. Yuri Erokhin, Dr. Zhao Zhiyong and Dr. Chua i Lye-Hing from Varian Semiconductor for their timely discussions and ion implantation support, without which some of the work entailed in this thesis would not have been possible. I am grateful for the guidance and discussions from the many outstanding graduate students from SNDL. I would like to specially thank Jason for mentoring me in the initial phase of my research. Special thanks also go out to Zhou Qian, Eugene, Yang Yue, Cheng Ran, Yinjie, Liu Bin, Gong Xiao, Tong Yi and Guo Cheng for their discussions and support in experiments and measurements during the critical submission deadlines. I would also like to extend an enormous thanks to Rinus, Kian Ming, Andy, Hoong Shing, Kah Wee, Hock Chun, Lina, Alvin, Fangyue, Litao, Zhang Lu, Edwin, Shen Chen, Zhu Ming, Manu, Ivana, Phyllis, Sujith, Ashvini and many more for their friendship, support and lively and simulating discussions over a wide range of topics. They have made my time at NUS truly enjoyable. I would also like to express my deepest gratitude to my mum who has always been supportive and encouraging ever since I embarked on my graduate studies. I hope that I have made her proud. To my brother, Yida, thank you for the support and patience over these years. Lastly, but certainly not least, I want to thank my lovely girlfriend, Shu Rong for her encouragement and support throughout this journey. I am eternally grateful for her love and devotion all this while. Thank you. ii Table of Contents Table of Contents i Abstract v List of Tables viii List of Figures ix List of Symbols xxiv Chapter 1: Transistor Scaling and Need for Reduced Parasitic Resistance 1.1 Introduction 1.2 Challenges in CMOS Scaling 1.3 S/D Parasitic Resistance 1.3.1 Motivation for S/D Parasitic Resistance Reduction 1.3.2 Major Resistance Components of REXT and their Contributions to REXT 1.3.3 Contact Resistance Reduction: Concepts and Techniques 1.4 Objective of Dissertation 11 1.5 Thesis Organization 11 Chapter 2: Silicon-Carbon Source and Drain Stressors for Enhanced N-Channel MOSFET Performance 14 14 2.1 Introduction 2.2 Materials Characterization and Process Optimization of Silicon-Carbon 16 Source/Drain Stressors 2.2.1 Substrate and Test Structures Fabrication 16 2.2.2 Dopants Diffusion during Silicon-Carbon Formation 18 2.2.3 Conductivity of Silicon-Carbon Films 20 2.2.4 Impact of Annealing Temperature and Duration on Csub 21 2.2.5 Impact of Post-Annealing Treatment on Csub 24 2.3 Strained N-Channel FETs with Silicon-Carbon Source/Drain Stressors and Channel Proximate Stressors for Enhanced Performance 27 2.3.1 Channel Proximate Stressors for Enhanced Strain Effect in Channel Region 28 2.3.2 Process Integration and Device Fabrication 30 i 2.3.3 Impact of Process Thermal Budget on Si:C 32 2.3.4 Device Characterization and Analysis 34 2.4 40 Summary Chapter 3: Contact Engineering for Strained n-FinFETs with Silicon:Carbon Source/Drain Stressors featuring Sulfur Implantation and Segregation 41 41 3.1 Introduction 3.2 Material Characterization and Schottky-Barrier Analysis of S-Segregated 43 NiSi:C Films 3.2.1 Fabrication of Substrate and Test Structures 43 3.2.2 Thermal Stability of NiSi:C films with Pre-Silicided S+ Implantation 44 3.2.3 Phase Analysis of NiSi:C films with Pre-Silicided S+ Implantation 45 3.2.4 SIMS Analysis of NiSi:C films with Pre-Silicided S+ Implantation 47 3.2.5 Impact of Sulfur Segregation on Electron Schottky Barrier Height 47 3.3 Mechanisms for SBH Modulation in S-Segregated NiSi:C Films 49 3.4 Fabrication of Si:C S/D n-FinFETs 53 3.5 Device Characterization and Analysis 58 3.6 Summary 66 Chapter 4: Contact Engineering for Complementary FinFETs featuring Tellurium Segregated Platinum-Based Silicide Contacts 67 67 4.1 Introduction 4.2 Material Characterization and Schottky-Barrier Analysis of Te-Segregated 69 PtSi:C Films 4.2.1 Contact Test Structure Fabrication 69 4.2.2 Impact of Te Implantation Dose on Electron Schottky Barrier Height 70 4.2.3 SIMS Analysis of PtSi:C films with Pre-Silicided Te+ Implantation 72 4.2.4 Impact of Te Implantation Dose on Sheet Resistance of PtSi:C films 73 4.2.5 Impact of Te Segregation on PtSi:C Phase Formation 74 4.2.6 Impact of Te Segregation on PtSi:C/Si:C Interface Morphology 76 4.2.7 Impact of Te Segregation on Strain State of Si:C 76 ii 4.3 Mechanisms for SBH Modulation in Te-Segregated PtSi:C Films 77 4.4 Fabrication of N- and P-FinFETs 80 4.5 Device Characterization and Analysis 82 4.6 Process Concept and Integration Flow 91 4.7 Summary 93 Chapter 5: Novel Contact Engineering Solution Featuring Tellurium and Source/Drain Dopant Co-Implantation 94 94 5.1 Introduction 5.2 Material Characterization and Schottky-Barrier Analysis of Te-Segregated NiSi Films 95 5.2.1 Contact Test Structure Fabrication 96 5.2.2 S and Te Depth Profile after Elevated Temperature Annealing 96 5.2.3 Impact of Elevated Temperature Annealing on Electron Schottky Barrier Height of NiSi with S or Te Implantation 5.2.4 98 SIMS Analysis of NiSi film with Pre-Silicided Te+ Implantation and after Elevated Temperature Annealing 100 5.2.5 100 Impact of Te Implantation on Phase Formation and RS of NiSi films 5.3 Fabrication of N-FinFETs with Te-Segregated Contacts 102 5.4 Device Characterization and Analysis 104 5.4.1 Impact of Te Implantation on SCEs 104 5.4.2 Impact of the RC Reduction Approach on Device Performance 108 5.5 Integration Concept and Flow 113 5.6 Summary 113 Chapter 6: Contact Resistance Reduction with Aluminum Profile Engineering 115 115 6.1 Introduction 6.2 Schottky Barrier Height Tuning of Silicides by Aluminum Implantation and 116 Pulsed Excimer Laser Anneal 6.2.1 Contact Test Structure Fabrication 6.2.2 SBH Modulation with Al implantation and Laser-Anneal for Silicide Formation 118 iii 117 6.2.3 6.3 Summary 129 Aluminum Profile Engineering in NiSi Contacts with Carbon for SBH 130 Modulation 6.3.1 Contact Test Structure Fabrication 130 6.3.2 SBH Modulation with Al and C Implantations 131 6.3.3 SIMS Analysis of NiSi films with Pre-Silicided Al, C and Ge Implantations 133 6.3.4 Phase Analysis of NiSi Films with Various Implantations 136 6.3.5 Thermal Stability of NiSi Films with Various Implantations 136 6.3.6 Interface Morphology of NiSi Films with Various Implantations 138 6.3.7 Integration of New Contact Technology in Si:C S/D nFETs 139 6.3.8 Device Characterization and Analysis 141 6.3.9 Process Concept and Integration Flow 146 6.3.10 Summary 147 Chapter 7: Summary and Future Directions 148 7.1 Summary 148 7.2 Contributions of this Thesis 149 7.2.1 Si:C S/D Stressors for Enhanced N-Channel MOSFET Performance 7.2.2 Contact Engineering for Strained n-FinFETs with Silicon-Carbon Source/Drain Stressors featuring Sulfur Implantation and Segregation 7.2.3 149 150 Contact Engineering for Complementary FinFETs featuring Tellurium Segregated Platinum-based Silicide Contacts 7.2.4 151 Novel Contact Engineering Solution featuring Tellurium and Source/Drain Dopant Co-Implantation 151 7.2.5 152 7.3 Contact Resistance Reduction with Aluminum Profile Engineering 154 Future Directions 7.3.1 Further Insights into Process Optimization Windows 154 7.3.2 Extension to New Silicide Materials and Doping Techniques 155 7.3.3 Extension to Alternative Substrates 156 Appendix A: List of Publications 157 References 161 iv Abstract Source and Drain External Resistance Reduction for Advanced Transistors by Koh Shao Ming Doctor of Philosophy – Electrical and Computer Engineering National University of Singapore Aggressive geometrical scaling to increase the performance-to-cost ratio for integrated circuit based products has met immense technological challenges. High external resistance REXT has been identified as one of the obstacles for achieving continual improvement of speed performance in the scaling of field-effect transistor (FET) technology. Multiple-gate FETS such as FinFETs would be adopted at the 22 nm generation technology and beyond. The revolutionary change in the device architecture is by no means a trivial process. The issue of high REXT may be further exacerbated with the use of narrow fins and the further scaling of fin width in sub-22 nm technology generations. In aggressively scaled FinFETs, high REXT would compromise drive current. Contact resistance (RC) at the silicide/heavily-doped S/D interface is a significant contributor to REXT. Thus, exploration of solutions to minimize RC is important. RC is an exponential function of the effective Schottky barrier height (SBH) at the silicide/heavily-doped S/D interface. Lowering the SBH will lead to the reduction in RC and hence REXT. In this thesis, new materials and process integration concepts were developed to address the escalating dominance of high REXT, and especially RC, in advanced strained Si transistors and FinFETs. Through pre-silicided ion implantation of novel impurities at the source/drain (S/D) regions of the transistors, SBH modulation of the metal contacts was demonstrated. In particular, Sulfur (S) or Tellurium (Te) implantation and segregation were v explored to reduce the effective electron SBH (ΦBn) of silicide formed on n-type siliconcarbon (Si:C) layer. Our results show that by introducing S or Te at the silicide/Si:C interface, a low ΦBn of 110 meV and 120 meV for S- and Te-segregated metal contacts were achieved, respectively. To explain the observation, we proposed that the presence of S or Te near the silicide/Si:C interface and their behavior as charged donor-like trap states enhance the electron tunneling across the contact which reduces the ΦBn. Integration of these low ΦBn metal contacts in the S/D regions of strained n-FinFETs with Si:C S/D stressors results in significant REXT reduction and drive current (IDsat) improvement. This firmly demonstrates the effectiveness of the novel ΦBn engineering concepts. Various process integration concepts coupled with Te have also been developed and extensively characterized on transistors and/or contact structures. One alternative concept exploited Te segregation to engineer the ΦBn of a high workfunction metal (i.e platinum silicide (PtSi)). Integration of this new RC reduction technology for the S/D regions of strained n-channel FinFETs (n-FinFETs) with Si:C S/D stressors leads to ~62 % REXT reduction and ~22 % IDsat enhancement with no detrimental impact on other device performance parameters such as threshold voltages and off-state leakage current. PtSi has an intrinsically low hole SBH and is a potential silicide for p-FinFETs. The ability to selectively adjust the  ΦBn of PtSi with Te implantation for RC optimization for n-FinFETs opens up the possibility of having a single-metal-silicide dual-barrier-height solution for future CMOS FinFET technology. A second RC reduction approach where a shallow Te ion implantation was performed sequentially with deep S/D dopant implantation prior to S/D activation anneal was also examined. Introducing Te at the same process step as deep S/D dopant implantation for nFETs eliminates the need for an extra masking step to block Te implantation into the S/D regions of pFETs, therefore simplifying the CMOS process flow. Integration of this new RC reduction technology in n-FinFETs with Si S/D stressors leads to ~40 % REXT reduction and a slight ~6% improvement of ballistic efficiency Bsat. The improvement in Bsat and reduction in REXT leads to IDsat enhancement of ~30 %. vi implementation of embedded phosphorus-doped   SiC   stressors   in   SOI   nMOSFETs,”   in   VLSI Symp. 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Thomas, E.H.A, Granneman, “Improved  thermal  stability  of  Ni-silicides  on  Si:C  epitaxial  layers,” Microelectronic Engineering, vol 84, no 11, pp. 2542 - 2546, 2007. 179 [...]... with smaller WFin and LG 61 Fig 3.17 Plot of total resistance as a function of LG for control devices at different WFin Devices with a narrower WFin tend to have a higher electron mobility and higher REXT 62 Fig 3.18 Plot of total resistance RTotal between the source and drain as a function of LG for devices with and without S+ implantation The whiskers indicate the standard deviation... - rsat Channel backscattering coefficient - Rac Accumulation resistance Ω.cm RCH Channel resistance Ω.cm RC Silicide contact resistance Ω.cm REXT External series resistance Ω.cm ROV SDE-to-gate overlap resistance Ω.µm RS Sheet resistance RSD Deep S/D resistance Ω.cm RSDE SDE resistance Ω.cm Rsp Spreading resistance Ω.cm RTotal Total series resistance Ω.cm T Temperature K TSi Thickness of Si consumed... of this new RC reduction technology with strained nFETs with Si:C S/D stressors leads to ~53 % REXT reduction and ~18 % IDsat enhancement Enhanced device performance shown here, coupled with reported contact resistance reduction for pFETs with Al, opens new avenues to realize a novel single metal silicide integration solution with dual band edge barrier heights for selective contact resistance optimization... [(e) and (f)] 138 Fig 6.21 Key process steps for contact resistance reduction with Al ion implantation for strained nFETs with Si:C S/D stressors The Ge PAI and Al implantation steps were skipped for the control nFETs 139 Fig 6.22 Cross-sectional transmission electron microscopy (XTEM) images of the silicided S/D region of nFET with Si:C S/D stressors Uniform NiSi are formed... transistor with lattice-mismatched Si:C source/ drain stressors The lattice interaction of the Si:C S/D stressor with Si lattice at the heterojunction are plotted in the insets 4 1.3 S/D Parasitic Resistance 1.3.1 Motivation for S/D Parasitic Resistance Reduction One of the goals of CMOS scaling is to increase the IDsat to meet the demand for better switching efficiency, speed, and functionality in electronics... magnitude of the transistor drive current is determined by the total resistance (RTotal) between the source and drain The RTotal is contributed by both the S/D parasitic resistance REXT as well as the channel resistance RCH [Fig 1.3(a)] With the aggressively scaling of LG, RCH is reduced due to shorter distance between the source and drain regions The strain effect due to the S/D stressors also increases... cause phase transformation in NiSi 136 Fig 6.19 NiSi sheet resistance (Rs) as a function of silicidation temperature Presence of C and Al improves the thermal stability of NiSi Thermal stability is maintained even at silicidation temperature of 700 °C for sample with C and/ or Al implantations Delay xxi in formation of low resistivity NiSi is observed for samples with C and/ or Al implantations... 6 Fig 1.6 The major resistance components of REXT The REXT is equivalent to the series and parallel combination of ROV, RSDE, RSD, and RC 7 Fig 1.7 Relative contributions of different resistance components to REXT for (a) nFETs and (b) pFETs The RC is a major contributor to the REXT for devices with small gate length [55] 8 Fig 1.8 Energy band diagrams across the silicide/semiconductor... % EA Activation energy for diffusion eV EC Conduction band eV Ef Fermi-level eV EV Valence band eV ξ Maximum electric field V/cm GD Drain conductance S Gm,ext Extrinsic linear transconductance S Gm,int Intrinsic linear transconductance S h Planck’s  constant J.s HFin Fin height nm IDlin Linear drain current µA/µm IDS Drain current A/µm IDsat Saturation drain current µA/µm If Forward diode current A... control PtSi:C film without Te+ implantation and (b) PtSi:C film with 2 × 1014 cm-2 dose of Te+ implantation Te+ implantation formed an amorphized region, which was consumed by the silicidation process performed at 550 oC for 30 s A ~15 nm thick PtSi:C was formed The interface morphology for PtSi:C with and without Te+ implant is similar, indicating that Te+ implant and segregation does not affect the PtSi:C/Si:C . 2012 SOURCE AND DRAIN EXTERNAL RESISTANCE REDUCTION FOR ADVANCED TRANSISTORS KOH SHAO MING A THESIS SUBMITTED FOR THE DEGREE. SOURCE AND DRAIN EXTERNAL RESISTANCE REDUCTION FOR ADVANCED TRANSISTORS KOH SHAO MING . Silicon-Carbon Source and Drain Stressors for Enhanced N-Channel MOSFET Performance 14 2.1 Introduction 14 2.2 Materials Characterization and Process Optimization of Silicon-Carbon Source/ Drain Stressors