MOSFET MODELING FOR VLSI SIMULATION - Theory and Practice Episode 9 potx

... Lett., EDL-2, pp. 46 6-4 68 ( 199 0). [80] N. Kotani and S. Kawazu, ‘Computer analysis of punch-through in MOSFETs’, Solid-state Electron., 22, pp. 6 3-7 0 ( 197 9). ED-36, pp .96 3 -9 67 ( 198 9). ( 199 0). ... Masetti. ‘A .CAD-oriented analytical MOSFET model for 34 5-3 55 ( 197 8). 99 1 -9 97 ( 197 9). L_. high-accuracy applications’, IEEE Trans. Computer-Aided De...

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... case permission to photocopy is not required from the publisher. ISBN-13 97 8 -9 8 1-2 5 6-8 6 2-5 ISBN- 10 98 1 -2 5 6-8 62-X Disclaimer: This book was prepared by the authors. Neither the Publisher ... Measurements 402 9. 1 Data Acquisition 403 9. 1.1 Data for DC Models 410 9. 1.2 Data for AC Models 414 9. 1.3 MOS Capacitor C-V Measurement 418 9. 2 Gate-Oxide...

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... form that at first glance appears different. 6.7 Short-Geometry Models 3 - 2- - a 9- W- (7 5 9 1.75 Q t- 6 !I 3 t- 6 fJY 0.5 293 I = 1.31 x 104V/cm a= 1.13 0 - ... needs 2- or 3-D analysis to account for short-channel and/ or narrow-width behavior. However, for circuit models we invariably modify the 1-D equations developed earl...

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... 10.6 Parameter Extraction Using Optimizer 53 1 lo-' 1 0-2 1 0-3 9 lo4 I 0-5 1 0-6 1 lo-' 1 0-2 1 0-3 9 lo4 I 0-5 1 0-6 1 0-7 10" 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 ... ED-30, pp. 121 9- 1 228 ( 198 3). [6] P. Yang and P. K. Chatterjee, ‘An optimal parameter extraction program for MOSFET models’, IEEE Trans. Electron Devic...

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... 198 2 and given in many textbooks) by as much as 50% for boron doped p-type silicon. For phosphorous doped n-type silicon the difference is only 1574. Curves for n-type are lower than p-doped ... conditions is given by the Fermi-Dirac At 77K ni for silicon is -1 0-2 0cm-3, while at 400K its value is -1 O'*~m-~ 28 2 Basic Semiconductor and pn Jun...

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... Prentice Hall, Englewood Cliffs, NJ, 197 5. 22, pp. 42 3-4 30 ( 197 9). pp. 146 4-1 474 ( 198 9). pp. 29 2-2 95 ( 198 2). 92 3 MOS Transistor Structure and Operation I I I 16'1 '; ... Electron. Devices, ED-18, pp. 17 8-1 95 ( 197 1). [28] H. G. Poon and H. K. Gummel, Modeling of emitter capacitance’, Proc. IEEE (Lett.), 57, pp.218 1-2 182 ( 19...

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... n-channel and p-channel MOS devices for VLSI , Solid-state Electron., 26, pp. 96 9- 9 86 ( 198 3). [I41 G. Baccarani, M. R. Wordeman, and R. H. Dennard, ‘Generalized scaling theory pp. 57 1-5 76 ( 198 3). ... Structure and Operation ~i 1; L 6i! - - - - - - - - - Fig. 3.3 1 Cross-section showing overlap capacitances between the...

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... df Qh Y <h VTO nMOST p-type - +- +++ pMOST n-type - -+ - (for metals and n+ polysilicon gate) - - (for metals and n+ polysilicon gate) + (for p+ polysilicon gate) (tax ... simulation of MOS capacitance’, IEEE Trans. Computer-Aided Design, CAD-2, pp. 11 1-1 16 ( 198 3). 23 8-2 41 ( 198 8). 153 9- 1544 ( 199 0). 26, pp. 36...

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... >" ;- I 5 0.4 lY I bO.3 195 1'1'1'1'1~1'1'1~ I - Nb = 2 X 10'"cm-3 - - - - - W=20 m - f"\L "A&ING - I I 1 ... both pMOST and nMOST devices, a general expression for the threshold voltage can be written as (5.63) where the + and - signs are for n- and p-cha...

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... ED-32, pp. 100 1-1 002 ( 198 5). [ 59] N.D. Arord and M. Sharma Modeling the anomalous threshold voltage behavior of submicron MOSFETs’, IEEE Electron Devices Lett., EDL-13, pp. 9 2 -9 4 ( 199 2). [60] ... pp. 63 9- 6 49 ( 198 4). [64] S. S. Chuang and C. T. Sah, ‘Threshold voltage models of the narrow-gate effect in micron and submicron MOSFETs’, Solid-state Electron., 3...

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