Tài liệu Circuits & Electronics P14 pptx

6.002 Fall 2000 Lecture 1 14 6.002 CIRCUITS AND ELECTRONICS State and Memory 6.002 Fall 2000 Lecture 2 14 C + – C v I v + – R 1 Recall Reading: Sections 10.3, 10.5, and 10.7 Review Vv II 0t ≥ = for () RC t IIC eVVv − −+= () C v 0 () C v 0 6.002 Fall 2000 Lecture 3 14 t I v 0 t C v 0 I V ( ) 0 C v I v I V This lecture will dwell on the memory property of capacitors. For the RC circuit in the previous slide Notice that the capacitor voltage for is independent of the form of the input voltage before . Instead, it depends only on the capacitor voltage at , and the input voltage for . 0t ≥ 0t ≥ 0t = 0t = 0t ≥ () RC t IIC eVVv − −+= () C v 0 6.002 Fall 2000 Lecture 4 14 VCq = for linear capacitors, capacitor voltage V is also state variable state variable, actually State : summary of past inputs relevant to predicting the future State 6.002 Fall 2000 Lecture 5 14 ()() RC t ICIC eVvVv − −+= 0 1 Back to our simple RC circuit ( ) ( )( ) tvvfv ICC ,0 = State Summarizes the past input relevant to predicting future behavior 6.002 Fall 2000 Lecture 6 14 We are often interested in circuit response for  zero state v C (0) = 0  zero input v I ( t ) = 0  zero input response or ZIR () RC t CC evv − = 0 RC t IIC eVVv − −= Correspondingly,  zero state response or ZSR 2 3 State 6.002 Fall 2000 Lecture 7 14 Why memory? Or, why is combinational logic insufficient? One application of STATE DIGITAL MEMORY Examples  Consider adding 6 numbers on your calculator  “Remembering” transient inputs 2 + 9 + 6 + 5 + 3 + 8 M+ 6.002 Fall 2000 Lecture 8 14 A 1-bit memory element Memory Abstraction Remembers input when store goes high. Like a camera that records input (d IN ) when the user presses the shutter release button. The recorded value is visible at d OUT . IN d OUT d store M IN d store OUT d remembers the 1 The 6.004 view The NEC View ☺ $ ¥ 6.002 Fall 2000 Lecture 9 14 A First attempt Building a memory element … store storage node d IN d OUT C * 6.002 Fall 2000 Lecture 10 14 A Stored value leaks away store pulse width >> R ON C Building a memory element … CR t C L ev − ⋅= 5 5 ln OH L V CRT −= 2 from v C t T 5V V OH v C store = 1 d IN d OUT C * v C store = 0 d IN d OUT C * R L . 6.002 Fall 2000 Lecture 1 14 6.002 CIRCUITS AND ELECTRONICS State and Memory 6.002 Fall 2000 Lecture 2 14 C + – C v. 6.002 Fall 2000 Lecture 10 14 A Stored value leaks away store pulse width >> R ON C Building a memory element … CR t C L ev − ⋅= 5 5 ln OH L V CRT