Tài liệu Circuits & Electronics P23 pptx

6.002 Fall 2000 Lecture 1 23 6.002 CIRCUITS AND ELECTRONICS Energy, CMOS 6.002 Fall 2000 Lecture 2 23  Reading: Section 11.5 of A & L. S V + – 1 R C 2 R 1 S 2 S f TTT 1 21 =+= fCVP S 2 = T 1 : closed T 2 : open open closed ONL S RR V P + = 2 O v S V ON R L R I v  Review 6.002 Fall 2000 Lecture 3 23 Inverter — O v I v C S V L R ON R fCV R V P S L S 2 2 2 += related to switching capacitor. independent of f. MOSFET ON half the time. STATIC P DYNAMIC P constant time "RC" 2 T RR ONL >> >> Square wave input f T 1 = Demo Review In standby mode, half the gates in a chip can be assumed to be on. So per gate is still . STATIC P L 2 S R2 V In standby mode, f Æ 0 , so dynamic power is 0 6.002 Fall 2000 Lecture 4 23 fCV R V P S L S 2 2 2 += Chip with 10 6 gates clocking at 100 MHz V5V,10100f,K10RF,f1C S 6 L =×=Ω== problem ! 1.25KWatts 2.5Watts not bad + • independent of f • also standby power (assume ½ MOSFETs ON if f Æ 0) • must get rid of this! • α f • αV S 2 reduce V S 5V Æ 1V 2.5V Æ 150mW [ ] watts5.2milliwatts25.110 6 μ += ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ ×××+ ×× = − 6215 3 2 6 10100510 10102 5 10P gates Review 6.002 Fall 2000 Lecture 5 23 How to get rid of static power Intuition: O v S V ON R L R I v high low i idea ! O v S V I v high low S V L R O v I v low off MOSFET high 6.002 Fall 2000 Lecture 6 23 New Device PFET •N-channel MOSFET (NFET) D S G on when v GS ≥ V TN off when v GS < V TN e.g. V TN = 1V • P-channel MOSFET (PFET) on when v GS ≤ V TP off when v GS > V TP e.g. V TP = -1V S D G ON when less than 4V 5V 6.002 Fall 2000 Lecture 7 23 Consider this circuit: S D G D S G O v I v + – S V PU = pull up PD = pull down works like an inverter! IN OUT 6.002 Fall 2000 Lecture 8 23 Consider this circuit: v I = 0V (input low) V5 v O = V5V S = V0v I = + – p ON R v I = 5V (input high) V0 v O = V5V S = V5v I = + – n ON R Called “CMOS logic” Complementary MOS (our previous logic was called “NMOS”) works like an inverter! IN OUT 6.002 Fall 2000 Lecture 9 23 O v I v S V C t T I v T f 1 = From fCVP S 2 = Key: no path from V S to GND! no static power! Let’s compute DYNAMIC P S V + – p ON R C n ON R closed for v I low closed for v I high 6.002 Fall 2000 Lecture 10 23 For our previous example — 1,MHz100f,V5VF,f1C S === “keep all else same” fCVP S 2 = 6215 10100510 ×××= − gateperμwatts5.2= chipgate10forμwatts5.2 6 =P P PIII? ~240 watts1.2 GHz8x10 6 PIV? ~1875 watts3 GHz25x10 6 PII? ~30 watts 600 MHz2x10 6 PII? ~15 watts 300 MHz2x10 6 Pentium? ~2.5 watts 100 MHz 10 6 f Gates ga s p ! . MOSFET ON half the time. STATIC P DYNAMIC P constant time "RC" 2 T RR ONL >> >> Square wave input f T 1 = Demo Review In standby mode,. Fall 2000 Lecture 1 23 6.002 CIRCUITS AND ELECTRONICS Energy, CMOS 6.002 Fall 2000 Lecture 2 23  Reading: Section 11.5 of A & L. S V + – 1 R C 2 R