A B C D E COMPAL CONFIDENTIAL MODEL NAME : ZAM81 LA-A914P PCB NO : BOM P/N : C yb er Fo ru m ru GPIO MAP: 3.1 Huston 15" DSC Entry 2 Broadwell U 2013 08 20 REV : 0.1 (X00) @ : Nopop Component EMC@ : EMI, ESD and RF Component @EMC@ : EMI, ESD and RF Nopop Component XDP@ : XDP Component CONN@ : Connector Component 3 4 MB PCB Part Number Description DA8000Z8000 PCB 13N LA-A914P REV0 MB DSC NONDOCK DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT A B C D Title SCHEMATICS,AA914 ZAM81 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RB Sheet E of 55 A B C D E Reverse Type Houston 15 DSC Entry Dock Block Diagram Memory BUS (DDR3L) 1333/1600MHz DDR3L-DIMM X2 BANK 0, 1, 2, eDP CONN eDP PAGE 18 19 PAGE 23 1 NVIDIA N15S-GT VRAM DDR3 x4 USB2.0[4] PCIE5 Gen2 x4Lane PAGE 23 PAGE 40~44 PAGE 45~46 USB2.0[5] INTEL HDMI DDI1 HDMI Level Shifter PS8401A PAGE 24 PAGE 24 BROADWELL U PAGE 26 VGA PAGE 23 USB POWER SHARE IT6513FN DP DP to VGA PS8338B DP Sw DDI2 PAGE 25 PAGE 26 USB2.0[1]_PS USB3.0/2.0 PS PAGE 32 PAGE 32 USB VGA CONN Camera TPS2544 USB2.0[1] C yb er Fo ru m ru HDMI CONN LCD Touch USB2.0[3] USB3.0[4] PAGE 6~17 Card reader SD4.0 O2 Micro OZ777FJ2LN PAGE 29 PAGE 29 PCIE1 USB2.0[0] USB3.0[1] USB3.0/2.0 PAGE 31 PCIE5_L0 PCIE4 Intel Clarkville I218LM PAGE 28 WLAN/BT/ WIGIG PAGE 30 Transformer WIGIG_DP PAGE 28 Combo Jack PAGE 21 PAGE 21 Dig MIC PAGE 23 Single DMIC 64M 4K sector Trough eDP Cable PAGE 21 W25Q32BVSSIQ 32M 4K sector SMSC SIO ECE1099 USB2.0[2] PAGE 21 W25Q64CVSSIQ LPC PCIE3 INT.Speaker HDA Codec ALC3235 SPI PCI Express BUS USB3.0[2] PAGE 31 HD Audio I/F SATA1 USB3.0 Redriver PS8713B PAGE 32 USB3.0/2.0 WIGIG_DP Trough eDP Cable PAGE 7 LID SWITCH SATA REPEATER PI3EQX6741STZDEX PAGE 20 PAGE 20 BC BUS PAGE 27 SMSC KBC MEC5085 CPU XDP Port PAGE 9 Automatic Power Switch (APS)PAGE 9 PAGE 37 Free Fall sensor FAN CONN PAGE 36 PAGE 27 KB/TP CONN PAGE 28 USH CONN Discrete TPM AT97SC3204 PAGE 35 RJ45 PAGE 39 SATA3 Conn PAGE 20 PAGE 36 shorten solution Smart Card RFID DC/DC Interface Power On/Off SW & LED USH BCM5882 TDA8034HN DELL CONFIDENTIAL/PROPRIETARY Fingerprint CONN FP_USB PAGE 29 A Compal Electronics, Inc USB2.0[6] PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT USH board B C D Title SCHEMATICS,MB AA914 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RB Sheet E of 55 POWER STATES SLP S3# SLP S4# SLP S5# SLP A# S0 (Full ON) / M0 HIGH HIGH HIGH HIGH D S3 (Suspend to RAM) / M3 LOW HIGH HIGH S4 (Suspend to DISK) / M3 LOW LOW S5 (SOFT OFF) / M3 LOW S3 (Suspend to RAM) / M-OFF C M PLANE SUS PLANE RUN PLANE ON ON ON ON ON HIGH ON ON ON OFF OFF HIGH HIGH ON ON OFF OFF OFF LOW LOW HIGH ON ON OFF OFF OFF LOW HIGH HIGH LOW ON OFF ON OFF OFF S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF OFF OFF S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF OFF OFF PM TABLE power plane ALWAYS PLANE +5V_ALW +3.3V_SUS +5V_RUN +3.3V_M +3.3V_M +3.3V_ALW +1.35V_MEM +3.3V_RUN +1.05V_M +1.05V_M +3.3V_ALW_PCH +3.3V_RTC_LDO PCIE CLOCKS USB3.0 SATA DESTINATION USB3.0 JUSB1 >Rear left USB3.0 JUSB3 >Right PCIE USB3.0 MMI (CARD READER) PCIE USB3.0 JUSB2 >Rear Right PCIE LOM PCIE WLAN PCIE GPU/WIGIG D C yb er Fo ru m ru Signal State +0.675V_DDR_VTT PCIE (M-OFF) SATA WIGI/Express SATA mSATA/PCIE SATA HDD SATA DOCK C +1.05V_RUN +VCC_CORE DESTINATION USB PORT# State B S0 ON S3 ON S5 S4/AC ON S5 S4/AC doesn't exist OFF ON ON ON ON ON OFF ON OFF OFF OFF ON OFF OFF OFF OFF OFF BDW ULT need to update Power Status and PM Table USH JUSB1 JUSB3 WLAN + BT JUSB2 Touch Screen CAMERA USH WWAN BIO NA B A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT Title SCHEMATICS,MB AA914 Size Document Number Rev A 4019RB Date: Thursday, November 14, 2013 Sheet of 55 MPHYP_PWR_EN SI3456 (QZ6) D D EN_INVPWR ADAPTER FDC654P (QV1) +BL_PWR_SRC +1.05V_MODPHY RUN_ON SY8208DQNC +1.05V_M C yb er Fo ru m ru (PU300) +1.05V_PEX_VDD 3V3_MAIN_EN BATTERY +PWR_SRC 3V3_MAIN_EN TPS22965 (UV15) RT8813 ALWON C CHARGER +3.3V_RUN_GFX +GPU_CORE (PU600) TPS51285 (PU100) +5V_ALW C +VCC_CORE +1.35V_MEM DGPU_PWR_ON SI416 (QV83) 0.675V_DDR_VTT_ON SUS_ON H_VR_EN B RT8207 (PU200) +3.3V_LAN +0.675V_DDR_VTT TPS22966 (UZ3) +3.3V_WLAN +3.3V_ALW_PCH +3.3V_SUS TPS22966 (UZ2) +3.3V_M APL3512 (UV24) RUN_ON RUN_ON EN_LCDPWR RUN_ON A_ON SUS_ON AUX_EN_WOWL TPS22966 (UZ8) +LCDVDD +1.05V_RUN +3.3V_RUN A LP2301ALT1G (QZ1) +3.3V_CAM USB_PWR_SHR_EN# +5V_RUN DGPU_PWR_EN +USB_LEFT_PWR +USB_RIGHT_PWR +5V_TS +3.3V_GFX_AON A DELL CONFIDENTIAL/PROPRIETARY +1.35V_MEM_GFX Compal Electronics, Inc PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT B LP2301ALT1G (QV8) LP2301ALT1G (QV86) G547I2P81U (UI2) G547I2P81U (UI1) +5V_USB_CHG_PWR 3.3V_TS_EN USB_PWR_EN2# USB_PWR_EN1# TPS2544 (UI3) TPS22966 (UZ9) 3.3V_CAM_EN# TPS51622 (PU500) PCH_ALW_ON SIO_SLP_LAN# +3.3V_ALW Title SCHEMATICS,MB AA914 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RB Sheet of 55 2.2K SMBUS Address [0x9a] +3.3V_ALW_PCH 2.2K AP2 MEM_SMBCLK AH1 MEM_SMBDATA 202 2N7002 DIMMA 200 2N7002 1K 202 BDW D +3.3V_ALW_PCH 1K AN1 AU3 LOM 53 SML1_SMBCLK 3A 31 AK1 SML1_SMBDATA A5 28 SML0DATA 2.2K XDP 51 2.2K +3.3V_ALW_PCH B6 10K C yb er Fo ru m ru AH3 SML0CLK 2.2K 3A 2.2K B4 DOCK_SMB_CLK A3 DOCK_SMB_DAT 1A 1A D DIMMB 200 +3.3V_RUN 10K +3.3V_ALW G Sensor 2.2K C 2.2K 1B B5 LCD_SMBCLK A4 LCD_SMDATA 1B C +3.3V_ALW 2.2K KBC 2.2K 1C 1C A56 B59 PBAT_SMBCLK PBAT_SMBDAT +3.3V_ALW 100 ohm 100 ohm BATTERY CONN 2.2K 2.2K A50 MEC 5085 1E B53 1E USH_SMBCLK USH_SMBDAT B +3.3V_SUS M9 L9 USH B 2.2K 2.2K 2B A49 CARD_SMBCLK 2B B52 CARD_SMBDAT +3.3V_ALW 10K 10K B50 1G A47 1G CHARGER_SMBCLK CHARGER_SMBDAT +3.3V_ALW Charger 2.2K 2.2K 2D B7 A 2D A7 +3.3V_ALW BAY_SMBDAT A BAY_SMBCLK 2.2K 2.2K 2A 2A B48 B49 GPU_SMBDAT DELL CONFIDENTIAL/PROPRIETARY +3.3V_ALW Compal Electronics, Inc PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT GPU_SMBCLK Title SCHEMATICS,MB AA914 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RB Sheet of 55 DSC SATA port Service Mode Switch: Add a switch to ME_FWP signal to unlock the ME region and allow the entire region of the SPI flash to be updated using FPT +3.3V_ALW_PCH RC2 1K_0402_5% SW1 ME_FWP_EC ME_FWP 3 G2 G1 SATA1 PCB E-Dock HDD H12 UMA NA HDD H12 Entry E-Dock HDD H14 DSC M2 3042 SATA-Cache(no HCA) E-Dock HDD H14 UMA M2 3042 2nd PCIe Lane for PCIe Cache NA HDD H14D_En NA NA HDD H14U_En NA SATA2/PCIE6 L1 SATA3/PCIE6 L0 C yb er Fo ru m ru ME_FWP=LOW ENABLE ME (DEFAULT) > Pin1 & Pin3 short =HIGH DISABLE ME (ME can update) > Pin2 & Pin3 short CC1 1 2 CC2 18P_0402_50V8J 1M_0402_5% RC10 RC8 2 20K_0402_5% 20K_0402_5% YC1 32.768KHZ_12.5PF_Q13FC135000040 1U_0402_6.3V6K 1 2 @ CMOS1 SHORT PADS~D 1U_0402_6.3V6K CC4 CMOS place near DIMM CMOS_CLR1 TPM setting Shunt Clear ME RTC Registers Shunt Clear CMOS Keep ME RTC Registers Open Keep CMOS +1.05V_M 2 PCH_JTAG_TDI 51_0402_5% PCH_JTAG_TDO 51_0402_5% PCH_JTAG_TMS 51_0402_5% PCH_JTAG_JTAGX 1K_0402_1% RC15 RC16 @ RC18 @ RC21 HDA for Codec H15 DSC M2 3042 SATA-Cache(no HCA) E-Dock HDD H15 UMA M2 3042 2nd PCIe Lane for PCIe Cache NA HDD H15D_En NA NA HDD H15U_En NA PCH_AZ_CODEC_SYNC PCH_AZ_CODEC_RST# PCH_AZ_CODEC_BITCLK PCH_AZ_CODEC_SDIN0 M2 3042 (HCA & SATA-Cache) Express card contact to WWAN contact to Express card RTCX1 RTCX2 INTRUDER INTVRMEN SRTCRST RTCRST SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3 SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3 RTC RC11 SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2 SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2 PCH_AZ_BITCLK PCH_AZ_SYNC PCH_AZ_RST# PCH_AZ_CODEC_SDIN0 PCH_AZ_SDOUT 1K_0402_5% AW8 AV11 AU8 AY10 AU12 AU11 AW10 AV10 AY8 PCH_JTAG_TRST# PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_JTAGX PCH_JTAG_TRST# PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS AU62 AE62 AD61 AE61 AD62 AL11 AC4 AE63 AV2 C HDA_BCLK/I2S0_SCLK HDA_SYNC/I2S0_SFRM HDA_RST/I2S_MCLK AUDIO HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_SDO/I2S0_TXD HDA_DOCK_EN/I2S1_TXD HDA_DOCK_RST/I2S1_SFRM I2S1_SCLK SATA SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1 SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1 SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0 SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0 SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37 PCH_TRST PCH_TCK PCH_TDI PCH_TDO PCH_TMS RSVD RSVD JTAGX RSVD JTAG SATA_IREF RSVD RSVD SATA_RCOMP SATALED J5 H5 B15 A15 J8 H8 A17 B17 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 SATA HDD J6 H6 B14 C15 F5 E5 C17 D17 V1 U1 V6 AC1 A12 L11 K10 C12 U3 PCIE_PRX_WIGIGTX_N6_L0 PCIE_PRX_WIGIGTX_P6_L0 PCIE_PTX_WIGIGRX_N6_L0 PCIE_PTX_WIGIGRX_P6_L0 for WIGIG (WLAN) MPCIE_RST# B HDD_DET# SATA2_PCIE6_L1 mCARD_PCIE#_SATA_R +PCH_ASATA3PLL SATA_COMP SATA_ACT# SATA_ACT# +3.3V_RUN LANCLK_REQ# RPC18 MCARD_PCIE#_SATA_R MPCIE_RST# HDD_DET# 10K_8P4R_5% SATA Impedance Compensation +PCH_ASATA3PLL SATA_COMP 3.01K_0402_1% RC17 CAD note: Place the resistor within 500 mils of the PCH. Avoid routing next to clock pins A CC5 @EMC@ 27P_0402_50V8J DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT Reserve for EMI SATA2/PCIE6_L1 contact to WWAN M2 3030 WIGIG SATA3/PCIE6 L0 contact to WLAN BDW_ULT_DDR3L PCH_RTCRST# ME_FWP contact to WWAN M2 3030 WIGIG contact to WLAN RC19 M2 3042 (HCA & SATA-Cache) D NA PCH_AZ_SDOUT 33_0402_5% PCH_AZ_SYNC RC20 33_0402_5% PCH_AZ_RST# RC22 33_0402_5% EMC@ PCH_AZ_BITCLK RC23 33_0402_5% PCH_AZ_CODEC_SDOUT SATA2/PCIE6_L1 contact to WWAN M2 3030 WIGIG SATA3/PCIE6 L0 contact to WLAN M2 3030 WIGIG contact to WLAN BDW-ULT-DDR3L_BGA1168 OF 19 PCH_JTAG_TCK 51_0402_5% AW5 AY5 AU6 AV7 AV6 AU7 CMOS setting Open RC14 INTRUDER# PCH_INTVRMEN SRTCRST# PCH_RTCRST# contact to WWAN NA HDD UC1E PCH_RTCX2 CC3 A M2 3042 (HCA & SATA-Cache) PCH_RTCX1 RC7 10M_0402_5% RC9 ME_CLR1 0_0402_5% @ RC4 18P_0402_50V8J +RTC_CELL PCH_RTCX1_R 2 RC1 330K_0402_5% FLASH DESCRIPTOR SECURITY OVERRIDE INTVRMEN INTEGRATED SUS 1.05V VRM ENABLE High Enable Internal VRs Low Enable External VRs NA E-Dock ME_FWP PCH has internal 20K PD PCH_INTVRMEN B M2 3042 2nd PCIe Lane for PCIe Cache SS3-CMFTQR9_3P +RTC_CELL C SATA0 D Title SCHEMATICS,MB AA914 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RB Sheet of 55 +3.3V_RUN +3.3V_ALW_PCH BDW_ULT_DDR3L LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME# LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME# PCH_SPI_CLK D PCH_SPI_CS2# PCH_SPI_DO PCH_SPI_DIN PCH_SPI_CLK PCH_SPI_CS0# PCH_SPI_CS1# PCH_SPI_CS2# PCH_SPI_DO PCH_SPI_DIN PCH_SPI_DO2 PCH_SPI_DO3 AU14 AW12 AY12 AW11 AV12 LAD0 LAD1 LAD2 LAD3 LFRAME AA3 Y7 Y4 AC2 AA2 AA4 Y6 AF1 LPC SMBUS SPI_CLK SPI_CS0 SPI_CS1 SPI_CS2 SPI_MOSI SPI_MISO SPI_IO2 SPI_IO3 SPI SMBALERT/GPIO11 SMBCLK SMBDATA SML0ALERT/GPIO60 SML0CLK SML0DATA SML1ALERT/PCHHOT/GPIO73 SML1CLK/GPIO75 SML1DATA/GPIO74 CL_CLK CL_DATA CL_RST C-LINK AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3 AF2 AD2 AF4 PCH_SMB_ALERT# MEM_SMBCLK MEM_SMBDATA MEM_SMBCLK SML0_SMBCLK SML0_SMBDATA SML0_SMBCLK SML0_SMBDATA PCH_GPIO73 SML1_SMBCLK SML1_SMBDATA SML1_SMBCLK SML1_SMBDATA PCH_CL_CLK1 PCH_CL_DATA1 PCH_CL_RST1# UC1G RPC14 DDR_XDP_WAN_SMBCLK SML1_SMBCLK MEM_SMBCLK MEM_SMBDATA SML1_SMBDATA QC1A DMN66D0LDW-7_SOT363-6 2.2K_0804_8P4R_5% MEM_SMBDATA DDR_XDP_WAN_SMBDAT SML0_SMBCLK 1K_0402_5% SML0_SMBDATA 1K_0402_5% QC1B DMN66D0LDW-7_SOT363-6 PCH_CL_CLK1 PCH_CL_DATA1 PCH_CL_RST1# 2 RC33 D RC34 +3.3V_SPI BDW-ULT-DDR3L_BGA1168 OF 19 64Mb Flash ROM SOFTWARE TAA SPI_CLK64 UC2 SPI_PCH_CS0# RC35 0_0402_5% SPI_PCH_DO2 RC38 33_0402_5% SPI_PCH_CS0#_R SPI_DIN64 SPI_PCH_DO2_64 C yb er Fo ru m ru SPI_CLK32 2 1 /CS DO(IO1) /WP(IO2) GND VCC /HOLD(IO3) CLK DI(IO0) SPI_PCH_DO3_64 SPI_CLK64 SPI_DO64 W25Q64FVSSIQ_SO8 RPC11 @EMC@ CC10 @EMC@ RC62 33P_0402_50V8J 33_0402_5% @EMC@ @EMC@ CC9 RC61 33P_0402_50V8J 33_0402_5% +3.3V_SPI C CC6 0.1U_0402_25V6 SPI_PCH_DIN SPI_PCH_DO SPI_PCH_CLK SPI_PCH_DO3 1 SPI_PCH_DO2 1K_0402_5% SPI_PCH_DO3 1K_0402_5% RC29 RC31 SPI_DIN64 SPI_DO64 SPI_CLK64 SPI_PCH_DO3_64 +3.3V_SPI 32Mb Flash ROM 33_0804_8P4R_5% SPI_PCH_CS1# VPRO@ RPC12 SPI_PCH_DO3 SPI_PCH_CLK SPI_PCH_DO SPI_PCH_DIN VPRO@ RC50 SPI_PCH_DO2 0_0402_5% RC55 VPRO@ 33_0402_5% SPI_PCH_CS1#_R SPI_DIN32 SPI_PCH_DO2_32 UC3 SPI_PCH_DO3_32 SPI_CLK32 SPI_DO32 SPI_DIN32 VPRO@ CC7 0.1U_0402_25V6 VPRO@ /CS DO/IO1 /WP/IO2 GND VCC /HOLD/IO3 CLK DI/IO0 SPI_PCH_DO3_32 SPI_CLK32 SPI_DO32 W25Q32FVSSIQ_SO8 C @EMC@ CC13 MMI > Reserve for EMI CLK_PCIE_MMI# CLK_PCIE_MMI MMICLK_REQ# +3.3V_RUN +3.3V_RUN 10/100/1G LAN > WLAN (NGFF1) > RPC6 MMICLK_REQ# WIGIGCLK_REQ# PCH_GPIO52 HDD_FALL_INT GPU > 10K_8P4R_5% WGIG (NGFF1) > B PCB PCIE1 H12 UMA SD card PCIE5 WLAN WIGIG LOM RC66 10K_0402_5% CLK_PCIE_LAN# CLK_PCIE_LAN LANCLK_REQ# CLK_PCIE_GFX# CLK_PCIE_GFX GFXCLK_REQ# +3.3V_RUN CLK_PCIE_WIGIG# CLK_PCIE_WIGIG WIGIGCLK_REQ# PCIE6 C43 C42 U2 MMICLK_REQ# CLK_PCIE_WLAN# CLK_PCIE_WLAN WLANCLK_REQ# PCIE2 PCIE3 PCIE4 NA UC1F BDW_ULT_DDR3L PCH_GPIO19 B41 A41 Y5 LANCLK_REQ# C41 B42 AD1 WLANCLK_REQ# B38 C37 N1 A39 B39 U5 RC68 10K_0402_5% B37 A37 T2 WIGIGCLK_REQ# CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 PCIECLKRQ0/GPIO18 XTAL24_IN XTAL24_OUT RSVD RSVD DIFFCLK_BIASREF CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 PCIECLKRQ1/GPIO19 CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 PCIECLKRQ2/GPIO20 TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8 CLOCK SIGNALS CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 PCIECLKRQ3/GPIO21 CLKOUT_LPC_0 CLKOUT_LPC_1 CLKOUT_ITPXDP CLKOUT_ITPXDP_P CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 PCIECLKRQ4/GPIO22 NA LOM WLAN WIGIG NA H14 DSC SD card NA LOM WLAN GPU WIGIG WLAN WIGIG RC74 22_0402_5% PCI_CLK_LPC_1 EMC@ RC67 22_0402_5% CLK_PCI_MEC H14U_En SD card NA NA LOM LOM WLAN WLAN GPU CLK_PCI_LPDEBUG H15 DSC SD card NA LOM WLAN RC224 RC225 RC226 RC227 M2 3042 (HCA & SATA-Cache) RC228 RC229 WIGIG WIGIG GPU RC230 LOM WLAN WIGIG M2 3042 (HCA & SATA-Cache) H15D_En SD card NA LOM WLAN GPU WIGIG LOM WLAN WIGIG MCP_TESTLOW1 MCP_TESTLOW2 MCP_TESTLOW3 MCP_TESTLOW4 AN15 AP15 PCI_CLK_LPC_0 PCI_CLK_LPC_1 18P_0402_50V8J +PCH_VCCACLKPLL Express card CLK_BIASREF 3.01K_0402_1% 1 1 2 2 MCP_TESTLOW1 MCP_TESTLOW2 MCP_TESTLOW3 MCP_TESTLOW4 B35 A35 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% SPI_PCH_CS1# PCH_SPI_CS1# SPI_PCH_DO PCH_SPI_DO SPI_PCH_DIN PCH_SPI_DIN SPI_PCH_CLK PCH_SPI_CLK SPI_PCH_CS0# PCH_SPI_CS0# SPI_PCH_DO2 PCH_SPI_DO2 SPI_PCH_DO3 PCH_SPI_DO3 +3.3V_M 0_0402_5% WIGIG NA NA C35 C34 AK8 AL8 +3.3V_SPI NA H15 UMA SD card H15U_En SD card CLK_BIASREF RC231 A K21 M21 C26 CC11 2 XTAL24_OUT_R 0_0402_5% RC240 RC241 RC242 RC243 RC69 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% B support SPI TPM H14D_En SD card @ RC65 BDW-ULT-DDR3L_BGA1168 OF 19 PCI_CLK_LPC_0 EMC@ LOM XTAL24_IN XTAL24_OUT CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 PCIECLKRQ5/GPIO23 NA YC2 24MHZ_12PF_X3G024000DC1H M2 3042 (HCA & SATA-Cache) H12 Entry SD card H14 UMA SD card A25 B25 PCI_CLK_LPC_1 12P_0402_50V8J PCIECLK for DSC 1 @EMC@ CC12 PCI_CLK_LPC_0 12P_0402_50V8J CC8 18P_0402_50V8J RC63 1M_0402_5% 33_0804_8P4R_5% 10 11 12 13 14 15 16 17 18 19 20 21 22 JSPI1 LPC_0 LPC_1 SIO DOCK MEC DEBUG 10 11 12 13 14 15 16 17 18 19 20 A GND1 GND2 TYCO_2-2041070-0 CONN@ DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT Title SCHEMATICS,MB AA914 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RB Sheet of 55 UC1C DDR_A_D[0 63] DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 C B AH63 AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57 AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54 AL55 AK55 AR54 AN54 AY58 AW58 AY56 AW56 AV58 AU58 AV56 AU56 AY54 AW54 AY52 AW52 AV54 AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51 SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63 BDW-ULT-DDR3L_BGA1168 OF 19 BDW_ULT_DDR3L SA_CLK#0 SA_CLK0 SA_CLK#1 SA_CLK1 SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3 SA_CS#0 SA_CS#1 AU37 AV37 AW36 AY36 M_CLK_DDR#0 M_CLK_DDR0 M_CLK_DDR#1 M_CLK_DDR1 AU43 AW43 AY42 AY43 DDR_CKE0_DIMMA DDR_CKE1_DIMMA AP33 AR32 DDR_CS0_DIMMA# DDR_CS1_DIMMA# M_CLK_DDR#0 M_CLK_DDR0 M_CLK_DDR#1 M_CLK_DDR1 DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 AY31 AW31 AY29 AW29 AV31 AU31 AV29 AU29 AY27 AW27 AY25 AW25 AV27 AU27 AV25 AU25 AM29 AK29 AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26 AM26 AK25 AL25 AY23 AW23 AY21 AW21 AV23 AU23 AV21 AU21 AY19 AW19 AY17 AW17 AV19 AU19 AV17 AU17 AR21 AR22 AL21 AM22 AN22 AP21 AK21 AK22 AN20 AR20 AK18 AL18 AK20 AM20 AR18 AP18 SA_ODT0 SA_RAS SA_WE SA_CAS SA_BA0 SA_BA1 SA_BA2 SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15 DDR CHANNEL A SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7 SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7 SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1 AP32 AY34 AW34 AU34 DDR_A_RAS# DDR_A_WE# DDR_A_CAS# AU35 AV35 AY41 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 AP49 AR51 AP51 DDR_A_RAS# DDR_A_WE# DDR_A_CAS# DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 DDR_A_MA[0 15] DDR_A_DQS#[0 7] DDR_A_DQS[0 7] +SM_VREF_CA +SM_VREF_DQ0 +SM_VREF_DQ1 D BDW_ULT_DDR3L UC1D DDR_B_D[0 63] SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63 SB_CK#0 SB_CK0 SB_CK#1 SB_CK1 SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3 C yb er Fo ru m ru D SB_CS#0 SB_CS#1 SB_ODT0 SB_RAS SB_WE SB_CAS SB_BA0 SB_BA1 SB_BA2 DDR CHANNEL B SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15 SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7 SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7 AM38 AN38 AK38 AL38 M_CLK_DDR#2 M_CLK_DDR2 M_CLK_DDR#3 M_CLK_DDR3 AY49 AU50 AW49 AV50 DDR_CKE2_DIMMB DDR_CKE3_DIMMB AM32 AK32 DDR_CS2_DIMMB# DDR_CS3_DIMMB# M_CLK_DDR#2 M_CLK_DDR2 M_CLK_DDR#3 M_CLK_DDR3 DDR_CKE2_DIMMB DDR_CKE3_DIMMB DDR_CS2_DIMMB# DDR_CS3_DIMMB# AL32 AM35 AK35 AM33 DDR_B_RAS# DDR_B_WE# DDR_B_CAS# AL35 AM36 AU49 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_RAS# DDR_B_WE# DDR_B_CAS# DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 DDR_B_MA[0 15] C DDR_B_DQS#[0 7] DDR_B_DQS[0 7] B BDW-ULT-DDR3L_BGA1168 OF 19 A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT Title SCHEMATICS,MB AA914 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RB Sheet of 55 @ RC77 2 0_0402_5% +3.3V_RUN B A UC5 TC7SH08FU_SSOP5~D O 4PCH_PLTRST#_EC PCH_PLTRST#_EC PM_APWROK SIO_SLP_A# PM_APWROK B +RTC_CELL O A PM_APWROK_R 1 SYS_RESET# @ UC4 74AHC1G09GW_TSSOP5 P PCH_PLTRST# O A P B G UC6 TC7SH08FU_SSOP5~D 1 ME_RESET# 8.2K_0402_5% RC81 @ RC82 @ RC80 +PCH_VCCDSW3_3 D DSWODVREN RC78 330K_0402_5% ME_SUS_PWR_ACK 10K_0402_5% SUSACK# 10K_0402_5% SUS_STAT#/LPCPD# 10K_0402_5% G G XDP_DBRESET# RC79 P +3.3V_ALW_PCH +3.3V_ALW2 +3.3V_RUN D RPC1 AC_PRESENT PCH_PCIE_WAKE# PM_LANPHY_ENABLE PCH_BATLOW# 10K_8P4R_5% RC91 @ RC87 @ RC88 @ RC89 @ RC2201 PLTRST_USH# PLTRST_MMI# PLTRST_LAN# PLTRST_GPU# 2 2 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% DSWODVREN ON DIE DSW VR ENABLE PCH_PLTRST# HIGH = ENABLED (DEFAULT) LOW = DISABLED PCH_RSMRST#_Q 10K_0402_5% BDW_ULT_DDR3L UC1H SYSTEM POWER MANAGEMENT ME_RESET# 8.2K_0402_5% SYS_PWROK RESET_OUT# PCH_RSMRST#_Q ME_SUS_PWR_ACK SIO_PWRBTN# AC_PRESENT +3.3V_RUN UC7 XDP@ 14 TDO_XDP 0_0402_5% PCH_JTAG_TDI RC99 XDP@ TDI_XDP_R 0_0402_5% RUNPWROK PCH_JTAG_TMS PCH_JTAG_TMS 12 TRST#_XDP 13 RUNPWROK RUNPWROK 10 RUNPWROK DSWODVREN PCH_DPWROK PCH_PCIE_WAKE# SLP_S4 SLP_S3 SLP_A SLP_SUS SLP_LAN V5 AG4 AE6 AP5 CLKRUN# CLKRUN# SUS_STAT#/LPCPD# SUSCLK_R SUSCLK SIO_SLP_S5# @ @RC136 RC136 0_0402_5% SIO_SLP_S5# T8 PAD~D@ T9 PAD~D @ SIO_SLP_S4# SIO_SLP_S4# SIO_SLP_S3# SIO_SLP_S3# SIO_SLP_A# SIO_SLP_A# SIO_SLP_SUS# SIO_SLP_SUS# SIO_SLP_LAN# SIO_SLP_LAN# AJ6 AT4 AL5 AP4 AJ7 1A 1B CPU_XDP_TDO 1OE 2A 2B 2OE 3A 3B 3OE 4A CPU_XDP_PREQ# CPU_XDP_PRDY# CPU_XDP_TMS Place near JXDP1 11 4B 4OE CPU_XDP_TDI RC5 need to close to JCPU1 15 H_VCCST_PWRGD CFG0 CFG1 CFG2 CFG3 CFG0 CFG1 CFG2 CFG3 XDP_OBS0_R XDP_OBS1_R CPU_XDP_TRST# GND CFG4 CFG5 CFG4 CFG5 CFG6 CFG6 1K_0402_5% CFG7 RC102 CFG7 XDP@ 1K_0402_5% H_CPUPWRGD @ RC103 H_VCCST_PWRGD_XDP SIO_PWRBTN# PCH_JTAG_TRST# 0_0402_5% CPU_XDP_TRST# RC109 XDP@ PCH_JTAG_JTAGX 0_0402_5% CPU_XDP_TCLK RC112 XDP@ CPU_PWR_DEBUG# DDR_XDP_WAN_SMBDAT DDR_XDP_WAN_SMBCLK PCH_JTAG_TCK SYS_PWROK CPU_XDP_TCLK @EMC@ CC83 100P_0402_50V8J RC123 10K_0402_5% H_PROCHOT# H_CATERR# PECI_EC PECI_EC RC121 H_PROCHOT#_R 56_0402_5% K63 H_CPUPWRGD C61 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 CAD Note: Avoid stub in the PWRGD path while placing resistors RC123 DDR3_DRAMRST# DDR_PG_CTRL A D61 K61 N62 AU60 AV60 AU61 AV15 AV61 PROC_DETECT CATERR PECI PROCHOT PROCPWRGD SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST SM_PG_CNTL1 C CFG17 CFG16 CFG17 CFG16 CFG8 CFG9 CFG8 CFG9 CFG10 CFG11 CFG10 CFG11 CFG19 CFG18 CFG19 CFG18 CFG12 CFG13 CFG12 CFG13 CFG14 CFG15 CFG14 CFG15 XDP_RST#_R XDP_DBRESET# TDO_XDP TRST#_XDP PCH_JTAG_TDI PCH_JTAG_TMS CFG3_R RC113 XDP@ RC106 XDP@ PCH_PLTRST#_EC 1K_0402_5% CFG3 1K_0402_5% +1.05V_RUN TDO_XDP 51_0402_5% B @ RC117 Place near JXDP1.48 XDP_DBRESET# @ CC22 0.1U_0402_25V6 BDW_ULT_DDR3L UC1B EMI request add GND1 OBSFN_C0 OBSFN_C1 GND3 OBSDATA_C0 OBSDATA_C1 GND5 OBSDATA_C2 OBSDATA_C3 GND7 OBSFN_D0 OBSFN_D1 GND9 OBSDATA_D0 OBSDATA_D1 GND11 OBSDATA_D2 OBSDATA_D3 GND13 ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 GND15 TD0 TRST# TDI TMS GND17 SYS_PWROK CONN@ ACES_50506-01841-P01 CC21 XDP@ 0.1U_0402_25V6 H_PROCHOT# GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16 XDP@ RC120 1K_0402_5% CPU_XDP_TCLK RC119 @ @EMC@ CC20 22P_0402_50V8J H_CPUPWRGD SIO_SLP_S0# +3.3V_ALW_PCH TDI_XDP_R RC118 @ PCH_JTAG_TCK 0_0402_5% SYS_RESET# TDO_XDP RC115 @ PCH_JTAG_TDO 0_0402_5% PCH_RTCRST# PCH_RTCRST# POWER_SW#_MB +1.05V_RUN 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 SAMTE_BSH-030-01-L-D-A CONN@ 0_0402_5% B 10 11 12 13 14 15 16 17 18 GND GND JXDP1 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 74CBTLV3126BQ_DHVQFN14_2P5X3 H_CATERR# 49.9_0402_1% H_PROCHOT# 62_0402_5% SIO_SLP_S5# SIO_SLP_S4# SIO_SLP_A# +PCH_VCCDSW3_3 +1.05V_RUN VCC reference Shark Bay ULT Validation Customer Debug Port Implementation Requirement Rev 1.0 @ RC114 RC116 10 11 12 13 14 15 16 17 18 19 20 SIO_SLP_S3# +PCH_VCCDSW3_3 +1.05V_RUN GND PAD +1.05V_VCCST JAPS1 +3.3V_ALW_PCH PCH_DPWROK PCH_PCIE_WAKE# PCH_JTAG_TDI RSMRST SUSWARN/SUSPWRDNACK/GPIO30 PWRBTN ACPRESENT/GPIO31 BATLOW/GPIO72 SLP_S0 SLP_WLAN/GPIO29 RUNPWROK CLKRUN/GPIO32 SUS_STAT/GPIO61 SUSCLK/GPIO62 SLP_S5/GPIO63 @ CC19 0.1U_0402_25V6 RC98 XDP@ AW6 AV4 AL7 AJ8 AN4 AF3 AM5 @ CC18 0.1U_0402_25V6 PCH_JTAG_TDO AW7 AV5 AJ5 BDW-ULT-DDR3L_BGA1168 OF 19 CC17 XDP@ 0.1U_0402_25V6 PCH_RSMRST#_Q ME_SUS_PWR_ACK SIO_PWRBTN# AC_PRESENT PCH_BATLOW# SIO_SLP_S0# SIO_SLP_WLAN# DSWVRMEN DPWROK WAKE SIO_SLP_WLAN# PM_APWROK_R PCH_PLTRST# SUSACK SYS_RESET SYS_PWROK PCH_PWROK APWROK PLTRST C AK2 AC3 AG2 AY7 AB5 AG7 SUSACK# @ RC95 SUSACK# SYS_RESET# SYS_PWROK C yb er Fo ru m ru +3.3V_RUN MISC PRDY PREQ PROC_TCK PROC_TMS PROC_TRST PROC_TDI PROC_TDO JTAG THERMAL J62 K62 E60 E61 E59 F63 F62 CPU_XDP_PRDY# CPU_XDP_PREQ# CPU_XDP_TCLK CPU_XDP_TMS CPU_XDP_TRST# CPU_XDP_TDI CPU_XDP_TDO J60 H60 H61 H62 K59 H63 K60 J61 XDP_OBS0_R XDP_OBS1_R XDP_OBS2_R XDP_OBS3_R XDP_OBS4_R XDP_OBS5_R XDP_OBS6_R XDP_OBS7_R Place near JXDP1.47 +3.3V_RUN XDP_DBRESET# 1K_0402_5% +1.05V_RUN DDR3L PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D T10 T11 T12 T13 T14 T15 @ RC124 @ RC125 @ RC126 CPU_XDP_TCLK 51_0402_5% CPU_XDP_TRST# 51_0402_5% CPU_XDP_TMS 51_0402_5% CPU_XDP_TDI 51_0402_5% CPU_XDP_PREQ# 51_0402_5% CPU_XDP_TDO 51_0402_5% PWR BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7 RC122 @ @ @ @ @ @ BDW-ULT-DDR3L_BGA1168 OF 19 RC127 RC128 @ RC129 A DDR3 COMPENSATION SIGNALS 200_0402_1% 121_0402_1% 100_0402_1% RC130 SM_RCOMP0 RC131 SM_RCOMP1 RC132 SM_RCOMP2 DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc CAD Note: Trace width=12~15 mil, Spcing=20 mils Max trace length= 500 mil PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT Title SCHEMATICS,MB AA914 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RB Sheet of 55 D D BDW_ULT_DDR3L UC1A DDI1_LANE_N0 DDI1_LANE_P0 DDI1_LANE_N1 DDI1_LANE_P1 DDI1_LANE_N2 DDI1_LANE_P2 DDI1_LANE_N3 DDI1_LANE_P3 DDI2_LANE_N0 DDI2_LANE_P0 DDI2_LANE_N1 DDI2_LANE_P1 DDI2_LANE_N2 DDI2_LANE_P2 DDI2_LANE_N3 DDI2_LANE_P3 C C54 C55 B58 C58 B55 A55 A57 B57 C45 B46 A47 B47 EDP_CPU_LANE_N0 EDP_CPU_LANE_P0 EDP_CPU_LANE_N1 EDP_CPU_LANE_P1 C yb er Fo ru m ru C51 C50 C53 B54 C49 B50 A53 B53 DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3 EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1 DDI EDP DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3 EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3 EDP_AUXN EDP_AUXP EDP_RCOMP EDP_DISP_UTIL EDP_CPU_LANE_N0 EDP_CPU_LANE_P0 EDP_CPU_LANE_N1 EDP_CPU_LANE_P1 COMPENSATION PU FOR eDP +VCCIOA_OUT C47 C46 A49 B49 A45 B45 EDP_CPU_AUX# EDP_CPU_AUX D20 A43 EDP_COMP EDP_CPU_AUX# EDP_CPU_AUX EDP_COMP 24.9_0402_1% RC133 CAD Note:Trace width=20 mils ,Spacing=25mil, Max length=100 mils C BDW-ULT-DDR3L_BGA1168 OF 19 +3.3V_RUN RPC15 TOUCHPAD_INTR# 10K_8P4R_5% RC134 DGPU_PWR_EN 10K_0402_5% 2 @ RC139 @ RC140 ENVDD_PCH 100K_0402_5% PCH_GPIO53 1K_0402_5% PCH_GPIO16 SIO_RCIN# SATA2_PCIE6_L1 EDP_BIA_PWM PANEL_BKLEN ENVDD_PCH CONTACTLESS_DET# DGPU_PWROK HDD_FALL_INT PCH_GPIO80 @ T16 PAD~D EDP_BIA_PWM PANEL_BKLEN ENVDD_PCH B8 A9 C6 HDD_FALL_INT U6 P4 N4 N2 AD4 TOUCHPAD_INTR# PCH_GPIO52 DGPU_PWR_EN DGPU_PWR_EN PCH_GPIO53 B U7 L1 L3 R5 L4 EDP_BKLCTL EDP_BKLEN EDP_VDDEN +3.3V_RUN BDW_ULT_DDR3L UC1I DDPB_CTRLCLK DDPB_CTRLDATA DDPC_CTRLCLK DDPC_CTRLDATA eDP SIDEBAND PIRQA/GPIO77 PIRQB/GPIO78 PIRQC/GPIO79 PIRQD/GPIO80 PME DISPLAY PCIE GPIO55 GPIO52 GPIO54 GPIO51 GPIO53 DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP DDPB_HPD DDPC_HPD EDP_HPD RPC2 CPU_DPB_CTRLCLK CPU_DPB_CTRLDAT CPU_DPC_CTRLCLK CPU_DPC_CTRLDAT B9 C9 D9 D11 CPU_DPB_CTRLCLK CPU_DPB_CTRLDAT CPU_DPC_CTRLCLK CPU_DPC_CTRLDAT CPU_DPB_CTRLCLK CPU_DPB_CTRLDAT C5 B6 B5 A6 CPU_DPB_AUX# CPU_DPC_AUX# CPU_DPB_AUX CPU_DPC_AUX CPU_DPC_AUX# C8 A8 D6 DPB_HPD DPC_HPD EDP_CPU_HPD CPU_DPC_AUX 2.2K_0804_8P4R_5% DPB_HPD DPC_HPD EDP_CPU_HPD BDW-ULT-DDR3L_BGA1168 OF 19 RPC20 CPU_DPB_AUX# CPU_DPB_AUX CPU_DPC_AUX CPU_DPC_AUX# 100K_0804_8P4R_5% B EDP_CPU_HPD 100K_0402_5% DPC_HPD 100K_0402_5% RC141 RC142 A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT Title SCHEMATICS,MB AA914 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RB Sheet 10 of 55 ... 18 P _04 02_50V8J RC63 1M _04 02_5% 33 _08 0 4_8P4R_5% 10 11 12 13 14 15 16 17 18 19 20 21 22 JSPI1 LPC _0 LPC _1 SIO DOCK MEC DEBUG 10 11 12 13 14 15 16 17 18 19 20 A GND1 GND2 TYCO_2 - 204 10 7 0 -0 CONN@ DELL CONFIDENTIAL/PROPRIETARY... +1 .05 V_RUN 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 SAMTE_BSH -03 0 - 01 -L-D-A CONN@ 0_ 0 402 _5% B 10 11 12 13 14 15 16 17 18 GND GND JXDP1 11 13 15 17 19 21. .. > Pin2 & Pin3 short CC1 1 2 CC2 18 P _04 02_50V8J 1M _04 02_5% RC 10 RC8 2 20K _04 02_5% 20K _04 02_5% YC1 32.768KHZ _12 .5PF_Q13FC13 500 004 0 1U _04 02_6.3V6K 1 2 @ CMOS1 SHORT PADS~D 1U _04 02_6.3V6K CC4 CMOS place near DIMM