COMPAL LA a821p (ZEMAA) 2013 05 22 rev 0 1 schematic

A B C D E Intel BayTrail-M Platform 1 C yb er Fo ru m ru Date : 2013/05/22 Version 0.1 3 4 2014/01/03 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/01/03 Deciphered Date Title Cover Page THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 0.1 Bay Trail M LA-A821P Date: A B C D Monday, July 01, 2013 Sheet E of 40 A B C D E 204pin DDR3L-SO-DIMM X1 P.14 Memory BUS LVDS Conn Colay eDP P.17 XDP-SFF-26Pin Debug P.13 Conn LVDS Translator RTD2132R-CG P.16 Dual Channel 1.35V DDR3L 1066/1333 204pin DDR3L-SO-DIMM X1 C yb er Fo ru m ru P.15 DDI Port1 DDI Port0 HDMI Conn USB2.0 x3 P.18 RTL8106E-CG 10/100M RTL8111G-CG 1G P.21 P.21 PCIE x4 port SATA SSD NGFF B P.22 TYPE USB 3.0 Conn P.23 USB 2.0 Conn P.23 USB HUB FE1.1s(STT) P.23 port PCIE x4 port3 PCIeMini Card page 05~12 LPC BUS SPI ROM 1.8V (8MB) P.17 P.20 P.17 HD Audio NGFF E TYPE WLAN PCIe port HDA Codec KB9012QF A4 Int Camera Touch Screen WLAN PCIe port SATA HDD Conn P.19 port port FCBGA 1170 Pin port SPI port SOC SATA II x2 port port USB3.0 x1 VALLEYVIEW-M RJ45 port ALC259 P.24 P.22 P.08 P.25 Sub Boards CardReader GL834L(HUB Port0) +USB(Port 2)+ Audio Combo jack P.22 RTC CKT P.8 Int.KBD DC/DC Interface CKT SPK Conn P.22 P.26 P.26 Power Circuit DC/DC Touch pad/LED B P.28~P.36 P.22 LED/Power On/Off P.24 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/01/03 Deciphered Date 2014/01/03 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Block Diagrams Document Number Rev 0.1 Bay Trail M LA-A821P Monday, July 01, 2013 Sheet E of 40 A B C Voltage Rails E Board ID / SKU ID Table for AD channel Power Plane Description S0 S3 S4/S5 VIN 19V Adapter power supply ON ON ON BATT+ 12V Battery power supply ON ON ON B+ AC or battery power rail for power circuit (19V/12V) ON ON ON +RTCVCC RTC Battery Power +1.0VALW +1.0v Always power rail Vcc 3.3V +/- 5% Ra/Rc/Re 100K +/- 5% Board ID Rb / Rd / Rf 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V C yb er Fo ru m ru D ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON +1.8VALW +1.8v Always power rail +3VALW +3.3v Always power rail +5VALW +5.0v Always power rail +1.35V +1.35V power rail for DDR3L ON ON OFF +SOC_VCC Core voltage for SOC ON OFF OFF +SOC_VNN GFX voltage for SOC ON OFF OFF +0.675VS +0.675V power rail for DDR3L Terminator ON OFF OFF +1.0VS +1.0v system power rail ON OFF OFF +1.05VS +1.05v system power rail ON OFF OFF +1.35VS +1.35v system power rail ON OFF OFF +1.5VS +1.5v system power rail ON OFF OFF +1.8VS +1.8v system power rail ON OFF OFF +3VS +3.3v system power rail ON OFF OFF +5VS +5.0v system power rail ON OFF OFF V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V BOARD ID Table Board ID BOM Option Table PCB Revision Item BOM Structure Unpop @ Connector CONN@ XDP (Debug Port) XDP@ EMC requirement EMC@ EMC requirement unpop @EMC@ TPM TPM@ Touch Screen TS@ R short RS@ Test Point TEST@ Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF BOM config EC SM Bus1 address Device Address Smart Battery 0001 011X b SOC SM Bus address Device Address SO-DIMM A (JDIMM1) SO-DIMM B (JDIMM2) A0h A2h EC SM Bus2 address Device PCB P/N EVT BOM config Address 43 level BOM table 43 Level BOM Structure Compal Electronics, Inc Compal Secret Data Security Classification Issued Date Description 2014/01/03 Deciphered Date 2014/01/03 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Notes List Document Number Rev 0.1 Bay Trail M LA-A821P Monday, July 01, 2013 Sheet E of 40 Power ON +RTCVCC T0 RTCRST# D EC_ON D +3VALW/+5VALW +1.0VALW +1.2VALW ON/OFFBTN# 100 ms EC_RSMRST# 100 ms 20 ms PBTN_OUT# PMC_SLP_S4# SUSPWRDNACK 100 ms C yb er Fo ru m ru +1.8VALW 120 ms SYSON +1.35V DDR_PWROK C PMC_SLP_S3# C 20ms VR_ON +CORE_VNN +CORE_VCC VGET 20ms SUSP# +1.0VS 0.446 ms +1.05VS 0.606 ms +1.35VS 0.878 ms +1.5VS 0.973 ms +1.8VS 1.171 ms +3VS 1.757 ms B +5VS B 2.343 ms +0.675VS 6.774 ms 50 ms KBRST# 100 ms PMC_CORE_PWROK DDR_CORE_PWROK PMC_PLTRST# T0: +RTCVCC stable to RTCRST# high > 9ms T1: VR ramp up time from 10% to 90% voltage level < 2ms T2 :Rail to subsequent rail turn on delay < 2ms T3 :+VALWAS stable to EC_RSMRST# high > 10ms T4 :+VS rails stable to PMC_CORE_PWROK > TBD NOTE: T1 and T2 are recommended time for all the VR rails unless specified otherwise The VR ramp up time T2 and subsequent rail delay T3 are put in place to avoid inrush current which may be caused by multiple loads turning on simultaneously or fast charging of VR output decoupling A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Platform devices other than SOC sequencing are not explicitly shown as they are not limited by the SOC sequencing requirement 2014/01/03 Deciphered Date 2014/01/03 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Power Sequence Document Number Rev 0.1 Bay Trail M LA-A821P Monday, July 01, 2013 Sheet of 40 D D UC1A DDR_A_DM[0 7] DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 K45 H47 L41 H44 H50 G53 H49 D50 G52 E52 K48 E51 F47 J51 B49 B50 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 G36 B36 F38 B42 P51 V42 Y50 Y52 M45 M44 H51 DDR_A_RAS# DDR_A_CAS# DDR_A_WE# C K47 K44 D52 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 P44 DDR_A_CS0# P45 DDR_A_CS2# C47 D48 F44 E46 DDR_A_CKE0 DDR_A_CKE2 T41 DDR_A_ODT0 P42 DDR_A_ODT2 M50 M48 DDR_A_CLK0 DDR_A_CLK0# P50 P48 DDR_A_CLK2 DDR_A_CLK2# P41 DDR_A_RST# AF44 +DDR_SOC_VREF 100K_0402_5% 100K_0402_5% B RC1 RC2 DDR_TERMN0 DDR_TERMN1 AD42 AB42 DDR_PWROK DDR_CORE_PWROK 23.2_0402_1% 29.4_0402_1% 162_0402_1% RC3 RC4 RC5 AF42 AH42 DDR_RCOMP0 DDR_RCOMP1 DDR_RCOMP2 AD44 AF45 AD45 DRAM0_MA_0 DRAM0_MA_1 DRAM0_MA_2 DRAM0_MA_3 DRAM0_MA_4 DRAM0_MA_5 DRAM0_MA_6 DRAM0_MA_7 DRAM0_MA_8 DRAM0_MA_9 DRAM0_MA_10 DRAM0_MA_11 DRAM0_MA_12 DRAM0_MA_13 DRAM0_MA_14 DRAM0_MA_15 DRAM0_DM_0 DRAM0_DM_1 DRAM0_DM_2 DRAM0_DM_3 DRAM0_DM_4 DRAM0_DM_5 DRAM0_DM_6 DRAM0_DM_7 DRAM0_RAS# DRAM0_CAS# DRAM0_WE# DRAM0_BS_0 DRAM0_BS_1 DRAM0_BS_2 DRAM0_CS_0# DRAM0_CS_2# DRAM0_CKE_0 RESERVED_D48 DRAM0_CKE_2 RESERVED_E46 DRAM0_ODT_0 DRAM0_ODT_2 DRAM0_CKP_0 DRAM0_CKN_0 DRAM0_CKP_2 DRAM0_CKN_2 DRAM0_DRAMRST# DRAM_VREF 0.675V ICLK_DRAM_TERMN_AF42 ICLK_DRAM_TERMN_AH42 DRAM0_DQSP_0 DRAM0_DQSN_0 DRAM0_DQSP_1 DRAM0_DQSN_1 DRAM0_DQSP_2 DRAM0_DQSN_2 DRAM0_DQSP_3 DRAM0_DQSN_3 DRAM0_DQSP_4 DRAM0_DQSN_4 DRAM0_DQSP_5 DRAM0_DQSN_5 DRAM0_DQSP_6 DRAM0_DQSN_6 DRAM0_DQSP_7 DRAM0_DQSN_7 DRAM_VDD_S4_PWROK DRAM_CORE_PWROK DRAM_RCOMP_0 DRAM_RCOMP_1 DRAM_RCOMP_2 Follow CRB v1.15 AF40 AF41 AD40 AD41 DRAM0_DQ_0 DRAM0_DQ_1 DRAM0_DQ_2 DRAM0_DQ_3 DRAM0_DQ_4 DRAM0_DQ_5 DRAM0_DQ_6 DRAM0_DQ_7 DRAM0_DQ_8 DRAM0_DQ_9 DRAM0_DQ_10 DRAM0_DQ_11 DRAM0_DQ_12 DRAM0_DQ_13 DRAM0_DQ_14 DRAM0_DQ_15 DRAM0_DQ_16 DRAM0_DQ_17 DRAM0_DQ_18 DRAM0_DQ_19 DRAM0_DQ_20 DRAM0_DQ_21 DRAM0_DQ_22 DRAM0_DQ_23 DRAM0_DQ_24 DRAM0_DQ_25 DRAM0_DQ_26 DRAM0_DQ_27 DRAM0_DQ_28 DRAM0_DQ_29 DRAM0_DQ_30 DRAM0_DQ_31 DRAM0_DQ_32 DRAM0_DQ_33 DRAM0_DQ_34 DRAM0_DQ_35 DRAM0_DQ_36 DRAM0_DQ_37 DRAM0_DQ_38 DRAM0_DQ_39 DRAM0_DQ_40 DRAM0_DQ_41 DRAM0_DQ_42 DRAM0_DQ_43 DRAM0_DQ_44 DRAM0_DQ_45 DRAM0_DQ_46 DRAM0_DQ_47 DRAM0_DQ_48 DRAM0_DQ_49 DRAM0_DQ_50 DRAM0_DQ_51 DRAM0_DQ_52 DRAM0_DQ_53 DRAM0_DQ_54 DRAM0_DQ_55 DRAM0_DQ_56 DRAM0_DQ_57 DRAM0_DQ_58 DRAM0_DQ_59 DRAM0_DQ_60 DRAM0_DQ_61 DRAM0_DQ_62 DRAM0_DQ_63 M36 J36 P40 M40 P36 N36 K40 K42 B32 C32 C36 A37 C33 A33 C37 B38 F36 G38 F42 J42 G40 C38 G44 D42 A41 C41 A45 B46 C40 B40 B48 B47 K52 K51 T52 T51 L51 L53 R51 R53 T47 T45 Y40 V41 T48 T50 Y42 AB40 V45 V47 AD48 AD50 V48 V50 AB44 Y45 V52 W51 AC53 AC51 W53 Y51 AD52 AD51 DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 J38 K38 C35 B34 D40 F40 B44 C43 N53 M52 T42 T44 Y47 Y48 AB52 AA51 DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7 DDR_A_D[0 63] DDR_B_MA[0 15] AY45 DDR_B_MA0 BB47 DDR_B_MA1 DDR_B_MA2 AW41 BB44 DDR_B_MA3 BB50 DDR_B_MA4 BC53 DDR_B_MA5 BB49 DDR_B_MA6 BF50 DDR_B_MA7 BC52 DDR_B_MA8 BE52 DDR_B_MA9 DDR_B_MA10 AY48 DDR_B_MA11 BE51 DDR_B_MA12 BD47 DDR_B_MA13 BA51 DDR_B_MA14 BH49 DDR_B_MA15 BH50 RESERVED_AF40 RESERVED_AF41 RESERVED_AD40 RESERVED_AD41 DDR_B_DM[0 7] DDR_B_RAS# DDR_B_CAS# DDR_B_WE# DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 DDR_B_CS0# DDR_B_CS2# DDR_B_CKE0 DDR_B_CKE2 DDR_B_ODT0 DDR_B_ODT2 DDR_B_CLK0 DDR_B_CLK0# DDR_B_CLK2 DDR_B_CLK2# DDR_B_RST# DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 BD38 BH36 BC36 BH42 AT51 AM42 AK50 AK52 AV45 AV44 BB51 AY47 AY44 BF52 AT44 AT45 BG47 BE46 BD44 BF48 AP41 AT42 AV50 AV48 AT50 AT48 AT41 +1.35V DRAM1_DM_0 DRAM1_DM_1 DRAM1_DM_2 DRAM1_DM_3 DRAM1_DM_4 DRAM1_DM_5 DRAM1_DM_6 DRAM1_DM_7 DRAM1_RAS# DRAM1_CAS# DRAM1_WE# DRAM1_BS_0 DRAM1_BS_1 DRAM1_BS_2 DRAM1_CS_0# DRAM1_CS_2# DRAM1_CKE_0 RESERVED_BE46 DRAM1_CKE_2 RESERVED_BF48 DRAM1_ODT_0 DRAM1_ODT_2 DRAM1_CKP_0 DRAM1_CKN_0 DRAM1_CKP_2 DRAM1_CKN_2 DRAM1_DRAMRST# DDR_A_DQS[0 7] DDR_A_DQS#[0 7] OF 13 DRAM1_DQ_0 DRAM1_DQ_1 DRAM1_DQ_2 DRAM1_DQ_3 DRAM1_DQ_4 DRAM1_DQ_5 DRAM1_DQ_6 DRAM1_DQ_7 DRAM1_DQ_8 DRAM1_DQ_9 DRAM1_DQ_10 DRAM1_DQ_11 DRAM1_DQ_12 DRAM1_DQ_13 DRAM1_DQ_14 DRAM1_DQ_15 DRAM1_DQ_16 DRAM1_DQ_17 DRAM1_DQ_18 DRAM1_DQ_19 DRAM1_DQ_20 DRAM1_DQ_21 DRAM1_DQ_22 DRAM1_DQ_23 DRAM1_DQ_24 DRAM1_DQ_25 DRAM1_DQ_26 DRAM1_DQ_27 DRAM1_DQ_28 DRAM1_DQ_29 DRAM1_DQ_30 DRAM1_DQ_31 DRAM1_DQ_32 DRAM1_DQ_33 DRAM1_DQ_34 DRAM1_DQ_35 DRAM1_DQ_36 DRAM1_DQ_37 DRAM1_DQ_38 DRAM1_DQ_39 DRAM1_DQ_40 DRAM1_DQ_41 DRAM1_DQ_42 DRAM1_DQ_43 DRAM1_DQ_44 DRAM1_DQ_45 DRAM1_DQ_46 DRAM1_DQ_47 DRAM1_DQ_48 DRAM1_DQ_49 DRAM1_DQ_50 DRAM1_DQ_51 DRAM1_DQ_52 DRAM1_DQ_53 DRAM1_DQ_54 DRAM1_DQ_55 DRAM1_DQ_56 DRAM1_DQ_57 DRAM1_DQ_58 DRAM1_DQ_59 DRAM1_DQ_60 DRAM1_DQ_61 DRAM1_DQ_62 DRAM1_DQ_63 DRAM1_DQSP_0 DRAM1_DQSN_0 DRAM1_DQSP_1 DRAM1_DQSN_1 DRAM1_DQSP_2 DRAM1_DQSN_2 DRAM1_DQSP_3 DRAM1_DQSN_3 DRAM1_DQSP_4 DRAM1_DQSN_4 DRAM1_DQSP_5 DRAM1_DQSN_5 DRAM1_DQSP_6 DRAM1_DQSN_6 DRAM1_DQSP_7 DRAM1_DQSN_7 BG38 BC40 BA42 BD42 BC38 BD36 BF42 BC44 BH32 BG32 BG36 BJ37 BG33 BJ33 BG37 BH38 AU36 AT36 AV40 AT40 BA36 AV36 AY42 AY40 BJ41 BG41 BJ45 BH46 BG40 BH40 BH48 BH47 AY52 AY51 AP52 AP51 AW51 AW53 AR51 AR53 AP47 AP45 AK40 AM41 AP48 AP50 AK42 AH40 AM45 AM47 AF48 AF50 AM48 AM50 AH44 AK45 AM52 AL51 AG53 AG51 AL53 AK51 AF52 AF51 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 BF40 BD40 BG35 BH34 BA38 AY38 BH44 BG43 AU53 AV52 AP42 AP44 AK47 AK48 AH52 AJ51 DDR_B_DQS0 DDR_B_DQS#0 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS7 DDR_B_DQS#7 DDR_B_D[0 63] C B DDR_B_DQS[0 7] DDR_B_DQS#[0 7] OF 13 VALLEYVIEW-M_FCBGA1170 Close To SOC Pin DRAM1_MA_0 DRAM1_MA_1 DRAM1_MA_2 DRAM1_MA_3 DRAM1_MA_4 DRAM1_MA_5 DRAM1_MA_6 DRAM1_MA_7 DRAM1_MA_8 DRAM1_MA_9 DRAM1_MA_10 DRAM1_MA_11 DRAM1_MA_12 DRAM1_MA_13 DRAM1_MA_14 DRAM1_MA_15 C yb er Fo ru m ru DDR_A_MA[0 15] UC1B VALLEYVIEW-M_FCBGA1170 +DDR_SOC_VREF 1 RC6 4.7K_0402_1% RC7 4.7K_0402_1% CC1 1U_0402_16V7K A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/01/03 Deciphered Date 2014/01/03 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: VLV-M SOC Memory DDR3L Document Number Rev 0.1 Bay Trail M LA-A821P Monday, July 01, 2013 Sheet of 40 UC1C Follow CRB v1.15 0ohm till to GND AK12 AK13 AM14 AM13 AM3 AM2 C 1.8V 1.8V 1.8V 1.8V DDI1_DDCDATA DDI1_DDCCLK 1.8V 1.8V 1.8V DDI1_VDDEN DDI1_BKLTEN DDI1_BKLTCTL DDI0_VDDEN DDI0_BKLTEN DDI0_BKLTCTL VSS_AH3 VSS_AH2 DDI0_RCOMP_P DDI0_RCOMP_N RESERVED_AM14 RESERVED_AM13 VSS_AM3 VSS_AM2 RESERVED_AH14 RESERVED_AH13 RESERVED_AF14 RESERVED_AF13 +1.8VS @ RC10 10K_0402_5% T1 GPIO_NC12 RC11 10K_0402_5% T2 GPIO_NC13 GPIO_NC14 Follow CRB v1.15 T2 T3 AB3 AB2 Y3 Y2 W3 W1 V2 V3 R3 R1 AD6 AD4 AB9 AB7 Y4 Y6 V4 V6 A29 C29 AB14 B30 C30 RESERVED_T2 RESERVED_T3 RESERVED_AB3 RESERVED_AB2 RESERVED_Y3 RESERVED_Y2 RESERVED_W3 RESERVED_W1 RESERVED_V2 RESERVED_V3 RESERVED_R3 RESERVED_R1 RESERVED_AD6 RESERVED_AD4 RESERVED_AB9 RESERVED_AB7 RESERVED_Y4 RESERVED_Y6 RESERVED_V4 RESERVED_V6 GPIO_S0_NC_13 GPIO_S0_NC14 RESERVED_AB14 GPIO_S0_NC_12 RESERVED_C30 3.3V 3.3V VGA_HSYNC VGA_VSYNC 3.3V 3.3V VGA_DDCCLK VGA_DDCDATA RESERVED_T7 RESERVED_T9 RESERVED_AB13 RESERVED_AB12 RESERVED_Y12 RESERVED_Y13 RESERVED_V10 RESERVED_V9 RESERVED_T12 RESERVED_T10 RESERVED_V14 RESERVED_V13 RESERVED_T14 RESERVED_T13 RESERVED_T6 RESERVED_T4 RESERVED_P14 OF 10 GPIO_S0_NC_15 GPIO_S0_NC_16 GPIO_S0_NC_17 GPIO_S0_NC_18 GPIO_S0_NC_19 GPIO_S0_NC_20 GPIO_S0_NC_21 GPIO_S0_NC_22 GPIO_S0_NC_23 GPIO_S0_NC_24 GPIO_S0_NC_25 GPIO_S0_NC_26 H_EDP_HPD# P30 DDI1_ENABLE RC8 G30 2.2K_0402_5% +1.8VS +1.8VS DDI0_DDCDATA DDI0_DDCCLK H_EDP_AUXP H_EDP_AUXN K30 N30 DDI1_ENVDD J30 DDI1_ENBKL M30 DDI1_PWM AH3 AH2 DDI1_ENBKL UC6 NC Y A A EC_ENBKL_R Follow CRB v1.15 0ohm till to GND AH14 AH13 AF14 AF13 +1.8VS BA3 AY2 BA1 AW1 AY3 DDI1_ENVDD UC7 NC Y A C LCD_ENVDD NL17SZ07DFT2G_SC70-5 SA00004BV00 BD2 BF2 +1.8VS BC1 BC2 T7 T9 AB13 AB12 Y12 Y13 V10 V9 T12 T10 V14 V13 T14 T13 T6 T4 P14 DDI1_PWM UC8 NC LVDS@ RC64 0_0402_5% Y A SOC_PWM_TL IEDP@ RC65 0_0402_5% SOC_PWM_EDP NL17SZ07DFT2G_SC70-5 SA00004BV00 +3VS RPC1 SOC_PWM_TL LCD_ENVDD SOC_PWM_EDP B 4.7K_0804_8P4R_5% F34 M32 D28 J28 K34 D34 F32 F28 K28 J34 N32 D32 RPC2 DDI1_ENBKL DDI1_ENVDD DDI1_PWM 0504 100K_0804_8P4R_5% +3VS EC_ENBKL_R 4.7K_0402_5% RB24 Straps Pin:MDSI_DDCDATA A Compal Electronics, Inc Compal Secret Data Security Classification 2014/01/03 Issued Date Deciphered Date 2014/01/03 Title VLV-M SOC Display THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 0.1 Bay Trail M LA-A821P Date: NL17SZ07DFT2G_SC70-5 SA00004BV00 VALLEYVIEW-M_FCBGA1170 GPIO_S0_NC[13]: Multiplexed with Hardware EC_ENBKL P DDI1_HPD IEDP@ 0_0402_5% G 1.8V EC_ENBKL_R1 RC87 DDI1_AUXP DDI1_AUXN 1.8V VGA_RED VGA_BLUE VGA_GREEN VGA_IREF VGA_IRTN B 1.0V 1.0V DDI0_HPD DDI0_AUXP DDI0_AUXN D eDP Panel AK3 AK2 RC9 DDI0_RCOMPP 402_0402_1% DDI0_RCOMPN P B28 C27 B26 H_EDP_TXP0 H_EDP_TXN0 H_EDP_TXP1 H_EDP_TXN1 G C26 C28 AG3 AG1 AF3 AF2 AD3 AD2 AC3 AC1 UMA_HDMI_DATA UMA_HDMI_CLK DDI1_TXP_0 DDI1_TXN_0 DDI1_TXP_1 DDI1_TXN_1 DDI1_TXP_2 DDI1_TXN_2 DDI1_TXP_3 DDI1_TXN_3 D27 HDMI_HPD# 1.0V P AL3 AL1 1.0V G HDMI DDI0_TXP_0 DDI0_TXN_0 DDI0_TXP_1 DDI0_TXN_1 DDI0_TXP_2 DDI0_TXN_2 DDI0_TXP_3 DDI0_TXN_3 D AV3 AV2 AT2 AT3 AR3 AR1 AP3 AP2 H_HDMI_TX2+ H_HDMI_TX2H_HDMI_TX1+ H_HDMI_TX1H_HDMI_TX0+ H_HDMI_TX0H_HDMI_TXC+ H_HDMI_TXC- C yb er Fo ru m ru Monday, July 01, 2013 Sheet of 40 PCIE_PTX_WLANRX_P4 PCIE_PTX_WLANRX_N4 NonUltra@ CC83 1U_0402_16V7K CC82 1U_0402_16V7K PCIE_PTX_C_WLANRX_P4_M PCIE_PTX_C_WLANRX_N4_M UC1D NonUltra@ +1.8VS RC18 AY16 BA16 BB10 BC10 BA12 SOC_SCI# AY14 DEVSLP_SOC SATA_LED#_SOC AY12 T3 10K_0402_5% RC12 SATA_RCOMPP 402_0402_1% SATA_RCOMPN AU18 AT18 AT22 AV20 AU22 AV22 AT20 AY24 AU26 AT26 AU20 C AV26 BA24 AY18 BA18 AY20 BD20 BA20 BD18 BC18 AY26 AT28 BD26 AU28 BA26 BC24 AV28 BF22 BD22 B BF26 SATA_TXP_1 SATA_TXN_1 PCIE_TXP_1 PCIE_TXN_1 SATA_RXP_1 SATA_RXN_1 PCIE_RXP_1 PCIE_RXN_1 VSS_BB10 VSS_BC10 PCIE_TXP_2 PCIE_TXN_2 SATA_GP0 / GPIO_S0_SC_0 SATA_GP1 / SATA_DEVSLP_0 / GPIO_S0_SC_1 SATA_LED# / GPIO_S0_SC_2 AT10 AT9 AT7 PCIE_PTX_LANRX_P3 AT6 PCIE_PTX_LANRX_N3 PCIE_RXP_2 PCIE_RXN_2 AP6 PCIE_PTX_WLANRX_P4 AP4 PCIE_PTX_WLANRX_N4 PCIE_TXP_3 PCIE_TXN_3 SATA_RCOMP_P SATA_RCOMP_N MMC1_CLK / GPIO_S0_SC_16 BB7 BB5 VSS_BB7 VSS_BB5 PCIE_CLKREQ_0# / GPIO_S0_SC_3 PCIE_CLKREQ_1# / GPIO_S0_SC_4 PCIE_CLKREQ_2# / GPIO_S0_SC_5 PCIE_CLKREQ_3# / GPIO_S0_SC_6 SD3_WP / GPIO_S0_SC_7 MMC1_CMD / GPIO_S0_SC_25 MMC1_RST# / SATA_DEVSLP_0 / GPIO_S0_SC_26 PCIE_RCOMP_P PCIE_RCOMP_N AP14 AP13 PCIE_RCOMPP PCIE_RCOMPN BF20 BG22 BH20 BJ21 BG20 BG19 BG21 BH18 BG18 HDA_LPE_RCOMP HDA_RST# / LPE_I2S0_CLK / GPIO_S0_SC_8 HDA_SYNC / LPE_I2S0_FRM / GPIO_S0_SC_9 HDA_CLK / LPE_I2S0_DATAOUT / GPIO_S0_SC_10 HDA_SDO / LPE_I2S0_DATAIN / GPIO_S0_SC_11 HDA_SDI0 / LPE_I2S1_CLK / GPIO_S0_SC_12 HDA_SDI1 / LPE_I2S1_FRM / GPIO_S0_SC_13 SD3_CLK / GPIO_S0_SC_33 HDA_DOCKRST# / LPE_I2S1_DATAOUT / GPIO_S0_SC_14 SD3_D0 / GPIO_S0_SC_34 HDA_DOCKEN# / LPE_I2S1_DATAIN / GPIO_S0_SC_15 SD3_D1 / GPIO_S0_SC_35 SD3_D2 / GPIO_S0_SC_36 LPE_I2S2_CLK / SATA_DEVSLP_1 / GPIO_S0_SC_62 SD3_D3 / GPIO_S0_SC_37 LPE_I2S2_FRM / GPIO_S0_SC_63 SD3_CD# / GPIO_S0_SC_38 LPE_I2S2_DATAIN / GPIO_S0_SC_64 SD3_CMD / GPIO_S0_SC_39 LPE_I2S2_DATAOUT / GPIO_S0_SC_65 SD3_1P8EN / GPIO_S0_SC_40 SD3_PWREN# / GPIO_S0_SC_41 RESERVED_P34 RESERVED_N34 SD3_RCOMP RESERVED_AK9 RESERVED_AK7 BF28 BA30 BD28 BC30 49.9_0402_1% GPIO_S0_SC_65 RC17 33.2_0402_1% RPC3 +1.8VS RC15 10K_0402_5% GPIO_S0_SC_63 AZ_SDOUT_HD AZ_SYNC_HD AZ_BITCLK_HD AZ_RST_HD# Deciphered Date GPIO_S0_SC_65: Security Flash Descriptors = Override = Normal Operation (Internal PU) B +1.8VS RC16 10K_0402_5% GPIO_S0_SC_65 ESD@ CC7 10P_0402_50V8J 2014/01/03 S TXE_DBG G QC1 BSS138W-7-F_SOT323-3 A Compal Electronics, Inc Title Date: EC programing : "High"for Flash BIOS D Compal Secret Data 3 33_0804_8P4R_5% EMC@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC +1.0VS H_PROCHOT# C CC6 @EMC@ 22P_0402_50V8J AZ_BITCLK_HD GPIO_S0_SC_63: BIOS/EFI Boot Strap (BBS) BIOS Boot Selection = LPC = SPI DEVSLP1 GPIO_S0_SC_63 Internal PD 2K 2014/01/03 For EMI AZ_SDIN0_HD Issued Date 10K_0804_8P4R_5% RC14 T4 T5 T6 C24 Security Classification 8411 Pin 36 O/D HDA_SDOUT HDA_SYNC HDA_BIT_CLK HDA_RST# HDA_RCOMP HDA_RST# HDA_SYNC HDA_BIT_CLK HDA_SDOUT WLAN PCIE_PRX_WLANTX_P4 PCIE_PRX_WLANTX_N4 RC13 402_0402_1% AK9 AK7 VALLEYVIEW-M_FCBGA1170 A Ultra@ PCIE_CLKREQ_0# LAN_CLKREQ# WLAN_CLKREQ# PCIE_CLKREQ_1# LAN_CLKREQ# WLAN_CLKREQ# HDMI_HPD# P34 N34 PROCHOT# OF 10 PCIE_CLKREQ_0# PCIE_CLKREQ_1# LAN_CLKREQ# WLAN_CLKREQ# +1.8VS RPC7 PCIE_PTX_C_WLANRX_P4 PCIE_PTX_C_WLANRX_N4 Follow CRB V1.15 0ohm till to GND BG3 BD7 BG5 BE3 BD5 LAN PCIE_PRX_C_LANTX_P3 PCIE_PRX_C_LANTX_N3 AV10 AV9 RESERVED_AV10 RESERVED_AV9 SD2_CLK / GPIO_S0_SC_27 SD2_D0 / GPIO_S0_SC_28 SD2_D1 / GPIO_S0_SC_29 SD2_D2 / GPIO_S0_SC_30 SD2_D3_CD# / GPIO_S0_SC_31 SD2_CMD / GPIO_S0_SC_32 PCIE_PTX_C_LANRX_P3 PCIE_PTX_C_LANRX_N3 BB4 BB3 RESERVED_BB4 RESERVED_BB3 MMC1_RCOMP CC2 CC3 Ultra@ CC4 1U_0402_16V7K CC5 1U_0402_16V7K AP9 PCIE_PRX_WLANTX_P4 AP7 PCIE_PRX_WLANTX_N4 PCIE_RXP_3 PCIE_RXN_3 MMC1_D0 / GPIO_S0_SC_17 MMC1_D1 / GPIO_S0_SC_18 MMC1_D2 / GPIO_S0_SC_19 MMC1_D3 / GPIO_S0_SC_20 MMC1_D4 / GPIO_S0_SC_21 MMC1_D5 / GPIO_S0_SC_22 MMC1_D6 / GPIO_S0_SC_23 MMC1_D7 / GPIO_S0_SC_24 1U_0402_16V7K 1U_0402_16V7K AP12 PCIE_PRX_C_LANTX_P3 AP10 PCIE_PRX_C_LANTX_N3 SOC_SCI# D AV6 AV4 Follow CRB V1.15 0ohm till to GND Follow CRB v1.15 AT14 AT13 SATA_PRX_C_DTX_P1 SATA_PRX_C_DTX_N1 PCIE_RXP_0 PCIE_RXN_0 SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 SSD SATA_RXP_0 SATA_RXN_0 AY7 AY6 C yb er Fo ru m ru BD10 BF10 PCIE_TXP_0 PCIE_TXN_0 AU16 AV16 SATA_PRX_C_DTX_P0 SATA_PRX_C_DTX_N0 D SATA_TXP_0 SATA_TXN_0 BF6 BG7 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 HDD VLV-M SOC SATA/PCI-E/HDA Document Number Rev 0.1 Bay Trail M LA-A821P Monday, July 01, 2013 Sheet of 40 GCLK@ 0_0402_5% XTAL_25M_IN_R RCL6 Place near to YC1 +1.8VS XTAL_25M_IN D GND GND 2 1 XTAL_25M_OUT 1.8V CC10 18P_0402_50V8J NOGCLK@ PMC_PLTRST# Y A RC21 4.7K_0402_5% UC2 NC RC22 2.2K_0402_5% 3.3V PLT_RST_BUF# 1 CC9 18P_0402_50V8J NOGCLK@ XDP_H_TDI XDP_H_TMS XDP_H_TCK XDP_H_TRST# P XDP_H_PRDY# RP52 G 51_0402_5% YC1 NOGCLK@ 25MHZ_10PF_7V25000014 RC25 XDP@ +1.8VALW RC20 1M_0402_5% NOGCLK@ +1.8VALW +3VS Close To SOC