A B C D E 1 C yb er Fo ru m ru Compal Confidential ZRMAA/ZEMAA Schematics Document 2 Haswell ULT with DDR3L nVIDIA N14P-GV2 (Dual Rank) nVIDIA N14M-GL LA-A481P REV 0.1 Schematic 3 Intel Processor (Haswell) 2013-02-22 Rev 0.1 4 2012/04/19 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2015/04/19 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Cover Page Rev 0.1 ZRMAA/ZEMAA Date: A B C D Sunday, April 07, 2013 Sheet E of 49 A B C D E VGA (DDR3) Intel Haswell ULT PCI-Express 4X Gen3 8GT/s nVIDIA N14P-GV2 & N14M-GL Memory BUS(DDR3L) 204pin DDR3-SO-DIMM X2 Dual Channel page 18~26 LVDS Conn Colay eDP page 16,17 BANK 0, 1, eDP 1X 5.4GT/s 1 1.35V DDR3L 1333/1600 MT/s Haswell ULT LVDS Translator RTD2132S (Single) page 28 GCLK Processor SLG3NB282VTR page 27 C yb er Fo ru m ru USB30 2x 5V 5GT/s OPI USB20 2x USB3.0 x2 Right USB20 port 0,1 USB30 port 1,2 5V 480MHz HDMI Conn USB20 1x page 34 page 37 CardReader Connector 5V 480MHz USB20 port page 36 page 30 Lynx Point - LP PCIe Gen1 1x PCIeMini Card WLAN PCIe port page 34 1.5V 5GT/s PCIeMini Card WIMAX USB20 port page 34 SATA HDD CardReader RTS5176(Port 3) +USB (Port 2)+Audio Combo jack page 35 Touch pad/LED B page 41 SATA SSD page Touch Screen USB20 port page 28 USB20 1x 5V 480MHz SATA Gen3 port USB20 1x 5V 480MHz SATA Gen3 port Int Camera USB20 port page 28 1168pin BGA SATA port 5V 6GHz(600MB/s) page 33 page 05~15 SPI ROM (8MB) RTC CKT 5V 480MHz PCH SATA port 5V 6GHz(600MB/s) page 33 Sub Boards USB20 1x LPC BUS HD Audio 3.3V 33 MHz 3.3V 24MHz HDA Codec KB9012 ALC282 (w/ S&M) page 40 page page 38 DC/DC Interface CKT page 42 Touch Pad page 41 Power Circuit DC/DC Int.KBD page 41 G-Sensor page 33 SPK Conn JHP page 39 page 39 page 43~51 4 Power On/Off CKT page 41 2012/04/19 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2015/04/19 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Block Diagram Document Number Rev 0.1 ZRMAA/ZEMAA Sunday, April 07, 2013 Sheet E of 49 A B C B+ D DESIGN CURRENT 26mA +3VL DESIGN CURRENT 12.47A +5VALW E USB_EN#0 DESIGN CURRENT 2A +USB_VCCB DESIGN CURRENT 2A +USB_VCCA SY6288DCAC USB_CHG_EN# G547N2P81U 1 USB_EN#2 DESIGN CURRENT 2A +USB_VCCC SUSP# SY6288DCAC DESIGN CURRENT 5.61A TPS22966DPUR +5VS +5VS RT8243AZQW DESIGN CURRENT 2A +HDMI_5V_OUT AP2151DWG-7 C yb er Fo ru m ru KB_LED DESIGN CURRENT 50mA SUSP# +5VS_LED A03413-SOT23 DESIGN CURRENT 10.5A SY8208DQNC +1.05VS_VTT VGA_PWROK DESIGN CURRENT 5.13A +1.05VS_DGPU 2N7002 SUSP# TPS22966DPUR DESIGN CURRENT 5.824A +3VALW DESIGN CURRENT 4.873A +3VS DESIGN CURRENT 2.0A +LCD_VDD LCD_ENVDD APL3512ABI-TRG DGPU_PWR_EN DESIGN CURRENT 1.02A +3VS_DGPU P-CHANNEL AO-3413 PCH_PWR_EN# +3VS_RT DESIGN CURRENT 451mA P-CHANNEL AO-3413 +3V_LAN WOWL_EN# SUSP# +3VALW_PCH DESIGN CURRENT 500mA P-CHANNEL AO-3413 +3V_WLAN DESIGN CURRENT 27.821A TPS51362RVER PCH_PWR_EN TPS51212DSCR +1.5VS DESIGN CURRENT 11A +1.5VSDGPU DESIGN CURRENT 15.9A +VRAM_1.5VS DESIGN CURRENT A +1.5VS 1.5V_PWR_EN FDS6676AS SUSP P-CHANNEL AO-3413 VR_ON DESIGN CURRENT 32A TPS51622RSM SYSON +CPU_CORE DESIGN CURRENT 6A +1.35V RT8207MZQW DESIGN CURRENT 1.5A +0.675VS +3VS_DGPU 4 DESIGN CURRENT 55.2A +VGA_CORE NCP81172MNTWG +LCD_INV Compal Secret Data Security Classification 2012/10/25 Issued Date 2013/10/05 Deciphered Date Title Compal Electronics, Inc Power Map THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev 0.1 ZRMAA/ZEMAA Sheet Sunday, April 07, 2013 E of 49 A B ( O MEANS ON Voltage Rails C D X MEANS OFF ) SKU Platform +RTCVCC E B+ +5VL +5VALW +3VL +3VALW +1.35V PCH VGA +5VS +3VS nVIDIA N13P-GL (N13PGL@) +1.8VS_CRT +1.5VALW power plane CPU +1.5VS +VSB +CPU_CORE +VGA_CORE +VRAM_1.5VS +3VS_DGPU Function +1.05VS_DGPU +1.05VS_VTT State BTO Option Table SKU MIC LAN description explain S0 O O O S1 O O O S3 O O O S5 S4/AC O O O O O O O X X S5 S4/ Battery only S5 S4/AC & Battery don't exist C yb er Fo ru m ru BTO O O O O O O O O X O X X X X X explain X X X BTO Function description Function PCH SM Bus Address HEX description explain Power Device Address +3VS DDR SO-DIMM A0 H 1010 0000 b +3VS DDR SO-DIMM A4 H 1010 0100 b BTO Function description 3 explain BTO EC SM Bus1 Address EC SM Bus2 Address SIGNAL STATE Full ON Power HEX Device Address Power +3VL Smart Battery 16 H 0001 0110 b +3VS +3VL Smart Charger 12 H 0001 0010 b +3VS Power Device HEX Address Device HEX PCH 96 H 1001 0110 b NVIDIA GPU 9E H 1001 1010 b SLP_S3# SLP_S4# SLP_S5# HIGH HIGH HIGH S1(Power On Suspend) HIGH HIGH HIGH S3 (Suspend to RAM) LOW HIGH HIGH S4 (Suspend to Disk) LOW LOW HIGH S5 (Soft OFF) LOW LOW LOW G3 LOW LOW LOW Address 4 2012/07/10 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/07/10 Deciphered Date Title Notes List THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 0.1 ZRMAA/ZEMAA Date: A B C D Sunday, April 07, 2013 Sheet E of 49 C54 C55 B58 C58 B55 A55 A57 B57 D HDMI C51 C50 C53 B54 C49 B50 A53 B53 H_HDMI_TX2H_HDMI_TX2+ H_HDMI_TX1H_HDMI_TX1+ H_HDMI_TX0H_HDMI_TX0+ H_HDMI_TXCH_HDMI_TXC+ DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3 EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1 DDI EDP DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3 EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3 EDP_AUXN EDP_AUXP EDP_RCOMP EDP_DISP_UTIL C yb er Fo ru m ru OF 19 T20 T97 D61 K61 N62 @ @ H_PECI +1.05VS_VTT ESD@ C H_CPUPW RGD CH11 R68 62_0402_5% H_PROCHOT# R6 +1.35V 1 1 C61 PROCHOT PROCPWRGD SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST SM_PG_CNTL1 H_EDP_TXN0 H_EDP_TXP0 H_EDP_TXN1 H_EDP_TXP1 C47 C46 A49 B49 D A45 B45 D20 A43 H_EDP_AUXN H_EDP_AUXP EDP_COMP R1 24.9_0402_1% +VCCIOA_OUT Trace width=20 mils,Spacing=25mil,Max length=100mils Rev1p2 MISC PRDY PREQ PROC_TCK PROC_TMS PROC_TRST PROC_TDI PROC_TDO JTAG DDR3 Compensation Signals DIMM_DRAMRST# B 10K_0402_5% H_CPUPW RGD 200_0402_1% SM_RCOMP0 AU60 120_0402_1% SM_RCOMP1 AV60 100_0402_1% SM_RCOMP2 AU61 DIMM_DRAMRST# AV15 DIMM_DRAMRST# AV61 DDR_PG_CTRL R11 R13 R41 R184 470_0603_5% R8 56_0402_5% H_PROCHOT#_R K63 PROC_DETECT CATERR PECI C45 B46 A47 B47 HASWELL_MCP_E U1B 100P_0402_50V8J HASWELL_MCP_E U1A THERMAL J62 K62 E60 E61 E59 F63 F62 XDP_PRDY# XDP_PREQ# XDP_TCK XDP_TMS XDP_TRST# XDP_TDI XDP_TDO J60 H60 H61 H62 K59 H63 K60 J61 BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7 @ T154 C PWR DDR3 OF 19 BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7 @ @ @ @ @ @ @ @ T155 T156 T148 T149 T150 T151 T152 T153 Rev1p2 ESD@ DIMM_DRAMRST# 0.1U_0402_10V7K CH7 PU/PD for JTAG signals +1.05VS_VTT B XDP_TMS R86 XDP_TDI R87 XDP@ 51_0402_5% XDP_PREQ# R88 51_0402_5% XDP_TDO R89 XDP@ 51_0402_5% XDP_TCK R90 XDP@ 51_0402_5% XDP_TRST# R91 51_0402_5% @ @ @ 51_0402_5% A A Compal Electronics, Inc Compal Secret Data Security Classification 2012/07/10 Issued Date Deciphered Date 2013/07/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom Rev 0.1 ZRMAA/ZEMAA Date: HSW MCP(1/11) DDI,MSIC,XDP Sheet Sunday, April 07, 2013 of 49 U1C HASWELL_MCP_E HASWELL_MCP_E U1D C AH63 AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57 AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54 AL55 AK55 AR54 AN54 AY58 AW58 AY56 AW56 AV58 AU58 AV56 AU56 AY54 AW54 AY52 AW52 AV54 AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51 SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63 SA_CLK#0 SA_CLK0 SA_CLK#1 SA_CLK1 SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3 SA_CS#0 SA_CS#1 SA_ODT0 SA_RAS SA_WE SA_CAS SA_BA0 SA_BA1 SA_BA2 DDR CHANNEL A SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15 SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7 SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7 SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1 B OF 19 AU37 AV37 AW36 AY36 SA_CLK_DDR#0 SA_CLK_DDR0 SA_CLK_DDR#1 SA_CLK_DDR1 AU43 AW43 AY42 AY43 DDRA_CKE0_DIMMA DDRA_CKE1_DIMMA AP33 AR32 AP32 DDRA_ODT0 AY34 AW34 AU34 AU35 AV35 AY41 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 DDRA_CS0_DIMMA# DDRA_CS1_DIMMA# @ T4 DDR_A_RAS# DDR_A_WE# DDR_A_CAS# DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 AY31 AW31 AY29 AW29 AV31 AU31 AV29 AU29 AY27 AW27 AY25 AW25 AV27 AU27 AV25 AU25 AM29 AK29 AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26 AM26 AK25 AL25 AY23 AW23 AY21 AW21 AV23 AU23 AV21 AU21 AY19 AW19 AY17 AW17 AV19 AU19 AV17 AU17 AR21 AR22 AL21 AM22 AN22 AP21 AK21 AK22 AN20 AR20 AK18 AL18 AK20 AM20 AR18 AP18 SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63 SB_CK#0 SB_CK0 SB_CK#1 SB_CK1 SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3 SB_CS#0 SB_CS#1 SB_ODT0 SB_RAS SB_WE SB_CAS C yb er Fo ru m ru D DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 AU36 DDR_A_MA0 AY37 DDR_A_MA1 AR38 DDR_A_MA2 AP36 DDR_A_MA3 AU39 DDR_A_MA4 AR36 DDR_A_MA5 AV40 DDR_A_MA6 AW39DDR_A_MA7 AY39 DDR_A_MA8 AU40 DDR_A_MA9 AP35 DDR_A_MA10 AW41DDR_A_MA11 AU41 DDR_A_MA12 AR35 DDR_A_MA13 AV42 DDR_A_MA14 AU42 DDR_A_MA15 AJ61 DDR_A_DQS#0 AN62 DDR_A_DQS#1 AM58 DDR_A_DQS#2 AM55 DDR_A_DQS#3 AV57 DDR_A_DQS#4 AV53 DDR_A_DQS#5 AL43 DDR_A_DQS#6 AL48 DDR_A_DQS#7 AJ62 DDR_A_DQS0 AN61 DDR_A_DQS1 AN58 DDR_A_DQS2 AN55 DDR_A_DQS3 AW57DDR_A_DQS4 AW53DDR_A_DQS5 AL42 DDR_A_DQS6 AL49 DDR_A_DQS7 AP49 AR51 AP51 DDR_A_D[0 63] DDR_A_MA[0 15] DDR_A_DQS#[0 7] DDR_A_DQS[0 7] SM_DIMM_VREFCA SA_DIMM_VREFDQ SB_DIMM_VREFDQ DDR CHANNEL B SB_BA0 SB_BA1 SB_BA2 SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15 SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7 SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7 AM38 AN38 AK38 AL38 SB_CLK_DDR#0 SB_CLK_DDR0 SB_CLK_DDR#1 SB_CLK_DDR1 AY49 AU50 AW49 AV50 D DDRB_CKE0_DIMMB DDRB_CKE1_DIMMB AM32 AK32 DDRB_CS0_DIMMB# DDRB_CS1_DIMMB# AL32 DDRB_ODT0 AM35 AK35 AM33 @ T5 DDR_B_RAS# DDR_B_WE# DDR_B_CAS# AL35 AM36 AU49 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 AP40 DDR_B_MA0 AR40 DDR_B_MA1 AP42 DDR_B_MA2 AR42 DDR_B_MA3 AR45 DDR_B_MA4 AP45 DDR_B_MA5 AW46 DDR_B_MA6 AY46 DDR_B_MA7 AY47 DDR_B_MA8 AU46 DDR_B_MA9 AK36 DDR_B_MA10 AV47 DDR_B_MA11 AU47 DDR_B_MA12 AK33 DDR_B_MA13 AR46 DDR_B_MA14 AP46 DDR_B_MA15 C AW30 DDR_B_DQS#0 AV26 DDR_B_DQS#1 AN28 DDR_B_DQS#2 AN25 DDR_B_DQS#3 AW22DDR_B_DQS#4 AV18 DDR_B_DQS#5 AN21 DDR_B_DQS#6 AN18 DDR_B_DQS#7 AV30 DDR_B_DQS0 AW26 DDR_B_DQS1 AM28 DDR_B_DQS2 AM25 DDR_B_DQS3 AV22 DDR_B_DQS4 AW18 DDR_B_DQS5 AM21 DDR_B_DQS6 AM18 DDR_B_DQS7 DDR_B_D[0 63] DDR_B_MA[0 15] DDR_B_DQS#[0 7] DDR_B_DQS[0 7] B Rev1p2 OF 19 Rev1p2 A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/07/10 2013/07/10 Deciphered Date Title HSW MCP(2/11) DDRIII THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 0.1 ZRMAA/ZEMAA Date: Sheet Sunday, April 07, 2013 of 49 PCH_RTCX1 T138 @ PCH_RTCX2 1M_0402_5% SM_INTRUDER# PCH_INTVRMEN PCH_SRTCRST# PCH_RTCRST# R72 AW5 AY5 AU6 AV7 AV6 AU7 RTCX1 RTCX2 INTRUDER INTVRMEN SRTCRST RTCRST HDA_BIT_CLK HDA_SYNC HDA_RST# AZ_SDIN0_HD iME Setting JME 2PCH_SRTCRST# CH5 1U_0402_6.3V6K @ C R73 @ HDA_SDOUT @ @ @ T7 T8 T9 T95 +RTCVCC PCH_INTVRMEN T6 51_0402_5% R98 @ T21 T19 T15 T10 T11 T22 T12 330K_0402_5% INTVRMEN Integrated VRM enable Integrated VRM disable * HL AW8 AV11 AU8 AY10 AU12 AU11 AW10 AV10 AY8 HDA_BCLK/I2S0_SCLK HDA_SYNC/I2S0_SFRM HDA_RST/I2S_MCLK HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_SDO/I2S0_TXD HDA_DOCK_EN/I2S1_TXD HDA_DOCK_RST/I2S1_SFRM I2S1_SCLK AUDIO @ PCH_JTAG_RST# PCH_JTAG_TCK @ PCH_JTAG_TDI @ PCH_JTAG_TDO @ PCH_JTAG_TMS @ @ @ PCH_TCK_JTAGX @ AU62 AE62 AD61 AE61 AD62 AL11 AC4 AE63 AV2 OF 19 HDA for AUDIO RP14 AZ_RST_HD# AZ_BITCLK_HD AZ_SDOUT_HD AZ_SYNC_HD 33_0804_8P4R_5% R163 PWRME_CTRL ME Debug B 0_0402_5% HDA_RST# HDA_BIT_CLK HDA_SDOUT HDA_SYNC PU at Page09 V1 U1 V6 AC1 EC_SMI# ODD_DETECT# @ T159 @ T165 EC_SMI# ODD_DETECT# +1.05VS_ASATA3PLL @ A12 L11 @ K10 @ C12 U3 SATA_IREF RSVD RSVD SATA_RCOMP SATALED JTAG D F5 E5 C17 D17 SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0 SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0 SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37 PCH_TRST PCH_TCK PCH_TDI PCH_TDO PCH_TMS RSVD RSVD JTAGX RSVD SSD J6 H6 B14 C15 SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1 SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1 SATA SATA_PRX_C_DTX_N1 SATA_PRX_C_DTX_P1 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 SATA_IREF T13 T14 SATA_RCOMP R75 0_0603_5% within 500 mils R2 3.01K_0402_1% C Rev1p2 FAN Control Circuit +3VS B R33 10K_0402_5% +FAN1 C4 0.01U_0402_25V7K @ 1 +FAN1 D1 BAS16_SOT23-3 C5 0_0603_5% 10U_0603_6.3V6M +3VL R32 1A G2 G1 E&T_3802-F04N-01R @ +5VS DH1 BAS40-04_SOT23-3 +RTCVCC FANPW M FAN_SPEED1 +RTCBATT JFAN CH4 1U_0402_6.3V6K RH24 20K_0402_5% SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2 SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2 JCMOS @ HDD PCH_RTCRST# J8 H8 A17 B17 SATA_PRX_C_DTX_N0 SATA_PRX_C_DTX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 +RTCVCC C yb er Fo ru m ru RH23 20K_0402_5% J5 H5 B15 A15 SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3 SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3 RTC D CMOS Setting, near DDR Door HASWELL_MCP_E U1E +RTCVCC GCLK@ PCH_RTCX1 RH26 0_0402_5% PCH_RTCX1_R CH8 0.1U_0402_10V7K A A Compal Electronics, Inc Compal Secret Data Security Classification 2012/07/10 Issued Date Deciphered Date 2013/07/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom Rev 0.1 ZRMAA/ZEMAA Date: HSW MCP(3/11) RTC,SATA,XDP Sheet Sunday, April 07, 2013 of 49 RH42 0_0402_5% GCLK@ PCH_X1_R T158 @ WLAN R52 +3VS CLKREQ_LAN# CLK_WLAN# CLK_WLAN CLKREQ_WLAN# CLK_REQ_VGA# RH89 T160 B37 A37 T2 CLKOUT_LPC_0 CLKOUT_LPC_1 CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 PCIECLKRQ4/GPIO22 @ AU14 LPC_AD0 AW12 LPC_AD1 AY12 LPC_AD2 AW11 LPC_AD3 LPC_FRAME# AV12 PCH_SPICLK PCH_SPICS0# PCH_SPIDI PCH_SPIDO1 PCH_SPIDO2 PCH_SPIDO3 1K_0402_5% PCH_SPIDO2 RH16 1K_0402_5% PCH_SPIDO3 RH5 B AA3 Y7 Y4 AC2 AA2 AA4 Y6 AF1 LAD0 LAD1 LAD2 LAD3 LFRAME SPI_CLK SPI_CS0 SPI_CS1 SPI_CS2 SPI_MOSI SPI_MISO SPI_IO2 SPI_IO3 SMBALERT/GPIO11 SMBCLK SMBDATA SML0ALERT/GPIO60 SMBUS SML0CLK SML0DATA SML1ALERT/PCHHOT/GPIO73 SML1CLK/GPIO75 SML1DATA/GPIO74 LPC SPI C-LINK SPI ROM for BIOS & ME & Win8 (8MByte ) CH9 EC_SDIO AN15 AP15 1 1 2 2 CLKOUT_LPC0 R78 3.01K_0402_1% +1.05VS_AXCK_LCPLL D 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% R390 22_0402_5% CLK_PCI_EC EMI@ B35 CLK_BCLK_ITP# A35 CLK_BCLK_ITP @ @ CL_CLK CL_DATA CL_RST AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3 T18 T130 SMB_ALERT# PCH_SMBCLK PCH_SMBDATA PCH_SMBDATA LAN_EN SML0CLK SML0DATA @ T170 PCH_SMLCLK1 PCH_SMLDATA1 AF2 AD2 AF4 @ @ @ C PU 2.2K at EC side (+3VS) T23 T24 T25 +3VALW _PCH RP8 SUSW ARN# SLP_CHG_CB0 USB_CHG_OC# PCH_SMBCLK 2.2K_0804_8P4R_5% Rev1p2 RH73 2.2K_0402_5% PCH_SMLDATA1 RH77 2.2K_0402_5% PCH_SMLCLK1 +3VS RH61 885@ RH68 RH69 15_0402_5% 15_0402_5% 15_0402_5% RH72 885@ 15_0402_5% PCH_SPICS0# PCH_SPI0_DO1 PCH_SPI0_DO2 CS# SO WP# GND VCC HOLD# SCLK SI +3VS 0.1U_0402_10V7K UH3 PCH_SPIDO1 PCH_SPIDO2 R140 R141 R142 R148 +3VALW _PCH EC_CS0# C35 C34 AK8 AL8 T16 T17 XCLK_BIASREF Rev1p2 OF 19 +3VALW _PCH K21 @ M21 @ C26 HASWELL_MCP_E U1G C PCH_X1 PCH_X2 CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 PCIECLKRQ5/GPIO23 OF 19 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# A25 B25 Q7A DMN66D0LDW -7_SOT363-6 PCH_SPI0_DO3 PCH_SPI0_CLK PCH_SPI0_DI RH65 RH66 RH67 @ 15_0402_5% 0_0402_5% 15_0402_5% PCH_SPIDO3 PCH_SPICLK PCH_SPIDI PCH_SMBDATA 10K_0402_5% A39 B39 U5 SIGNALS CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 PCIECLKRQ3/GPIO21 C yb er Fo ru m ru +3VS CLK_REQ_VGA# TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8 CLOCK CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 PCIECLKRQ2/GPIO20 B38 C37 N1 CLK_PCIE_VGA# CLK_PCIE_VGA CLK_REQ_VGA# RSVD RSVD DIFFCLK_BIASREF CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 PCIECLKRQ1/GPIO19 C41 B42 AD1 10K_0402_5% XTAL24_IN XTAL24_OUT 2 CLK_LAN# CLK_LAN PCIE LAN CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 PCIECLKRQ0/GPIO18 B41 A41 Y5 PCH_GPIO19 C3 12P_0402_50V8J NOGCLK@ C43 C42 U2 R116 4.7K_0402_5% B R119 4.7K_0402_5% Placement near to YH2 PCH_X2 C2 12P_0402_50V8J NOGCLK@ HASWELL_MCP_E U1F PCH_X1 NOGCLK@ 1 PM_SMBDATA D 2 PCH_X1 1M_0402_5% R48 NOGCLK@ Y2 24MHZ_12PF_7A24000134 64M EN25QH64-104HIP SOP 8P RH74 885@ 15_0402_5% RH78 885@ 15_0402_5% PCH_SMBCLK EC_SCK PM_SMBCLK Q7B DMN66D0LDW -7_SOT363-6 EC_SDI Socket: SP07000F500/SP07000H900 Please place UH3 close to U1 CPU, Please place RH66, RH67, RH68 near UH3 +3VS PCH_SMLDATA1 PCH_SMLCLK1 EC_SMB_DA2 QH4B 2N7002DW -T/R7_SOT363-6 EC_SMB_CK2 QH4A A A 2N7002DW -T/R7_SOT363-6 Compal Electronics, Inc Compal Secret Data Security Classification 2012/07/10 Issued Date Deciphered Date 2013/07/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom Rev 0.1 ZRMAA/ZEMAA Date: HSW MCP(4/11) CLK,SPI,SMBUS Sheet Sunday, April 07, 2013 of 49 DH2 +3VALW _PCH PCH_PW ROK +3VS 1 EC_SW I# RH171 POK R227 10K_0402_5% PCH_RSMRST# 1K_0402_5% DSWODVREN - On Die DSW VR Enable Enable(DEFAULT) Disable * LH BAS40-04_SOT23-3 SYS_RESET# +RTCVCC HASWELL_MCP_E U1H R124 D SUSW ARN# PCH_PW ROK VCCST_PG_EC R63 @ R206 0_0402_5% @ 0_0402_5% PCH_RSMRST# +3VALW _PCH +3VALW_PCH R245 100K_0402_5% ACIN R79 @ 0_0402_5% PCH_RSMRST#_R SUSW ARN# AW6 AV4 AL7 AJ8 AN4 AF3 AM5 DSWVRMEN DPWROK WAKE PCH_ACIN RB751V40_SC76-2 V5 AG4 AE6 AP5 CLKRUN/GPIO32 SUS_STAT/GPIO61 SUSCLK/GPIO62 SLP_S5/GPIO63 SUSW ARN# PBTN_OUT# RSMRST SUSWARN/SUSPWRDNACK/GPIO30 PWRBTN ACPRESENT/GPIO31 BATLOW/GPIO72 SLP_S0 SLP_WLAN/GPIO29 R156 PCH_ACIN 8.2K_0402_5% PCH_BATLOW # T31 @ Note for PCH_ACIN: Deep Sx need use EC GPIO for ACPRESENT function D21 PCH_RSMRST# PCH_RSMRST# SUSACK SYS_RESET SYS_PWROK PCH_PWROK APWROK PLTRST AW7 AV5 AJ5 C yb er Fo ru m ru R117 AK2 AC3 AG2 AY7 AB5 AG7 SUSACK# SYS_RESET# SYS_PW ROK PCH_PW ROK PM_APW ROK PLT_RST# PLT_RST# 10K_0402_5% SLP_S4 SLP_S3 SLP_A SLP_SUS SLP_LAN DSW ODVREN PCH_RSMRST#_R EC_SW I# PCH_PW M_EDP EC_ENBKL RH17 LVDS@ 0_0402_5% PCH_PW M RH18 IEDP@ 0_0402_5% EC_ENBKL_R RH19 IEDP@ 0_0402_5% B8 A9 C6 8.2K_0402_5% T104 CLK_EC PM_SLP_S5# PM_SLP_S5# @ @ AJ6 AT4 AL5 AP4 AJ7 +3VS PM_SLP_S4# PM_SLP_S3# @ @ PM_SLP_LAN# T27 T28 @ T29 PM_SLP_S4# PM_SLP_S3# T30 T96 R118 @ 10K_0402_5% +3VALW _PCH not support Deep S4,S5 can NC Rev1p2 OF 19 DDPB_CTRLDATA: Port B Detected DDPC_CTRLDATA: Port C Detected C * 1: Port B or C is detected 0: Port B or C is not detected (Have internal PD) HASWELL_MCP_E U1I PCH_PW M_TL D EC_SW I# R157 @ CLKRUN# Need to Check C 330K_0402_5% SYSTEM POWER MANAGEMENT EDP_BKLCTL EDP_BKLEN EDP_VDDEN DDPB_CTRLCLK DDPB_CTRLDATA DDPC_CTRLCLK DDPC_CTRLDATA eDP SIDEBAND +3VS B9 C9 D9 D11 R271 2.2K_0402_5% UMA_HDMI_CLK UMA_HDMI_DATA LCD_ENVDD @ U7 L1 L3 R5 L4 PCH_GPIO55 @ PCH_GPIO54 PCH_GPIO51 PCH_GPIO53 PIRQA/GPIO77 PIRQB/GPIO78 PIRQC/GPIO79 PIRQD/GPIO80 PME DISPLAY GPIO GPIO55 GPIO52 GPIO54 GPIO51 GPIO53 DDPB_HPD DDPC_HPD EDP_HPD OF 19 PCH_PW ROK R65 0_0402_5% DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP C5 B6 B5 A6 C8 A8 D6 B H_EDP_HPD Rev1p2 R417 100K_0402_5% R403 0_0402_5% @ SYS_PW ROK +3VS +3VS R391 100K_0402_5% OPT@ IN1 IN2 OUT PLT_RST_BUF# 1 R416 100K_0402_5% U30 MC74VHC1G08DFT2G_SC70-5 U37 MC74VHC1G08DFT2G_SC70-5 OPT@ PLT_RST# PLTRST_VGA# VCC OUT GND IN2 IN1 VCC DGPU_HOLD_RST# GND PLT_RST# R208 10K_0402_5% HDMI_HPD H_EDP_HPD H_EDP_HPD T26 T157 B U6 P4 N4 N2 AD4 DGPU_HOLD_RST# VGA_PW ROK DGPU_PW R_EN DGPU_HOLD_RST# TP_INTR# A A Compal Electronics, Inc Compal Secret Data Security Classification 2012/07/10 Issued Date Deciphered Date 2013/07/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom Rev 0.1 ZRMAA/ZEMAA Date: HSW MCP(5/11) PM,GPIO,DDI Sheet Sunday, April 07, 2013 of 49 Note: need check all GPIO PU need or not after BIOS post +3VS RP23 SERIRQ ODD_EN# 10K_0804_8P4R_5% TP_INTR# HASWELL_MCP_E U1J D D PASSW ORD_CLEAR# AG6 AP1 T166 @ PCH_GPIO58 AL4 PCH_GPIO59 AT5 SLP_CHG_CB1 AK4 SLP_CHG_CB1 PCH_GPIO47 AB6 U4 Y3 T163 @ P3 T139 @ Y2 PCH_GPIO71 AT3 T168 @ PCH_GPIO14 AH4 AM4 T169 @ PCH_GPIO45 AG5 PCH_GPIO46 AG3 JPW @ +3VALW _PCH RP34 10K_0804_8P4R_5% SLP_CHG_CB1 10K_0804_8P4R_5% RP35 LAN_EN USB_OC#0 SMB_ALERT# SML0CLK SML0DATA PCH_SMBDATA USB_OC#2 C EC_SCI# RP28 +3VS PCH_GPIO27 PASSW ORD_CLEAR# 10K_0804_8P4R_5% EC_LID_OUT# ODD_EN# ODD_DA# PCH_GPIO24 PCH_GPIO27 PCH_GPIO28 PCH_GPIO26 BMBUSY/GPIO76 GPIO8 LAN_PHY_PWR_CTRL/GPIO12 GPIO15 GPIO16 GPIO17 GPIO24 GPIO27 GPIO28 GPIO26 CPU/ MISC THERMTRIP RCIN/GPIO82 SERIRQ PCH_OPI_RCOMP RSVD RSVD DEVSLP1 PCH_SPKR AM3 AM2 P2 C4 L2 N5 V2 PCH_GPIO9 EC_SCI# T136 @ DEVSLP1 PCH_SPKR GPIO56 GPIO57 GPIO58 GPIO59 GPIO44 GPIO47 GPIO48 GPIO49 GPIO50 HSIOPC/GPIO71 GPIO13 GPIO14 GPIO25 GPIO45 GPIO46 GPIO LPIO GPIO9 GPIO10 DEVSLP0/GPIO33 SDIO_POWER_EN/GPIO70 DEVSLP1/GPIO38 DEVSLP2/GPIO39 SPKR/GPIO81 ODD_DETECT# DGPU_PW R_EN D60 H_THERMTRIP# V4 KB_RST# T4 SERIRQ AW15 PCH_OPIRCOMP AF20 @ T106 AB21 @ T32 GSPI0_CS/GPIO83 GSPI0_CLK/GPIO84 GSPI0_MISO/GPIO85 GSPI0_MOSI/GPIO86 GSPI1_CS/GPIO87 GSPI1_CLK/GPIO88 GSPI1_MISO/GPIO89 GSPI_MOSI/GPIO90 UART0_RXD/GPIO91 UART0_TXD/GPIO92 UART0_RTS/GPIO93 UART0_CTS/GPIO94 UART1_RXD/GPIO0 UART1_TXD/GPIO1 UART1_RST/GPIO2 UART1_CTS/GPIO3 I2C0_SDA/GPIO4 I2C0_SCL/GPIO5 I2C1_SDA/GPIO6 I2C1_SCL/GPIO7 SDIO_CLK/GPIO64 SDIO_CMD/GPIO65 SDIO_D0/GPIO66 SDIO_D1/GPIO67 SDIO_D2/GPIO68 SDIO_D3/GPIO69 10 OF 19 R6 L6 N6 L8 R7 L5 N7 K2 J1 K3 J2 G1 K4 G2 J3 J4 F2 F3 G4 F1 E3 F4 D3 E4 C3 E2 @ @ PCH_GPIO3 @ PCH_GPIO5 PM_I2CSDA1 PM_I2CSCL1 PCH_GPIO64 PCH_GPIO65 PCH_GPIO66 PCH_GPIO67 PCH_GPIO68 SSD_Detect T111 T133 R219 10K_0402_5% OPT@ DIS,Optimus UMA R30 0_0402_5% @ +3VALW _PCH PCH_GPIO86 R247 10K_0402_5% * R274 @ 1K_0402_5% PM_I2CSCL1 R272 @ 1K_0603_5% R269 resistors value @ 1K_0402_1% PCH_SPKR B PROJECT_ID SPKR / GPIO81 : NO REBOOT 1: ENABLED * 0: DISABLED (Have internal PD) 1K_0402_5% 1: ENABLED 0: Intel ME TLS with no confidentiality 0: SPI ROM (Have internal PD) (Have internal PD) PCH_GPIO66 R270 @ 1K_0402_1% SDIO_D0 / GPIO66 : Top-Block Swap Override * * Deciphered Date 1: ENABLED (Have internal PU) 0: DISABLED A Compal Electronics, Inc Compal Secret Data 2012/07/10 2013/07/10 Title HSW MCP(6/11) GPIO,LPIO Size Document Number Custom Rev 0.1 ZRMAA/ZEMAA Date: PM_I2CSDA1 GPIO69 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC C +3VS 1: Intel ME TLS with confidentiality Security Classification ESD@ ODD_DA# CH6 180P_0402_50V8J Need to check the GSPI0_MOSI / GPIO86 : Boot BIOS Strap Issued Date HDMI_HPD EC_LID_OUT# GPIO15 : TLS Confidentiality A R273 @ +3VS Ultra Non-Ultra 2 DGPU_PRSNT# SSD_Detect H_THERMTRIP# PM_I2CSDA1 PM_I2CSCL1 GPIO87 DGPU_PRSNT# SSD_Detect R144 1K_0402_5% Rev1p2 1 R306 10K_0402_5% UMA@ +1.05VS_VTT T132 R215 10K_0402_5% B KB_RST# SERIRQ R145 49.9_0402_1% PCH_GPIO83 PCH_GPIO84 PCH_GPIO85 PCH_GPIO86 DGPU_PRSNT# PCH_GPIO88 PCH_GPIO89 @ T135 @ T134 PCH_GPIO92 PCH_GPIO93 @ T114 +3VS +3VS 1 EC_LID_OUT# P1 AU2 AM7 AD6 Y1 T3 AD5 AN5 AD7 AN3 DGPU_HOLD_RST# CLKREQ_W LAN# @ @ CH12 ESD@ 0.1U_0402_10V7K T162 T167 DEVSLP1 ODD_DA# 10K_0804_8P4R_5% C yb er Fo ru m ru RP27 Sheet Sunday, April 07, 2013 10 of 49 For EMI reserve close to codec 35 37 CA23 CPVEE 34 CA20 CA21 CA22 2 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M LDO1-CAP LDO2-CAP LDO3-CAP 27 39 SPKLSPKL+ SPKRSPKR+ 43 42 44 45 close to pin, 10mil AC_VREF 2 CA12 0.1U_0402_10V7K COMBO_GPI 48 RA2 282@ 0_0402_5% CA25 2.2U_0603_10V6K 25 38 49 CBN CBP SDATA-IN SDATA-OUT CPVEE BCLK LDO1-CAP LDO2-CAP LDO3-CAP SYNC PCBEEP SPK-OUT-LSPK-OUT-L+ SPK-OUT-RSPK-OUT-R+ SPDIF-OUT/GPIO2 DVSS AVSS1 AVSS2 Thermal Pad Sense A Sense B MIC1-L(PORT-B-L) MIC1-R(PORT-B-R) MIC2-L(PORT-F-L) MIC2-R(PORT-F-R) LINE1-L(PORT-C-L) LINE1-R(PORT-C-R) LINE2-L(PORT-E-L) LINE2-R(PORT-E-R) RESETB PDB DGND INT_MIC_DATA AZ_BITCLK_HD AZ_BITCLK_HD AZ_SYNC_HD MONO_IN 13 14 SENSE_A CA40 0.1U_0402_10V7K close to pin26 close to pin3 CA44 0.1U_0402_10V7K 19 20 17 18 close to pin40 CA51 CA52 MIC2_R_C_L MIC2_R_C_R 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 22 21 24 23 47 AZ_RST_HD# EC_MUTE# RA50 4.7K_0402_5% @ CA8 0.1U_0402_16V4Z CA65 0.01U_0402_25V7K @ESD@ close to pin1 SPK IF need cost down and don't care common design RA63 change to 1K RA62 change to reserve CA71 2 47K_0402_5% SPKL+ 0.1U_0402_10V7K RA62 4.7K_0402_5% Impedance SENSE A Codec Signals Function 39.2K PORT-I (PIN 32, 33) Headphone out 20K PORT-B (PIN 21, 22) Ext MIC 10K PORT-C (PIN 23, 24) (PIN 48) +1.5VS CA41 10U_0603_6.3V6M RA68 0_0603_5% +3VS CA43 10U_0603_6.3V6M 2 close to pin9 Combo Jack 30mil +MIC2_VREFO MIC2_LINE1_R_R @ RA11 0_0603_5% SPK_L1 @ RA12 0_0603_5% SPK_L2 RA69 2.2K_0402_5% RA35 EXT_MIC 1K_0402_5% LA8 @ RA13 0_0603_5% SPK_R1 SPKR- @ RA14 0_0603_5% SPK_R2 1 2 11 EMI@ SBY100505T-470Y-N 0402 22K_0402_5% HP_R LA7 Rshort@ 0_0402_5% HP_L LA6 Rshort@ 0_0402_5% @EMI@ CA45 1000P_0402_50V7K B PR +DVDD PL 1 CA75 2 CA74 @EMI@ EXT_MIC_L if need EMI material will use SM01000GK00 SPKR+ @EMI@ CA42 1000P_0402_50V7K CA48 10U_0603_6.3V6M CA46 1000P_0402_50V7K @EMI@ Change material to SM01000GK00 MIC2_LINE1_R_L COMBO_GPI C @ RA45 0_0603_5% @ RA46 0_0603_5% @ RA42 0_0603_5% @EMI@ RA32 0_0603_5% @EMI@ RA31 0_0603_5% NBA_PLUG# @EMI@ RA5 100K_0402_5% Q5539B 2N7002DW-T/R7_SOT363-6 NBA_PLUG 5.1K CA11 0.1U_0402_16V4Z Enable Disable CA47 1000P_0402_50V7K @EMI@ For better sound by customer request Sense Pin RA65 0_0603_5% RA71 SPKL- CA27 100P_0402_50V8J B 1 close to pin36 For EMI reserve close to codec MONO_IN +AVDD2 +5VS CA39 10U_0603_6.3V6M 100P_0402_50V8J RA63 1 Internal AMP PCI Beep D RA28 0_0603_5% CA7 0.1U_0402_16V4Z Reserve for solve noise issue PCH_SPKR +DVDD 11 EC_MUTE# Hight LOW Beep sound +AVDD1 MIC2_LINE1_R_L MIC2_LINE1_R_R AGND INT_MIC_CLK AZ_SDIN0_HD AZ_SDOUT_HD 10 12 For EMI reserve INT_MIC_CLK_R RA66 CAM_EMI@ FBMA-10-100505-301T AZ_SDIN0_HD_R RA67 33_0402_5% ALC282-CG_MQFN48_6X6 C CA38 0.1U_0402_10V7K close to pin46 CBN CBP 2.2U_0603_10V6K GPIO0/DMIC-DATA GPIO1/DMIC-CLK 2.2U_0603_10V6K HPOUT-L(PORT-I-L) HPOUT-R(PORT-I-R) CA36 10U_0603_6.3V6M 2 CA53 10P_0402_50V8J EMI@ CA24 VREF +PVDD +PVDD +DVDD 100P_0402_50V8J HPOUT_L 32 HPOUT_R 33 75_0402_1% 75_0402_1% 41 46 36 close to pin41 AZ_BITCLK_HD RA41 10_0402_5% EMI@ CA69 RA20 RA21 +AVDD1 +AVDD2 +5VS HP_L HP_R PVDD1 PVDD2 CPVDD 26 40 RA27 0_0603_5% D AVDD1 AVDD2 JDREF +DVDD +DVDD RA70 15 AC_VREF 28 CA61 EMI@ 220P_0402_50V7K 20K_0402_1% JDREF DVDD DVDD-IO RA38 MONO-OUT MIC2-VREFO MIC1-VREFO-R MIC1-VREFO-L +PVDD CA34 0.1U_0402_10V7K C yb er Fo ru m ru 16 29 30 31 22K_0402_5% UA1 +MIC2_VREFO 100P_0402_50V8J A SENSE B 39.2K PORT-E (PIN 14, 15) 20K PORT-F (PIN 16, 17) 10K PORT-H (PIN 20) place close to chip A NBA_PLUG# RA61 Need connector list, check normal close or open apple or nokia for Combo Jack normal Close Compal Secret Data Security Classification Issued Date SENSE_A 39.2K_0402_1% 2012/07/25 2013/07/25 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Compal Electronics, Inc Cover Sheet Rev 0.1 Sheet Sunday, April 07, 2013 35 of 49 B C UB1 RB4 10_0402_5% @EMI@ CB11 22P_0402_50V8J @EMI@ 10 KB_RST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 EC_SCI# WOWL_EN# EC_RST# CB12 0.1U_0402_10V7K KSI[0 7] KSI[0 7] KSO[0 17] +3VL 2 CHG_PWR_GATE# 10K_0402_5% RPB1 +3VS EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 PM_SLP_S3# PM_SLP_S5# EC_SMI# USB_OC#2 USB_CHG_OC# USB_CHG_EN# USB_EN#2 KB_LED FAN_SPEED1 WL_OFF# E51_TXD E51_RXD PCH_PWROK BT_ON E51_TXD RB7 14 15 16 17 18 19 25 28 29 30 31 32 34 36 E51_TXD E51_RXD 0_0402_5% 122 123 CLK_EC_R KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 EC_SMB_CK1/GPIO44 EC_SMB_DA1/GPIO45 SM EC_SMB_CK2/GPIO46 EC_SMB_DA2/GPIO47 PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 GPIO0A GPIO0B GPIO0C GPIO0D EC_INVT_PWM/GPIO11 FAN_SPEED1/GPIO14 EC_PME#/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 PCH_PWROK/GPIO18 SUSP_LED#/GPIO19 NUM_LED#/GPIO1A XCLKI/GPIO5D XCLKO/GPIO5E 2 Signal pull high is default status (ROM only mode) If signal pull low, EC will send translator code to chip.(EP mode) +3VL CB16 20P_0402_50V8 @ RR8 0_0402_5% @ SPI Flash ROM GPIO Bus @ GPIO AC_IN/GPXIOD01 EC_ON/GPXIOD02 ON/OFF/GPXIOD03 GPI LID_SW#/GPXIOD04 SUSP#/GPXIOD05 GPXIOD06 PECI_KB9012/GPXIOD07 V18R EC_CB1 GPS_DOWN# PWRME_CTRL VCIN0_PH GPS_DOWN# @ 10K_0402_5% +3VL WLAN_WAKE# WLAN_WAKE# WOL_EN# CHG_PWR_GATE# BATT_FULL_LED# CAPS_LED# PWR_SUSP_LED# BATT_CHG_LOW_LED# SYSON VCCST_PG_EC FB_CLAMP CHG_PWR_GATE# SYSON PCH_RSMRST# EC_LID_OUT# PROCHOT_IN H_PROCHOT#_EC VCOUT0_PH_L LID_SW# RB35 47K_0402_5% WLAN_WAKE# RB37 47K_0402_5% +3VS TP_CLK RB8 4.7K_0402_5% TP_DATA RB9 4.7K_0402_5% EC_SMB_CK3 RB15 2.2K_0402_5% EC_SMB_DA3 RB16 2.2K_0402_5% SYSON RB10 4.7K_0402_5% SUSP# RB21 10K_0402_5% VCIN0_PH connect to power portion (9012 only) EC_SDIO EC_SDI EC_SCK EC_CS0# PROCHOT_IN connect to power portion (9012 only) BKOFF# PBTN_OUT# PCH_PWR_EN EC_SWI# 110 112 114 115 116 117 118 ACIN EC_ON_R 124 +EC_V18R ACIN ON/OFFBTN# LID_SW# SUSP# LID_SW# SUSP# +VTT_EC EC_PECI KB9012QF-A3_LQFP128_14X14 9012@ UB1 NPCE885NB0DX LQFP 128P 885@ 885@ RB3 RB19 2 0_0402_5% 43_0402_5% VCOUT0_PH_L RB34 @ 0_0402_5% VS_ON VCOUT0_PH connect to power portion (9012 only) +1.05VS_VTT H_PECI CB15 4.7U_0805_10V4Z 885@ RB20 330K_0402_5% 2 CB10 100P_0402_50V8J 0_0402_5% EC_MUTE# PM_SLP_S4# EC_SMB_CK3 EC_SMB_DA3 TP_CLK TP_DATA EC_SMB_CK3 EC_SMB_DA3 TP_CLK TP_DATA 100 101 102 103 104 105 106 107 108 EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04 PROCHOT_IN/GPXIOA05 H_PROCHOT#_EC/GPXIOA06 VCOUT0_PH/GPXIOA07 GPO BKOFF#/GPXIOA08 PBTN_OUT#/GPXIOA09 PCH_APWROK/GPXIOA10 SA_PGOOD/GPXIOA11 100P_0402_50V8J LAN_WAKE# H_PROCHOT#_EC RB6 EC_CB0 Reserve this signal to EC by SW demand 2011/10/18a 73 74 89 90 91 92 93 95 121 127 ENBKL/GPIO40 PECI_KB930/GPIO41 FSTCHG/GPIO50 BATT_CHG_LED#/GPIO52 CAPS_LED#/GPIO53 PWR_LED#/GPIO54 BATT_LOW_LED#/GPIO55 SYSON/GPIO56 VR_ON/GPIO57 PM_SLP_S4#/GPIO59 @ CB9 VCCST_PWRGD 119 120 126 128 SPIDI/GPIO5B SPIDO/GPIO5C SPICLK/GPIO58 SPICS#/GPIO5A CB8 47P_0402_50V8J +3VS CB0_WAKE# RR9 SPI Device Interface +3VL 9012@ EC_ON_R RB36 0_0402_5% QB2 EC_ON 1 RB26 10K_0402_5% 1U_0402_6.3V6K CB50 @ Close to EC SUSP# G 885_EC_ON Voltage Comparator Pins FOR 9012 A3 For Translator select 885@ 2N7002K_SOT23-3 H_PROCHOT# ACIN 885_EC_ON CB0_WAKE# RB25 10K_0402_5% @ S BATT_PRES EC_ENBKL 97 98 99 109 CPU1.5V_S3_GATE/GPXIOA00 WOL_EN/GPXIOA01 ME_EN/GPXIOA02 VCIN0_PH/GPXIOD00 TRANS_SEL D BATT_PRES USB_OC#0 ADP_I ADP_V TRANS_SEL 83 84 85 86 87 88 EC_MUTE#/GPIO4A USB_EN#/GPIO4B CAP_INT#/GPIO4C EAPD/GPIO4D TP_CLK/GPIO4E TP_DATA/GPIO4F PS2 Interface 11 24 35 94 113 @ RB22 100K_0402_5% LVDS@ BATT_PRES 68 70 71 72 DAC_BRIG/GPIO3C EN_DFAN1/GPIO3D IREF/GPIO3E CHGVADJ/GPIO3F DA Output POK 77 78 79 80 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 2.2K_8P4R_5% RB27 100K_0402_5% 63 64 65 66 75 76 BATT_TEMP/GPIO38 GPIO39 ADP_I/GPIO3A GPIO3B GPIO42 IMON/GPIO43 S +3VL AD Input WL_BT_LED# USB_EN#0 FANPWM CLK_REQ_GC6# D RB12 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 ESD@ PLT_RST# CB13 0.1U_0402_10V7K KSO[0 17] 21 23 26 27 GPIO0F BEEP#/GPIO10 GPIO12 ACOFF/GPIO13 PWM Output CLK_PCI_EC PCIRST#/GPIO05 EC_RST# EC_SCII#/GPIO0E GPIO1D 0_0402_5% @ G QB1 2N7002_SOT23-3 C yb er Fo ru m ru RB2 47K_0402_5% 12 13 37 20 38 CLK_PCI_EC PLT_RST# EC_RST# CLK_PCI_EC PLT_RST# +3VL GATEA20/GPIO00 KBRST#/GPIO01 SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC & MISC LPC_AD0 RB1 VR_HOT# H_PROCHOT#_EC AGND/AGND E 67 0.1U_0402_10V7K EC_VDD/AVCC CB4 69 22 33 96 111 125 CLK_PCI_EC EC_VDD/VCC EC_VDD/VCC EC_VDD/VCC EC_VDD/VCC EC_VDD0 EC_VDD/VCC CB1 0.1U_0402_10V7K For EMI CB3 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 1 CB2 @ @ CB5 GND/GND GND/GND GND/GND GND/GND GND0 D +3VL +3VL A @ JDB E51_TXD E51_RXD +3VS VCIN0 pin109 VCIN1 pin102 >1.2V VCOUT0 pin104 HIGH (default) VCOUT1 pin103 ACES_85205-0400 ESD@ 180P_0402_50V8J HIGH