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A B C D E 1 Compal Confidential 2 QCL40 MB Schematic Document LA-8224P 3 Rev: 0.2 2011.09.28 4 Compal Secret Data Security Classification 2011/07/12 Issued Date 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Compal Electronics, Inc Cover Sheet Size Document Number Custom Rev 0.2 LA-8224P Date: Thursday, October 27, 2011 Sheet E of 59 Compal Confidential QCL40 ZZZ1 PCB-MB PCB P/N for Load BOM NV N13M-GE1 Gb1B-64 23x23mm PEG 16X +1.5V, +0.75VS port USB conn x1 USB Board port 100MHz 5GB/s Camera Page 30 HDMI Card Reader RTS5137 port 10 RGB, HV Sync, DDC HDMI, DDC Page 35 Page 30 USB2.0 LVDS, EDID, DISPOFF#, PWM Page 30 Page 33 DMI x4 100MHz 2.7GT/s CRT Conn A Page 10, 11 rPGA 988B Socket Page ~ +VCC_CORE, +VCCP, +VCC_GFXCORE_AVG, +1.5V_CPU_VDDQ, +1.8VS, _VCCSA FDI x8 (UMA) B BANK 0, 1, 2, Dual Channel Ivy Bridge Processor Page 20 ~ 28 LCD conn DDR3-SO-DIMM X DDR3 1333/1600MHz 1.5V Mobile DA80000QT00 A Memory Card Slot SD/MMC Page 34 Page 34 Intel PANTHER-POINT PCH B port MiniCard-2 Page 40 port 0,1 USB3.0 USB3.0 conn x2 port 1,2 Page 36 HM77 Audio Jack (HP) Azalia Realtek ALC269 FCBGA 989 Balls Page 12 ~ 19 Page 33 Audio Jack (MIC) Page 33 SATA Speaker Connector Page 33 Page 33 C C PCI-e port ASM1042 USB3.0 Controller page 36 port port LAN/CRT Board 10/100/1000 LAN Realtek GbE RTL8111F port +1.05VS, +1.8VS, +3VS, +3V_PCH, +5V_PCH, +RTCVCC, +VCCAFDI_VRM Page 31 Mini Card-1 WLAN Bluetooth port Page 31 USB3.0 conn x2 SPI ROM 4MB+2MB Touch Pad CONN External board Page 29,41 LS-4221P USB/B Page 38 ENE KB9012QF Reserve KB930F +3VLP/+3VALW page 39 Int KBD D Page 38 Page 33 SPI ROM 256KB Fan Control Page 37 Page 12 LPC BUS Page 37 DC/DC Interface CKT SATA ODD Connector Page 40 Page 32 SPI D 2.5" SATA HDD Connector Compal Secret Data Security Classification Issued Date Page 39 2011/07/12 Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc Block Diagram Size Document Number Custom Date: Rev 0.2 LA-8224P Thursday, October 27, 2011 Sheet of 59 A X76@: VRAMX16X8 N13P-GS ZZZ11 VRAMX16X4 N13P-GL X76L11@ ZZZ X76L01@ VRAMX8X8 N13M-GE1 N13M-GE1 x8 ZZZ3 ZZZ7 X76L03@ PCI0 ER39 2G HYN 2G SAM ZZZ12 X76L12@ 2G SAM ZZZ2 1G SAM X76L02@ ZZZ4 2G HYN ZZZ5 2G HYN X76L04@ ZZZ8 1G HYN X76L08@ ZZZ9 1G SAM X76L09@ N13P-GS N13M-GE1 GE@ GL@ U10 U10 GS@ U10 N13M-GE1 x8 GE8@ GE@ U10 N13M-GE1 x8 N13P-GL IU3@: USB3.0 by PCH USB30@:USB3.0 controller IC AI@: AI Charger NAI@: Non AI Charger DIS@: VGA componet GE8@: N13M-GE1_GB1b GE8@ GL@ N13M-GE1 N13P-GS X76L10@ 4G HYN N13P-GL GS@ 9012@: EC(ENE 9012 chip) 930@: EC(ENE 930 chip) XDP@: Intel debug port BATT PCH EC SODIMM DGPU V X X V X X X X X V PCH V X X X V X PCH X X X V X V KB930 EC_SMB_CK2 EC_SMB_DA2 KB930 PCH_SMBCLK PCH_SMBDATA PCH_SMLCLK PCH_SMLDATA CLK MINI1 X X EC_SMB_CK1 EC_SMB_DA1 PCI1 EC PCI2 None PCH LPC Debug Port PCI4 USB2.0+3.0 USB2.0+3.0 USB2.0+3.0 None None None None JMINI1 (WLAN) Bluetooth None None None None Power Plane Description S1 S3 VIN Adapter power supply (19V) N/A Deep S3 N/A N/A BATT+ Battery power supply (12.6V) N/A N/A N/A N/A B+ AC or battery power rail for power circuit N/A N/A N/A N/A +3VLP 3.3V power rail for 51ON power management ON ON ON ON N/A +3VALW 3.3V always on power rail ON ON ON +LAN_IO 3.3V power rail for ethernet ON ON OFF +3VS_WLAN 3.3V power rail for WLAN/BT Combo ON OFF OFF OFF +3V_PCH 3.3V power rail for PCH suspend well plane ON ON OFF OFF +3VS 3.3V power rail for DDR SPI,PCH,HDD,Audio,Card Reader ON OFF OFF OFF +3VSG 3.3V power rail for VGA ON OFF OFF OFF PCH AC/ON; DC/OFF CAMERA USB2 10 Card Reader 11 None 12 None 13 None OFF +LCDVDD 3.3V power rail for LCD ON OFF OFF +5VALW 5V always on power rail ON ON ON +5V_PCH 5V power rail for PCH suspend well plane ON ON OFF OFF +5VS 5V power rail for HDD,AUDIO,FAN,Touch PAD ON OFF OFF OFF +5VS_ODD 5V power rail for SATA ODD ON OFF OFF OFF +1.8VS 1.8V power rail for CPU,PCH ON OFF OFF OFF +1.05VS 1.05V power rail for PCH ON OFF OFF OFF +VCCP 1.05V power rail for CPU VCCIO,PCH ON OFF OFF OFF +1.05VSG 1.05V power rail for N13P ON OFF OFF OFF +1.5V 1.5V power rail for DDR3 system memory ON ON ON OFF +1.5V_CPU_VDDQ 1.5V power rail CPU VDDQ ON OFF OFF OFF +1.5VSG 1.5V power rail for N13P,VRAM ON OFF OFF OFF +1.5VS 1.5V power rail for PCH,WLAN/BT combo ON OFF OFF OFF +0.75VS 0.75V power rail for DDR VREF ON OFF OFF OFF +VCCSA VCCSA for CPU system agent ON OFF OFF OFF +VCC_CORE CORE Voltage for CPU ON OFF OFF OFF 1.5V power rail for N13P,VRAM ON OFF OFF OFF CORE Voltage for N13P Graphics ON OFF OFF ON OFF OFF OFF +VCC_GFXCORE_AXG +VGA_CORE SATA DESTINATION SATA0 HDD SATA1 None DIFFERENTIAL DESTINATION FLEX CLOCKS DESTINATION SATA2 ODD CLKOUT_PCIE0 10/100/1G LAN CLKOUTFLEX0 CLK_SD_48M SATA3 None CLKOUT_PCIE1 MINI CARD WLAN CLKOUTFLEX1 None SATA4 None CLKOUT_PCIE2 None CLKOUTFLEX2 None SATA5 None CLKOUT_PCIE3 USB3.0 controller CLKOUTFLEX3 None CLKOUT_PCIE4 None CLKOUT_PCIE5 None CLKOUT_PCIE6 None CLKOUT_PCIE7 None CLKOUT_PEG_B S5 OFF AC/ON; DC/OFF SMBUS Control Table SOURCE DESTINATION USB2.0+3.0 X76L06@ 1G HYN USB2 PORT Voltage Rails 4G ELP ZZZ10 ZZZ6 USB3 PORT DESTINATION PCH_LOOPBACK PCI3 2G ELP X76L05@ DESTINATION CLKOUT X76L07@ None PCI EXPRESS DESTINATION Lane 10/100/1G LAN Lane MINI CARD WLAN Lane None Lane USB3.0 controller Lane None Lane None Lane None Lane None Symbol Note : : means Digital Ground Compal Secret Data Security Classification : means Analog Ground Issued Date 2011/07/12 Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size C Date: A Compal Electronics, Inc Notes List Document Number Rev 0.2 LA-8224P Thursday, October 27, 2011 Sheet of 59 1 +1.05VS R1 24.9_0402_1% JCPU1A D 14 14 14 14 DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 B27 B25 A25 B24 14 14 14 14 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 B28 B26 A24 B23 14 14 14 14 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 G21 E22 F21 D21 DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] 14 14 14 14 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 G22 D22 F20 C21 DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] 14 14 14 14 14 14 14 14 +1.05VS FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 14 FDI_FSYNC0 14 FDI_FSYNC1 14 FDI_INT R2 14 FDI_LSYNC0 14 FDI_LSYNC1 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 A21 H19 E19 F18 B21 C20 D18 E17 FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 A22 G19 E20 G18 B20 C19 D19 F17 FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] FDI_FSYNC0 FDI_FSYNC1 J18 J17 FDI0_FSYNC FDI1_FSYNC FDI_INT H20 FDI_LSYNC0 FDI_LSYNC1 J19 H17 DMI DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] FDI_INT FDI0_LSYNC FDI1_LSYNC 24.9_0402_1% B eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance 上 上1(CSD17308)下 下1(TPCA8059) Gfx_core >上 上1(CSD17308)下 下1(TPCA8057) PR268 4.7_1206_5% QC 45W CPU solution: 3+2 MOS: cpu_core >上 上1(CSD17308)下 下1(TPCA8059) Gfx_core >上 上1(CSD17308)下 下1(TPCA8059) CSREF 51 10_0402_1% PC296 SWN3 51 680P_0402_50V7K PQ208 SNUB_GFX1 6132_PWM DRVEN +5VS PR287 2 PR267 1EN_GFX2 2K_0402_1% 1VCC_GFX2 PR273 PR276 0_0402_5% 0_0402_5% CSREFA 51 10_0402_1% PWM EN VCC DRVH SW GND DRVL SW2A LG2A PC290 PC294 2200P_0402_25V7K +VCC_GFXCORE_AXG PR269 4.7_1206_5% NCP5911MNTBG_DFN8_2X2 PC298 2.2U_0603_10V7K S TR FDMS0308AS 1N POWER56-8 680P_0402_50V7K B PL205 0.36UH_VMPI1004AR-R36M-Z03_30A_20% PQ210 PC293 0.1U_0402_25V6 PC209 10U_0805_25V6K HG2A SWN1A 51 S TR FDMS0308AS 1N POWER56-8 51 51 V2N_GFX PR286 4.7_1206_5% FLAG @ PQ215 @S TR AON7518 1N DFN 0.36UH_VMPI1004AR-R36M-Z03_30A_20% LG1A BST PR229 0_0603_5% 1 DRVL 51 GND PC288 2200P_0402_25V7K PC287 0.1U_0402_25V6 VCC 2 NCP5911MNTBG_DFN8_2X2 PC289 2.2U_0603_10V7K PC205 10U_0805_25V6K SW1A PR270 10_0402_1% SNUB_GFX2 SW PU203 PL203 PQ209 S TR AON7518 1N DFN EN DRVH PC295 0.22U_0402_10V6K PWM BSTA2_1 +VCC_GFXCORE_AXG V1N_GFX HG1A PR288 2.2_0603_5% 1EN_GFX1 51 DRVEN 2K_0402_1% +5VS 1VCC_GFX1 PR272 PR275 0_0402_5% 0_0402_5% BSTA2 PR285 FLAG 51 6132_PWMA BST PR225 0_0603_5% @ PQ214 @S TR AON7518 1N DFN PQ205 S TR AON7518 1N DFN PU202 1 PC286 0.22U_0402_10V6K BSTA1_1 PC206 10U_0805_25V6K PR284 2.2_0603_5% BSTA1 2Phase: install 1Phase:: @ PC210 10U_0805_25V6K AXG_B+ AXG_B+ B CSREFA SWN2A 51 PC297 680P_0402_50V7K A A QC 45W GT2 VID1=1.23V IccMax=46A Icc_Dyn=37A Icc_TDC=38A R_LL=3.9m ohm OCP~55A DC 35W GT2 VID1=1.23V IccMax=33A Icc_Dyn=20.2A Icc_TDC=21.5A R_LL=3.9m ohm OCP~40A Compal Secret Data Security Classification Issued Date 2009/12/01 Deciphered Date 2010/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR-CPU_CORE Size C Date: Compal Electronics, Inc Document Number Rev 0.2 PBL22 LA-7391P M/B Thursday, October 27, 2011 Sheet 52 of 59 2 2 1 1 2 2 PC1158 22U_0805_6.3V6M 2 2 + + PC765 + @330U_D2_2V_Y 2 + PC764 + 330U_D2_2V_Y 2 PC1166 + PC1165 PC1126 22U_0805_6.3V6M PC761 22U_0805_6.3V6M PC760 22U_0805_6.3V6M @330U_D2_2V_Y PC1125 22U_0805_6.3V6M + PC1164 PC1124 22U_0805_6.3V6M 330U_D2_2V_Y PC1123 22U_0805_6.3V6M 2 PC1120 22U_0805_6.3V6M 330U_D2_2V_Y PC1122 22U_0805_6.3V6M 2 PC1163 PC1121 22U_0805_6.3V6M PC1119 22U_0805_6.3V6M 330U_D2_2V_Y PC1118 22U_0805_6.3V6M PC763 PC1117 22U_0805_6.3V6M 330U_D2_2V_Y PC1116 22U_0805_6.3V6M 1 PC762 22U_0805_6.3V6M C 1 PC759 22U_0805_6.3V6M 1 PC758 22U_0805_6.3V6M 1 PC757 22U_0805_6.3V6M PC1115 22U_0805_6.3V6M +1.05vs 1 PC756 22U_0805_6.3V6M PC755 22U_0805_6.3V6M PC1114 22U_0805_6.3V6M PC1162 22U_0805_6.3V6M PC754 22U_0805_6.3V6M PC1113 22U_0805_6.3V6M PC1161 22U_0805_6.3V6M PC753 22U_0805_6.3V6M PC1112 22U_0805_6.3V6M PC1160 22U_0805_6.3V6M PC752 22U_0805_6.3V6M PC1111 22U_0805_6.3V6M PC1159 22U_0805_6.3V6M Socket Top x 22 µF (0805) x (0805) no-stuff sites +1.05vs PC751 22U_0805_6.3V6M PC1157 22U_0805_6.3V6M PC1156 22U_0805_6.3V6M 1 x 22 µF (0805) x (0805) no-stuff sites D PC1155 22U_0805_6.3V6M PC1154 22U_0805_6.3V6M PC1110 10U_0805_6.3V6M PC1153 22U_0805_6.3V6M PC1109 10U_0805_6.3V6M +VCC_CORE Socket Bottom +VCC_GFXCORE_AXG PC1152 22U_0805_6.3V6M PC1108 10U_0805_6.3V6M Below is 458544_CRV_PDDG_0.5 Table 5-8 +VCC_GFXCORE_AXG PC1151 22U_0805_6.3V6M PC1107 10U_0805_6.3V6M PC1105 10U_0805_6.3V6M D PC1106 10U_0805_6.3V6M PC1104 10U_0805_6.3V6M PC1103 10U_0805_6.3V6M 2 PC1102 10U_0805_6.3V6M 2 PC1101 10U_0805_6.3V6M 1 +VCC_CORE 1 +VCC_CORE C +VCC_CORE Chief River + + PC1127 330U_D2_2V_Y 2 PC1128 330U_D2_2V_Y + PC1129 330U_D2_2V_Y + 330uF*9m 470uF*4.5m 22uF 10uF 16 10 PC1130 330U_D2_2V_Y + PC1131 330U_D2_2V_Y 8layer for DC CPU B B 8layer for QC CPU 16 10 6layer for DC CPU 16 10 6layer for QC CPU 16 10 GFX_CORE DC 12 GFX_CORE QC 12 1.05V_VCCP 12 A A Compal Secret Data Security Classification 2008/09/15 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc PWR - PROCESSOR DECOUPLING Size Document Number Rev 0.2 LA-8224P Date: Thursday, October 27, 2011 Sheet 53 of 59 A B C D BOOT2_2_VGA UGATE2_VGA 2 PC926 47U_0805_6.3V6M PC935 4.7U_0603_6.3V6M PC927 @22U_0805_6.3V6M PC934 4.7U_0603_6.3V6M PC928 22U_0805_6.3V6M PC933 4.7U_0603_6.3V6M PC929 22U_0805_6.3V6M PC930 22U_0805_6.3V6M PC906 10U_0805_25V6K PC905 10U_0805_25V6K PC953 2200P_0402_50V7K S TR AON7518 1N DFN PL901 0.36UH_VMPI1004AR-R36M-Z03_30A_20% SNUB1_VGA +VGA_CORE V1N_VGA PR939 1_0402_1% + Layout Note: Place near Phase1 Choke + VSUM-_VGA 1P : @ 2P: install VSUM+_VGA PC902 330U_D2_2V_Y S TR FDMS0309S 1N POWER56-8 PH901 10K_0402_1%_TSM0A103F34D1RZ PR936 4.7_1206_5% PR938 10K_0402_1% LGATE1_VGA PR937 3.65K_0805_1% LF1_VGA PQ902 PC901 330U_D2_2V_Y PHASE1_VGA BOOT1_1_VGA UGATE1_VGA1 PC954 0.22U_0603_10V7K PR934 2.2_0603_5% 3 PR916 0_0603_5% UGATE1_VGA PC952 0.1U_0402_25V6 PQ906 PQ901 @S TR AON7518 1N DFN ISEN1_VGA VSUM-_VGA PC961 680P_0402_50V7K PC962 0.1U_0402_16V7K 20W solution:1P OCP:38A 25W ~30W solution:2P OCP:75A Compal Secret Data Security Classification Issued Date 2008/09/15 Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title B C Compal Electronics, Inc PWR - VGA_COREP Size Document Number Rev 0.2 LA-8224P Date: A PC932 4.7U_0603_6.3V6M 1 PC913 4.7U_0603_6.3V6M PC965 0.1U_0402_10V7K 1 PC912 4.7U_0603_6.3V6M 1 2 VGA的 的的的的的 (20W ~ 35W的 的bulk cap都 都的330uF_9m * 4) 35W > * 0.1uF +15 * 4.7u + 22u * + 330_9m * PC957 0.022U_0603_25V7K 1 +VGA_B+ PR943 1.58K_0402_1% 1P: 0.1uF 2P: 0.22uF Near VGA Core PC931 4.7U_0603_6.3V6M 2 +5VS 1P: 866 2P: 1.58K + PC904 470U 2V M D2 LESR4.5M SX H1.9 SNUB2_VGA PC919 4.7U_0603_6.3V6M PC911 4.7U_0603_6.3V6M PC925 4.7U_0603_6.3V6M PC922 4.7U_0603_6.3V6M PC967 0.1U_0402_10V7K PC924 4.7U_0603_6.3V6M PC921 4.7U_0603_6.3V6M PC966 0.1U_0402_10V7K 1 2 PC920 4.7U_0603_6.3V6M 1 PC951 0.22U_0603_25V7K PC950 1U_0603_10V6K 2 +VGA_B+ PR932 @82.5_0402_5% 1P: @ 2 PC960 @0.01U_0402_25V7K PR942 10_0402_5% PC959 @330P_0402_50V7K PR940 0_0402_5% 2 PC958 0.01U_0402_50V7K PC955 @330P_0402_50V7K VSUM_VGA_N001 +5VS VSUM+_VGA PR931 10_0402_5% PR935 0_0402_5% 24 VSSSENSE_VGA PC949 0.22U_0402_10V6K 1P: @ 2P: 0.22u +5VS VSUM-_VGA 2 23 VCCSENSE_VGA 0_0402_5% 1P: 68nF 2P: 0.022uF PC956 0.22U_0603_10V7K 1 +VGA_CORE 2 1P: install 2P: @ PC943 1U_0603_10V6K BOOT1_VGA PR944 @0_0402_5% PC948 0.22U_0402_10V6K PR930 249K_0402_1% 1P: 120K 2P: @249K +5VS PC968 0.1U_0402_10V7K 1 0_0402_5% PR929 1_0402_5% ISEN1_VGA 2 PR925 IMON_VGA ISEN2_VGA PR928 267K_0402_1% ISL62883CHRTZ-T_TQFN40_5X5 VSEN_VGA 2FB2_VGA1 VCCP_VGA PR933 2.61K_0402_1% NTC_VGA 680P_0402_50V7K PR926 3.48K_0402_1% 1 PC947 150P_0402_50V8J VSUM-_VGA VSUM+_VGA ISEN2_VGA PR921 0_0402_5% PR927 VIN_VGA + Under VGA Core PC923 4.7U_0603_6.3V6M 40 39 38 37 36 35 34 33 32 31 CLK_EN# DPRSLPVR VR_ON VID6 VID5 VID4 VID3 VID2 VID1 VID0 PR946 @0_0402_5% PR920 VCCP_VGA11 0_0402_5% PR941 11K_0402_1% PR924 499_0402_1% PC945 2FB1_VGA1 AGND VDD_VGA 41 30 29 28 27 26 25 24 23 22 21 ISEN1 VSEN RTN ISUMISUM+ VDD VIN IMON BOOT1 UGATE1 PC944 1000P_0402_50V7K PR923 8.06K_0402_1% PC942 @22P_0402_50V8J PC946 47P_0402_50V8J PC941 1U_0603_10V6K 1P : @ 2P: install BOOT2 UGATE2 PHASE2 VSSP2 LGATE2 VCCP PWM3 LGATE1 VSSP1 PHASE1 PGOOD PSI# RBIAS VR_TT# NTC VW COMP FB ISEN3 ISEN2 11 12 13 14 15 16 17 18 19 20 2 10 RTN_VGA ISUM-_VGA RBIAS_VGA PSI#_VGA VGA_VR_TT# NTC_MOSFET_VGA VW_VGA COMP_VGA FB_VGA 2ISEN3_VGA 470K_0402_5%_TSM0B474J4702RE PR922 @249K_0402_1% PU901 @56P_0402_50V8 PR909 1_0402_1% +VGA_CORE PR912 100K_0402_5% PR914 14.7K_0402_1% PH902 2NTC_MOS_VGA +VGA_CORE V2N_VGA +VGA_CORE PR913 0_0402_5% PC909 PC940 1 2 PR918 100K_0402_5% PR919 47K_0402_1% ACIN_BUF 4.7_1206_5% 680P_0402_50V7K 20 PR906 S TR FDMS0309S 1N POWER56-8 PR907 3.65K_0805_1% LGATE2_VGA PD901 @RB751V-40TE17_SOD323-2 +3VS +3VS LF2_VGA PQ904 PR915 1.91K_0402_1% 1P: @ 2P: 100K 1P : @ 2P: install PL902 0.36UH_VMPI1004AR-R36M-Z03_30A_20% CLK_ENABLE#_VGA 29,40 VGA_PWROK PC971 @680P_0603_50V7K 1 @S TR AON7518 1N DFN UGATE2_VGA1 PHASE2_VGA HW端端PU PC908 10U_0805_25V6K PC938 0.22U_0603_10V7K PR911 0_0603_5% 20 20 20 20 20 20 BOOT2_VGA GPU_VID6 GPU_VID5 GPU_VID4 GPU_VID3 GPU_VID2 GPU_VID1 GPU_VID0 PR910 1.91K_0402_1% 1U_0402_16V7K 1P: @ 2P: 1.91K +3VS B+ PC903 330U_D2_2V_Y PC939 DPRSLPVR_VGA PR904 2.2_0603_5% PR908 10K_0402_1% PR905 10K_0402_1% PR903 150K_0402_1% 2VRON_VGA DGPU_PWR_EN PQ905 PL903 HCB2012KF-121T50_0805 PL904 HCB2012KF-121T50_0805 PR902 0_0402_5% GPU_VID5 GPU_VID4 GPU_VID3 GPU_VID2 GPU_VID1 GPU_VID0 PR945 68K_0402_1% 15,20,29 S TR AON7518 1N DFN 2 5 PQ903 PC907 10U_0805_25V6K 1P : @ 2P: install PC937 2200P_0402_50V7K PC936 0.1U_0402_25V6 +VGA_B+ Thursday, October 27, 2011 D Sheet 54 of 59 Power block CPU OTP Page 56 Turn Off D Input Switch Page 57 DC IN D B+ +3VALWP: TDC:6A +5VALWP: TDC:6.1A RT8205LZQW(2) WQFN CHARGER CC:0A~3.64A CV:12.6V(6cell) BQ24725RGRR Always Page 52 +1.8VP: TDC:1.2A SY8033BDBC SUSP# Page 59 Page 57 C Battery Page 60 +V1.05SP: TDC:7.9A TPS51212DSCR Page 61 SUSP# +1.5VP: TDC:16A TPS51212DSCR DGPU_PWR_EN B C SUSP# +VCCPP: TDC:8.5A TPS51212DSCR SYSON Page 62 +VGA_CORE TDC:23A TPS51212DSCR B +0.75VSP: TDC:2A APL5331KAC-TRL Page 65 +3VALW Page 62 +VCCSAP: TDC:4.2A TPS51461RGER +VCC_CORE TDC: 52A ISL95832HRTZ-T VR_ON +V1.05S_VCCP_PWRGOOD Page 63 Page 64 +VCC_GFXCORE_AXG TDC: 38A ISL95832HRTZ-T VR_ON A A Page 64 Compal Secret Data Security Classification 2010/08/03 Issued Date 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc POWER BLOCK DIAGRAM Size Document Number Custom Rev 0.2 LA-8224P Date: Thursday, October 27, 2011 Sheet 55 of 59 Version Change List ( P I R List ) Item Page# Title Date Request Owner Page Issue Description Solution Description Rev D D C C B B A A Compal Secret Data Security Classification 2008/09/15 Issued Date 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc PWR - PIR Size Document Number Rev 0.2 LA-8224P Date: Thursday, October 27, 2011 Sheet 56 of 59 Timing Diagram for G3 or S4-5/M-off (Suspend Well Off) to S0/M0 [non Deep S4/S5 Platform] ACIN/BATT-IN +5VALW/+3VALW D VCCSUS (+5V_PCH/+3V_PCH) D PCH_RSMRST# T3>0ms PM_SLP_SUS# T516ms PM_SLP_S5# PM_SLP_S4# PM_SLP_S3# T9>30us T10>30us C C CPU1.5V_S3_GATE CPU1.5V_S3_GATE may come up before SUSP# and come down after SUSP# T>?ms SUSP# +V1.05S_VCCP(CPU), +V1.05S(VccASW) T=?ms T11>1ms PCH_APWROK may come up anytime before PCH_PWROK, but not after PCH_PWROK assertion PCH_APWROK SA_PGOOD T>?ms VR_ON T33