compal la 8371p r0 2 schematics

A B C D E ÿÿÿÿÿÿÿ 1 Compal Confidential 2 QML70 Schematics Document AMD Comal APU Trinity / Hudson M3 / Thames XT M2 UMA Only / PX Muxless with BACO 3 2011-10-17 LA-8371P REV: 0.2 4 2011/07/29 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/07/29 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Cover Page Size B Date: Document Number Rev 0.2 QML70 LA-8371P Wednesday, October 19, 2011 Sheet E of 53 A B C D E Compal Confidential Model Name : QML70 ZZZ1 VRAM 2G/1G 128M x16 x / 64M x 16 x Comal page 24, 25 PCB 0OG LA-8371P REV0 MB DA80000RG00 DDR3 Thermal Sensor ATI Thames XT M2 uFCBGA-962 ADM1032 page 19 GFX x 16 Gen2 AMD FS1r2 APU Trinity DP x4 (DP0 TXP/N0 ~ 3) +1.0VSG, +1.5VSG, +1.8VSG, +3VSG, +VGA_CORE, +VDDCI Page 18~25 APU HDMI (UMA / Muxless) DP x2 (DP2 TXP/N0 ~ 1) Memory BUS(DDR3) 204pin DDRIII-SO-DIMM X2 Dual Channel Page 11,12 BANK 0, 1, 2, 1.5V DDRIII 800~1333MHz uPGA-722 Package HDMI Conn page 29 +APU_CORE, +APU_CORE_NB, +1.5V, +1.2VS, +2.5VS LVDS Conn LVDS page 28 LVDS Translator RTD2136S-VE-CG P_GPP x GEN1 Page 6~10 DP x4 (DP1 TXP/N0 ~ 3) UMI USB 2.0 + 3.0 page 27 USB 2.0 + 3.0 page 35 FCH CRT (VGA DAC) CRT Conn page 28 GPP1 GPP2 LAN(GbE) RTL8111F-CGT MINI Card WLAN w/ BT page 30 USB FCH Hudson-M3 page 35 USB3.0 Port USB2.0 Port 10 USB2.0 USB2.0 page 30 page 30 USB3.0 Port USB2.0 Port 11 USB2.0 Port CMOS Camera Mini Card (with BT) page 28 USB2.0 Port page 33 USB2.0 Port USB2.0 Port 3.3V 48MHz HD Audio uFCBGA-656 USB2.0 Port 3.3V 24.576MHz/48Mhz Card Reader RTS5137-GR SATA Gen2 page 33 page 32 port port port 3 RJ45 page 30 Page 13~17 +3V_PCH, +1.1VALW, +1.1VS SATA HDD1 Conn page 34 SATA HDD2 Conn page 34 ODD Conn page 34 HDA Codec ALC269Q-VB5-GR page 31 LPC BUS SPI ROM 4MB page 15 LED SPI ROM 128KB (Reserve) ENE KB9012 page 39 page 37 page 37 RTC CKT Touch Pad page 13 Int.KBD page 38 DC/DC Interface CKT.page 39 VGA DC/DC Interface CKT.page 26 Power Circuit 2011/07/29 2012/07/29 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC page 40~50 A Compal Electronics, Inc Compal Secret Data Security Classification Issued Date page 38 B C D Title Block Diagrams Size B Date: Document Number Rev 0.2 QML70 LA-8371P Wednesday, October 19, 2011 Sheet E of 53 DISPLAY DISTRIBUTION CLOCK DISTRIBUTION : LVDS PATH : APU HDMI PATH LVDS CONN A_SODIMM B_SODIMM D D TXOUT[0:2]+/TXCLK+/TZOUT[0:2]+/TZCLK+/I2CC_SCL/DA AMD R ATI VGA 1066~1600MHz MEM_MA_CLK1_P/N MEM_MA_CLK7_P/N 1066~1600MHz MEM_MB_CLK1_P/N MEM_MB_CLK7_P/N Thames XT M2 CLK_PEG_VGA / CLK_PEG_VGA# 100MHz APU_DISP_CLKP/N C AMD 100MHz CPU FS1r2 SOCKET APU_TXOUT[0:2]+/APU_TXOUT_CLK+/APU_TZOUT[0:2]+/APU_TZOUT_CLK+/APU_LVDS_CLK/DATA APU_CLKP/N 100MHz AMD C LVDS_OUT RTD2136S-VE-CG FCH Hudson-M3 Internal CLK GEN DP2_AUX DP_IN GPP_CLK 100MHz 32.768KHz 25MHz LVDS Transtator C DP0_TXP/N[0:1] DP0_AUXP/N B GPP2 GPP1 WLAN Mini PCI Socket B DP0 APU GbE LAN DP1 PCIE_GFX[0:7] C PCIE_GFX[12:15] C VGA PCIE_GFX[0:15] 25MHz FCH LS R A A CRT CONN Compal Secret Data Security Classification 2011/07/29 Issued Date HDMI CONN 2012/07/29 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title CLOCK / DISPLAY DISTRIBUTION Size Document Number Custom QML70 LA-8371P Date: Rev 0.2 Sheet W ednesday, October 19, 2011 of 53 A B C D E Voltage Rails Power Plane Description S4/S5 Deep S3 S1 S3 VIN Adapter power supply (19V) N/A N/A N/A N/A B+ AC or battery power rail for power circuit N/A N/A N/A N/A +APU_CORE Core voltage for CPU ON OFF OFF OFF +APU_CORE_NB Voltage for On-die VGA of APU ON OFF OFF OFF +VGA_CORE 0.95-1.2V switched power rail ON OFF OFF OFF +0.75VS 0.75V switched power rail for DDR terminator ON ON OFF ON +1.0VSG 1.0V switched power rail for VGA ON OFF OFF OFF +1.1VALW 1.1V switched power rail for FCH ON ON ON* OFF +3V_PCH 3.3V switched power rail for FCH ON ON ON* OFF +1.1VS 1.1V switched power rail for FCH ON OFF OFF OFF +1.2VS 1.2V switched power rail for APU ON OFF OFF OFF +3VSG 1.8V switched power rail ON OFF OFF OFF +1.5V 1.5V power rail for CPU VDDIO and DDR ON ON OFF ON +1.5VS 1.5V switched power rail ON OFF OFF OFF +1.8VSG 1.8V switched power rail ON OFF OFF OFF +2.5VS 2.5V for CPU_VDDA ON OFF OFF OFF +3VALW 3.3V always on power rail ON ON ON* ON +LAN_IO 3.3V power rail for LAN ON ON ON ON +3VS 3.3V switched power rail ON OFF OFF OFF +5VALW 5V always on power rail ON ON ON* ON +5VS 5V switched power rail ON OFF OFF OFF +VSB VSB always on power rail ON ON ON* ON +RTCVCC RTC power ON ON ON ON HIGH HIGH ON ON ON ON HIGH ON ON ON LOW S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF BTO Option Table EC SM Bus2 address BOM Structure BTO Item PX@ Use VGA (Mux) X76@ VRAM ID Table AI Use AI Charger nonAI@ Do not use AI Charger CARD@ Use Card Reader IC nonCARD@ not use Card Reader IC X76L01@ Use Hynix GDDR3 1GB VRAM X76L02@ Use Hynix GDDR3 2GB VRAM X76L03@ Use Samsung GDDR3 1GB VRAM X76L04@ Use Samsung GDDR3 2GB VRAM 930@ Use EC KB930 9012@ Use EC KB9012 Board ID Table for AD channel Address HEX Device Address HEX Smart Battery 0001 011X b 16H ADI ADM1032 1001 101X b 9AH AMD Thames XT M2 1000 001X b 82H AMD FS1r2 (APU) 1001 1000 b 98H RTD2132S (TL) 1010 1000 b A8H Vcc Ra / Rc Board ID 3.3V +/- 5% 100K +/- 5% Rb / Rd +/- 5% 8.2K +/- 5% V AD_BID V 0.168 V V AD_BID typ V 0.250 V V AD_BID max 0.155 V 0.362 V FCH SM Bus address Device Address HEX DDR DIMM1 1101 000X b D0 DDR DIMM2 1101 001X b D2 Device Address HEX 2011/07/29 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/07/29 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A Clock HIGH Interrupts Device FCH SM Bus address +VS HIGH EC SM Bus1 address +V HIGH External PCI Devices REQ#/GNT# +VALW S1(Power On Suspend) x = is read cmd, x= is writee cmd IDSEL# SLP_S3# SLP_S4# SLP_S5# Full ON Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF Device SIGNAL STATE B C D Title Notes List Size B Date: Document Number Rev 0.2 QML70 LA-8371P Wednesday, October 19, 2011 Sheet E of 53 AMD APU FS1 BATTERY 12.6V PU101 CHARGER BATT+ PU201 ISL6277HRTZ-T +APU_CORE +CPU_CORE +APU_CORE_NB +CPU_CORE_NB +2.5VS +1.5V D AC ADAPTOR 19V 90W PU501 RT8207MZQW VIN 1.025~1.475VVDD CORE 54A 0.7~1.475V VDDNB 27.5A +2.5VS +2.5VS VDDA 500mA +1.5V +1.5V VDDIO 4.6A +1.2VS +1.2VS VDDR 6.7A PU702 APL5508-25DC D RAM DDRIII SODIMMX2 PU701 TPS51212DSCR B+ +1.2VS +1.5V VDD_MEM 4A +0.75VS VTT_MEM 0.5A +0.75VS +0.75VS PU501 RT8207MZQW PU901 TPS51212DSCR +VGA_CORE +VDDCI +VDDCI PU701 SY8036DBC +1.1VALW PU301 RT8205LZQW +3VALW VGA ATI Whistler/Seymour/Granville +VGA_CORE PU902 APL5912 +1.0VSG U19 AO4430L +1.5VSG 0.85~1.1V VDDC 47A 0.9~1.0V VDDCI 4.6A +1.0VSG DPLL_VDDC: 125 mA SPV10: 120 mA PCIE_VDDC: 2000 mA DP[A:E]_VDD10: 680 mA +1.5VSG VDDR1: 3400 mA +1.0VSG C +INVPWR_B+ PU401 SY8033BDBC U71 SI4178 +5VALW +1.8VSG +1.8VSG +1.8VSG Q7 AO3404AL U69 SI4178 +3VSG +3VSG +3VSG U39 AO4430L +1.1VS +1.1VS +3.3 350mA FAN Control APL5607 C VDDPL_11_DAC: mA VDDAN_11_ML: 226 mA VDDCR_11: 1007 mA VDDAN_11_CLK: 340 mA VDDAN_11_PCIE: 1088 mA VDDAN_11_SATA: 1337 mA +1.1VALW VDDAN_11_USB_S: 140 mA VDDCR_11_USB_S: 197 mA VDDAN_11_SSUSB_S: 282 mA VDDCR_11_SSUSB_S: 424 mA VDDCR_11_S: 187 mA VDDPL_11_SYS: 70 mA +5VS +5VALW U27,U29,U30,U31 +USB_VCCA AP2301MPG +USB_VCCB +3VS +3VS +3VS +1.5VS USB X4 +5V Dual+1 2.5A +3VALW +3VALW +3VALW SATA HDD*2 ODD*1 +5V 3A A2VDD: 130 mA VDDR3: 60 mA +1.1VS +1.1VALW +5VS 500mA Audio Codec ALC269-GR EC ENE KB9012 +5V 45mA +3.3VALW 30mA +3.3VS 3mA +3.3VS 25mA LAN RTL8111F Mini Card +3.3VALW 201mA +1.5VS 500mA +3.3VS 1A +3.3VALW 330mA RTC Bettary A Issued Date VDDIO_33_PCIGP: 131 mA VDDPL_33_SYS: 47 mA VDDPL_33_DAC: 20 mA VDDPL_33_ML: 20 mA VDDAN_33_DAC: 200 mA VDDPL_33_PCIE: 43 mA VDDPL_33_SATA: 93 mA VDDIO_AZ_S: 26 mA VDDPL_33_SSUSB_S: 20 mA VDDPL_33_USB_S: 17 mA VDDAN_33_USB_S: 658 mA VDDIO_33_S: 59 mA VDDXL_33_S: mA VDDAN_33_HWM_S: 12 mA GND VDDIO_33_GBE_S VDDCR_11_GBE_S VDDIO_GBE_S RTC BAT VDDBT_RTC_G 2011/07/29 Deciphered Date 2012/07/29 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A Title POWER DELIVERY CHART Size Document Number Custom QML70 LA-8371P Date: B Compal Secret Data Security Classification 2.4 A FCH AMD Hudson M2/M3 B+ 300mA +3.3V +1.5VSG PLL_PVDD: 75 mA TSVDD: 20 mA AVDD: 70 mA VDD1DI: 100 mA VDD2DI: 50 mA A2VDDQ: 1.5 mA VDD_CT: 110 mA VDDR4: 170 mA PCIE_PVDD: 40 mA MPV18: 150 mA SPV18: 75 mA PCIE_VDDR: 400 mA DP[A:F]_VDD18: 920 mA DP[A:F]_PVDD: 120 mA +3VS LCD panel 17.3" B VRAM 1GB/2GB 64M / 128Mx16 * / +1.5VSG Rev 0.2 Wednesday, October 19, 2011 Sheet of 53 A B C D 18 PCIE_CRX_GTX_P[0 15] PCIE_CTX_GRX_P[0 15] 18 18 PCIE_CRX_GTX_N[0 15] PCIE_CTX_GRX_N[0 15] 18 E JCPU1A WLAN 30 30 33 33 PCIE_DTX_C_CRX_P1 PCIE_DTX_C_CRX_N1 PCIE_DTX_C_CRX_P2 PCIE_DTX_C_CRX_N2 AE5 AE6 AD8 AD7 AC9 AC8 AC5 AC6 P_GPP_RXP0 P_GPP_RXN0 P_GPP_RXP1 P_GPP_RXN1 P_GPP_RXP2 P_GPP_RXN2 P_GPP_RXP3 P_GPP_RXN3 13 13 13 13 13 13 13 13 UMI_MTX_C_CRX_P0 UMI_MTX_C_CRX_N0 UMI_MTX_C_CRX_P1 UMI_MTX_C_CRX_N1 UMI_MTX_C_CRX_P2 UMI_MTX_C_CRX_N2 UMI_MTX_C_CRX_P3 UMI_MTX_C_CRX_N3 AG8 AG9 AG6 AG5 AF7 AF8 AE8 AE9 P_UMI_RXP0 P_UMI_RXN0 P_UMI_RXP1 P_UMI_RXN1 P_UMI_RXP2 P_UMI_RXN2 P_UMI_RXP3 P_UMI_RXN3 +1.2VS R1 P_ZVDDP 196_0402_1% AG11 P_ZVDDP CONN@ GPP LAN P_GFX_RXP0 P_GFX_RXN0 P_GFX_RXP1 P_GFX_RXN1 P_GFX_RXP2 P_GFX_RXN2 P_GFX_RXP3 P_GFX_RXN3 P_GFX_RXP4 P_GFX_RXN4 P_GFX_RXP5 P_GFX_RXN5 P_GFX_RXP6 P_GFX_RXN6 P_GFX_RXP7 P_GFX_RXN7 P_GFX_RXP8 P_GFX_RXN8 P_GFX_RXP9 P_GFX_RXN9 P_GFX_RXP10 P_GFX_RXN10 P_GFX_RXP11 P_GFX_RXN11 P_GFX_RXP12 P_GFX_RXN12 P_GFX_RXP13 P_GFX_RXN13 P_GFX_RXP14 P_GFX_RXN14 P_GFX_RXP15 P_GFX_RXN15 UMI AB8 AB7 AA9 AA8 AA5 AA6 Y8 Y7 W9 W8 W5 W6 V8 V7 U9 U8 U5 U6 T8 T7 R9 R8 R5 R6 P8 P7 N9 N8 N5 N6 M8 M7 GRAPHICS PCI EXPRESS PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7 PCIE_CRX_GTX_P8 PCIE_CRX_GTX_N8 PCIE_CRX_GTX_P9 PCIE_CRX_GTX_N9 PCIE_CRX_GTX_P10 PCIE_CRX_GTX_N10 PCIE_CRX_GTX_P11 PCIE_CRX_GTX_N11 PCIE_CRX_GTX_P12 PCIE_CRX_GTX_N12 PCIE_CRX_GTX_P13 PCIE_CRX_GTX_N13 PCIE_CRX_GTX_P14 PCIE_CRX_GTX_N14 PCIE_CRX_GTX_P15 PCIE_CRX_GTX_N15 P_GFX_TXP0 P_GFX_TXN0 P_GFX_TXP1 P_GFX_TXN1 P_GFX_TXP2 P_GFX_TXN2 P_GFX_TXP3 P_GFX_TXN3 P_GFX_TXP4 P_GFX_TXN4 P_GFX_TXP5 P_GFX_TXN5 P_GFX_TXP6 P_GFX_TXN6 P_GFX_TXP7 P_GFX_TXN7 P_GFX_TXP8 P_GFX_TXN8 P_GFX_TXP9 P_GFX_TXN9 P_GFX_TXP10 P_GFX_TXN10 P_GFX_TXP11 P_GFX_TXN11 P_GFX_TXP12 P_GFX_TXN12 P_GFX_TXP13 P_GFX_TXN13 P_GFX_TXP14 P_GFX_TXN14 P_GFX_TXP15 P_GFX_TXN15 AB2 AB1 AA3 AA2 Y5 Y4 Y2 Y1 W3 W2 V5 V4 V2 V1 U3 U2 T5 T4 T2 T1 R3 R2 P5 P4 P2 P1 N3 N2 M5 M4 M2 M1 PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_N4 PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_N5 PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_N6 PCIE_CTX_C_GRX_P7 PCIE_CTX_C_GRX_N7 PCIE_CTX_C_GRX_P8 PCIE_CTX_C_GRX_N8 PCIE_CTX_C_GRX_P9 PCIE_CTX_C_GRX_N9 PCIE_CTX_C_GRX_P10 PCIE_CTX_C_GRX_N10 PCIE_CTX_C_GRX_P11 PCIE_CTX_C_GRX_N11 PCIE_CTX_C_GRX_P12 PCIE_CTX_C_GRX_N12 PCIE_CTX_C_GRX_P13 PCIE_CTX_C_GRX_N13 PCIE_CTX_C_GRX_P14 PCIE_CTX_C_GRX_N14 PCIE_CTX_C_GRX_P15 PCIE_CTX_C_GRX_N15 P_GPP_TXP0 P_GPP_TXN0 P_GPP_TXP1 P_GPP_TXN1 P_GPP_TXP2 P_GPP_TXN2 P_GPP_TXP3 P_GPP_TXN3 AD5 AD4 AD2 AD1 AC3 AC2 AB5 AB4 P_UMI_TXP0 P_UMI_TXN0 P_UMI_TXP1 P_UMI_TXN1 P_UMI_TXP2 P_UMI_TXN2 P_UMI_TXP3 P_UMI_TXN3 AG2 AG3 AF4 AF5 AF1 AF2 AE2 AE3 P_ZVSS PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K PCIE_CTX_DRX_P1 PCIE_CTX_DRX_N1 PCIE_CTX_DRX_P2 PCIE_CTX_DRX_N2 C35 C36 C71 C72 1 1 2 2 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K UMI_CTX_MRX_P0 UMI_CTX_MRX_N0 UMI_CTX_MRX_P1 UMI_CTX_MRX_N1 UMI_CTX_MRX_P2 UMI_CTX_MRX_N2 UMI_CTX_MRX_P3 UMI_CTX_MRX_N3 C37 C38 C39 C40 C41 C42 C43 C44 1 1 1 1 2 2 2 2 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K AH11 P_ZVSS R2 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 PCIE_CTX_GRX_P0 PCIE_CTX_GRX_N0 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_P8 PCIE_CTX_GRX_N8 PCIE_CTX_GRX_P9 PCIE_CTX_GRX_N9 PCIE_CTX_GRX_P10 PCIE_CTX_GRX_N10 PCIE_CTX_GRX_P11 PCIE_CTX_GRX_N11 PCIE_CTX_GRX_P12 PCIE_CTX_GRX_N12 PCIE_CTX_GRX_P13 PCIE_CTX_GRX_N13 PCIE_CTX_GRX_P14 PCIE_CTX_GRX_N14 PCIE_CTX_GRX_P15 PCIE_CTX_GRX_N15 PCIE_CTX_C_DRX_P1 PCIE_CTX_C_DRX_N1 PCIE_CTX_C_DRX_P2 PCIE_CTX_C_DRX_N2 30 30 33 33 UMI_CTX_C_MRX_P0 UMI_CTX_C_MRX_N0 UMI_CTX_C_MRX_P1 UMI_CTX_C_MRX_N1 UMI_CTX_C_MRX_P2 UMI_CTX_C_MRX_N2 UMI_CTX_C_MRX_P3 UMI_CTX_C_MRX_N3 LAN WLAN 13 13 13 13 13 13 13 13 196_0402_1% LOTES_ACA-ZIF-109-P12-A_FS1R2 3 Power Sequence of APU +1.5V +2.5VS Group A +1.5VS +CPU_CORE Group B +CPU_CORE_NB 4 +1.2VS 2011/07/29 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/07/29 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title FS1r2 PCIE/UMI Size Document Number Custom Date: Rev 0.2 QML70 LA-8371P Wednesday, October 19, 2011 Sheet E of 53 A B C D E 1 JCPU1B 11 11 11 11 DDRA_SMA0 U20 DDRA_SMA1 R20 DDRA_SMA2 R21 DDRA_SMA3 P22 DDRA_SMA4 P21 DDRA_SMA5 N24 DDRA_SMA6 N23 DDRA_SMA7 N20 DDRA_SMA8 N21 DDRA_SMA9 M21 DDRA_SMA10 U23 DDRA_SMA11 M22 DDRA_SMA12 L24 DDRA_SMA13 AA25 DDRA_SMA14 L21 DDRA_SMA15 L20 DDRA_SBS0# DDRA_SBS1# DDRA_SBS2# DDRA_SBS0# DDRA_SBS1# DDRA_SBS2# DDRA_SDM[7 0] DDRA_SDM0 DDRA_SDM1 DDRA_SDM2 DDRA_SDM3 DDRA_SDM4 DDRA_SDM5 DDRA_SDM6 DDRA_SDM7 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 DDRA_SDQS0 DDRA_SDQS0# DDRA_SDQS1 DDRA_SDQS1# DDRA_SDQS2 DDRA_SDQS2# DDRA_SDQS3 DDRA_SDQS3# DDRA_SDQS4 DDRA_SDQS4# DDRA_SDQS5 DDRA_SDQS5# DDRA_SDQS6 DDRA_SDQS6# DDRA_SDQS7 DDRA_SDQS7# 11 11 11 11 DDRA_CLK0 DDRA_CLK0# DDRA_CLK1 DDRA_CLK1# 11 DDRA_ODT0 11 DDRA_ODT1 11 DDRA_SCS0# 11 DDRA_SCS1# 11 DDRA_SRAS# 11 DDRA_SCAS# 11 DDRA_SWE# E14 J17 E21 F25 AD27 AC23 AD19 AC15 DDRA_CLK0 DDRA_CLK0# DDRA_CLK1 DDRA_CLK1# T21 T22 R23 R24 DDRA_CKE0 DDRA_CKE1 H28 H27 DDRA_ODT0 DDRA_ODT1 Y25 AA27 DDRA_SCS0# DDRA_SCS1# V22 AA26 DDRA_SRAS# DDRA_SCAS# DDRA_SWE# V21 W24 W23 MEM_MA_RST# H25 MEM_MA_EVENT# T24 11 MEM_MA_RST# 11 MEM_MA_EVENT# +MEM_VREF +1.5V 15mil U24 U21 L23 DDRA_SDQS0 G14 DDRA_SDQS0# H14 DDRA_SDQS1 G18 DDRA_SDQS1# H18 DDRA_SDQS2 J21 DDRA_SDQS2# H21 DDRA_SDQS3 E27 DDRA_SDQS3# E26 DDRA_SDQS4 AE26 DDRA_SDQS4# AD26 DDRA_SDQS5 AB22 DDRA_SDQS5# AA22 DDRA_SDQS6 AB18 DDRA_SDQS6# AA18 DDRA_SDQS7 AA14 DDRA_SDQS7# AA15 11 DDRA_CKE0 11 DDRA_CKE1 JCPU1C MEMORY CHANNEL A 11 DDRA_SMA[15 0] R3 M_ZVDDIO 39.2_0402_1% MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15 MA_BANK0 MA_BANK1 MA_BANK2 MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7 MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7 MA_CS_L0 MA_CS_L1 MA_RAS_L MA_CAS_L MA_WE_L M_ZVDDIO H17 F17 E19 J19 G16 H16 H19 F19 DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ12 DDRA_SDQ13 DDRA_SDQ14 DDRA_SDQ15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 H20 F21 J23 H23 G20 E20 G22 H22 DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ20 DDRA_SDQ21 DDRA_SDQ22 DDRA_SDQ23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 G24 E25 G27 G26 F23 H24 E28 F27 DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQ26 DDRA_SDQ27 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQ30 DDRA_SDQ31 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63 MA_RESET_L MA_EVENT_L M_VREF MA_DATA8 MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_ODT0 MA_ODT1 W21 DDRA_SDQ0 DDRA_SDQ1 DDRA_SDQ2 DDRA_SDQ3 DDRA_SDQ4 DDRA_SDQ5 DDRA_SDQ6 DDRA_SDQ7 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_CKE0 MA_CKE1 W20 E13 J13 H15 J15 H13 F13 F15 E15 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_CLK_H0 MA_CLK_L0 MA_CLK_H1 MA_CLK_L1 DDRA_SDQ[63 0] MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 11 MEMORY CHANNEL B 12 DDRB_SMA[15 0] 12 12 12 12 AB28 DDRA_SDQ32 AC27 DDRA_SDQ33 AD25 DDRA_SDQ34 AA24 DDRA_SDQ35 AE28 DDRA_SDQ36 AD28 DDRA_SDQ37 AB26 DDRA_SDQ38 AC25 DDRA_SDQ39 Y23 DDRA_SDQ40 AA23 DDRA_SDQ41 Y21 DDRA_SDQ42 AA20 DDRA_SDQ43 AB24 DDRA_SDQ44 AD24 DDRA_SDQ45 AA21 DDRA_SDQ46 AC21 DDRA_SDQ47 DDRB_SBS0# DDRB_SBS1# DDRB_SBS2# DDRB_SDM[7 0] 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 DDRB_SDQS0 DDRB_SDQS0# DDRB_SDQS1 DDRB_SDQS1# DDRB_SDQS2 DDRB_SDQS2# DDRB_SDQS3 DDRB_SDQS3# DDRB_SDQS4 DDRB_SDQS4# DDRB_SDQS5 DDRB_SDQS5# DDRB_SDQS6 DDRB_SDQS6# DDRB_SDQS7 DDRB_SDQS7# 12 12 12 12 DDRB_CLK0 DDRB_CLK0# DDRB_CLK1 DDRB_CLK1# 12 DDRB_ODT0 12 DDRB_ODT1 12 DDRB_SCS0# 12 DDRB_SCS1# 12 DDRB_SRAS# 12 DDRB_SCAS# 12 DDRB_SWE# AA16 DDRA_SDQ56 Y15 DDRA_SDQ57 AA13 DDRA_SDQ58 AC13 DDRA_SDQ59 Y17 DDRA_SDQ60 AB16 DDRA_SDQ61 AB14 DDRA_SDQ62 Y13 DDRA_SDQ63 T27 P24 P25 N27 N26 M28 M27 M24 M25 L26 U26 L27 K27 W26 K25 K24 MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8 MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15 DDRB_SBS0# DDRB_SBS1# DDRB_SBS2# U27 T28 K28 MB_BANK0 MB_BANK1 MB_BANK2 DDRB_SDM0 DDRB_SDM1 DDRB_SDM2 DDRB_SDM3 DDRB_SDM4 DDRB_SDM5 DDRB_SDM6 DDRB_SDM7 D14 A18 A22 C25 AF25 AG22 AH18 AD14 MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7 DDRB_SDQS0 DDRB_SDQS0# DDRB_SDQS1 DDRB_SDQS1# DDRB_SDQS2 DDRB_SDQS2# DDRB_SDQS3 DDRB_SDQS3# DDRB_SDQS4 DDRB_SDQS4# DDRB_SDQS5 DDRB_SDQS5# DDRB_SDQS6 DDRB_SDQS6# DDRB_SDQS7 DDRB_SDQS7# C15 B15 E18 D18 E22 D22 B26 A26 AG24 AG25 AG21 AF21 AG17 AG18 AH14 AG14 MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7 DDRB_CLK0 DDRB_CLK0# DDRB_CLK1 DDRB_CLK1# 12 DDRB_CKE0 12 DDRB_CKE1 AA19 DDRA_SDQ48 AC19 DDRA_SDQ49 AC17 DDRA_SDQ50 AA17 DDRA_SDQ51 AB20 DDRA_SDQ52 Y19 DDRA_SDQ53 AD18 DDRA_SDQ54 AD17 DDRA_SDQ55 DDRB_SMA0 DDRB_SMA1 DDRB_SMA2 DDRB_SMA3 DDRB_SMA4 DDRB_SMA5 DDRB_SMA6 DDRB_SMA7 DDRB_SMA8 DDRB_SMA9 DDRB_SMA10 DDRB_SMA11 DDRB_SMA12 DDRB_SMA13 DDRB_SMA14 DDRB_SMA15 12 MEM_MB_RST# 12 MEM_MB_EVENT# R26 R27 P27 P28 DDRB_CKE0 DDRB_CKE1 J26 J27 DDRB_ODT0 DDRB_ODT1 W27 Y28 DDRB_SCS0# DDRB_SCS1# V25 Y27 DDRB_SRAS# DDRB_SCAS# DDRB_SWE# V24 V27 V28 MEM_MB_RST# J25 MEM_MB_EVENT# T25 MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 A14 B14 D16 E16 B13 C13 B16 A16 DDRB_SDQ0 DDRB_SDQ1 DDRB_SDQ2 DDRB_SDQ3 DDRB_SDQ4 DDRB_SDQ5 DDRB_SDQ6 DDRB_SDQ7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 C17 B18 B20 A20 E17 B17 B19 C19 DDRB_SDQ8 DDRB_SDQ9 DDRB_SDQ10 DDRB_SDQ11 DDRB_SDQ12 DDRB_SDQ13 DDRB_SDQ14 DDRB_SDQ15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 C21 B22 C23 A24 D20 B21 E23 B23 DDRB_SDQ16 DDRB_SDQ17 DDRB_SDQ18 DDRB_SDQ19 DDRB_SDQ20 DDRB_SDQ21 DDRB_SDQ22 DDRB_SDQ23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 E24 B25 B27 D28 B24 D24 D26 C27 DDRB_SDQ24 DDRB_SDQ25 DDRB_SDQ26 DDRB_SDQ27 DDRB_SDQ28 DDRB_SDQ29 DDRB_SDQ30 DDRB_SDQ31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_CLK_H0 MB_CLK_L0 MB_CLK_H1 MB_CLK_L1 MB_CKE0 MB_CKE1 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_ODT0 MB_ODT1 MB_CS_L0 MB_CS_L1 MB_RAS_L MB_CAS_L MB_WE_L MB_RESET_L MB_EVENT_L MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63 DDRB_SDQ[63 0] 12 AG26 DDRB_SDQ32 AH26 DDRB_SDQ33 AF23 DDRB_SDQ34 AG23 DDRB_SDQ35 AG27 DDRB_SDQ36 AF27 DDRB_SDQ37 AH24 DDRB_SDQ38 AE24 DDRB_SDQ39 AE22 DDRB_SDQ40 AH22 DDRB_SDQ41 AE20 DDRB_SDQ42 AH20 DDRB_SDQ43 AD23 DDRB_SDQ44 AD22 DDRB_SDQ45 AD21 DDRB_SDQ46 AD20 DDRB_SDQ47 AF19 DDRB_SDQ48 AE18 DDRB_SDQ49 AE16 DDRB_SDQ50 AH16 DDRB_SDQ51 AG20 DDRB_SDQ52 AG19 DDRB_SDQ53 AF17 DDRB_SDQ54 AD16 DDRB_SDQ55 AG15 DDRB_SDQ56 AD15 DDRB_SDQ57 AG13 DDRB_SDQ58 AD13 DDRB_SDQ59 AG16 DDRB_SDQ60 AF15 DDRB_SDQ61 AE14 DDRB_SDQ62 AF13 DDRB_SDQ63 Place them close to APU within 1" CONN@ CONN@ EVENT# pull high LOTES_ACA-ZIF-109-P12-A_FS1R2 LOTES_ACA-ZIF-109-P12-A_FS1R2 0.75V reference voltage +1.5V +1.5V 4 R4 1K_0402_1% 1K_0402_5% MEM_MA_EVENT# R6 1K_0402_5% MEM_MB_EVENT# 15mil 1 +MEM_VREF R5 R7 1K_0402_1% 2 C45 1000P_0402_50V7K C46 0.1U_0402_16V7K 2011/07/29 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/07/29 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title FS1r2 DDRIII Memory I/F Size Document Number Custom Date: Rev 0.2 QML70 LA-8371P Wednesday, October 19, 2011 Sheet E of 53 A B C D E JCPU1D ANALOG/DISPLAY/MISC DP2_TXP1 DP2_TXN1 K8 K7 J6 J5 13 13 100P_0402_50V8J C597 47 APU_SVT 14 14 APU_SIC APU_SID APU_SIC APU_SID 13 APU_RST# 13 APU_PWRGD EMI request for ESD protection APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ# As close as U2 47 APU_VDD_RUN_FB_L Route as differential with VSS_SENSE DISP_CLKIN_H DISP_CLKIN_L B3 A3 SVC SVD C3 SVT AG12 AH12 SIC SID AF10 AB12 RESET_L PWROK AC10 APU_THERMTRIP# AE12 ALERT_L AF12 13 APU_PROCHOT# CLKIN_H CLKIN_L R541 R542 R543 R544 R545 R546 R547 1 1 1 2 2 2 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% H10 J10 F10 G10 F9 G9 H9 R28 0_0402_5% B4 C5 A4 A5 C4 B5 47 APU_VDDNB_SEN 47 APU_VDD_SEN PROCHOT_L THERMTRIP_L ALERT_L C1 DP_AUX_ZVSS TEST6 TEST9 TEST10 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19 TEST20 TEST24 TEST25_H TEST25_L TEST28_H TEST28_L TEST30_H TEST30_L TEST31 TEST32_H TEST32_L TEST35 AD12 M18 N18 F11 G11 H11 J11 F12 APU_TEST18 G12 APU_TEST19 J12 APU_TEST20 H12 APU_TEST24 AE10 TEST25_H AD10 TEST25_L L10 M10 P19 R19 K22 APU_TEST31 T19 N19 AA12 APU_TEST35 TEST4 TEST5 TDI TDO TCK TMS TRST_L DBRDY DBREQ_L VSS_SENSE VDDP_SENSE VDDNB_SENSE VDDIO_SENSE VDD_SENSE VDDR_SENSE C6 DP_ENBKL B6 A6 DP_INT_PWM DP_AUX_ZVSS FS1R2 DMAACTIVE_L RSVD1 RSVD2 RSVD3 RSVD4 +1.5V +3VS R615 R10 1K_0402_5% 1K_0402_5% @ DP_ENBKL 10 R11 10K_0402_5% DP_INT_PWM 10 R13 150_0402_1% T1 T2 T3 T4 T5 T6 T7 T8 Q101 APU_PROCHOT# H_PROCHOT#_EC 37,47 MMBT3904_NL_SOT23-3 +1.5VS R14 R15 R16 R17 R20 R21 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 510_0402_1% 510_0402_1% 1 1 1 2 2 2 R22 39.2_0402_1% R23 R24 R25 1 @ 300_0402_5% 300_0402_5% 10K_0402_5% +1.5V Indicates to the FCH that a thermal trip has occurred Its assertion will cause the FCH to transition the system to S5 immediately THERMTRIP shutdown temperature: 125 degree R614 1K_0402_5% @ +1.2VS R18 1K_0402_5% R19 10K_0402_5% @ APU_THERMTRIP# Q2 H_THERMTRIP# 14 MMBT3904_NL_SOT23-3 @ W10 FS1R2 AC12 +1.5V +3VALW for issue, HDMI no display @ DOS Mode R560 ALLOW_STOP 13 P18 R18 R12 10K_0402_5% C APU_SVC APU_SVD DP2_TXP3 DP2_TXN3 Asserted as an input to force the processor into the HTC-active state +1.5VS HDMI_DET 10 ML_VGA_HPD 10 LVDS_HPD_R 10 E @ 47 47 DP2_TXP2 DP2_TXN2 D3 E3 D7 E7 F7 G7 B @ 100P_0402_50V8J C598 APU_PWRGD AB11 AA11 13 APU_DISP_CLKP 13 APU_DISP_CLKN APU_RST# AE11 AD11 APU_CLKP APU_CLKN LVDS 1 0.1U_0402_16V7K DP2_TXP1 L5 0.1U_0402_16V7K DP2_TXN1 L6 1.8K_0402_5% 1 Place near APU 1.8K_0402_5% C51 C52 DP_BLON DP_DIGON DP_VARY_BL R30 2 B DP2_TXP0 DP2_TXN0 DP1_TXP3 DP1_TXN3 DP5_AUXP DP5_AUXN G5 G6 R40 DP2_AUXN E 0.1U_0402_16V7K DP2_TXP0 L9 0.1U_0402_16V7K DP2_TXN0 L8 F5 F6 DP2_AUXP C 0.1U_0402_16V7K DP1_TXP3 F2 0.1U_0402_16V7K DP1_TXN3 F1 1 DP4_AUXP DP4_AUXN DP0_HPD DP1_HPD DP2_HPD DP3_HPD DP4_HPD DP5_HPD To LVDS Translater 1 C47 C48 To FCH DP1_TXP2 DP1_TXN2 DP2_AUXP_C 27 DP2_AUXN_C 27 1.8K_0402_5% C61 C62 DP1_TXP1 DP1_TXN1 0.1U_0402_16V7K 0.1U_0402_16V7K 1.8K_0402_5% 2 0.1U_0402_16V7K DP1_TXP2 G3 0.1U_0402_16V7K DP1_TXN2 G2 1 E5 E6 ML_VGA_AUXN R9 2 1 To FCH for RGB ML_VGA_AUXP R8 C59 C60 ML_VGA_AUXP_C 15 ML_VGA_AUXN_C 15 2 0.1U_0402_16V7K DP1_TXP1 H2 0.1U_0402_16V7K DP1_TXN1 H1 C49 C50 1 1 D5 DP2_AUXP D6 DP2_AUXN To HDMI 27 DP2_TXP1_C 27 DP2_TXN1_C C57 C58 DP1_TXP0 DP1_TXN0 DP2_AUXP DP2_AUXN HDMI_CLK 29 HDMI_DATA 29 0.1U_0402_16V7K 0.1U_0402_16V7K 27 DP2_TXP0_C 27 DP2_TXN0_C 0.1U_0402_16V7K DP1_TXP0 H5 0.1U_0402_16V7K DP1_TXN0 H4 RSVD 15 ML_VGA_TXP3 15 ML_VGA_TXN3 1 CLK 15 ML_VGA_TXP2 15 ML_VGA_TXN2 C55 C56 DP1_AUXP DP1_AUXN E1 ML_VGA_AUXP C53 E2 ML_VGA_AUXN C54 DP3_AUXP DP3_AUXN SER 15 ML_VGA_TXP1 15 ML_VGA_TXN1 DP0_TXP3 DP0_TXN3 D1 D2 JTAG 15 ML_VGA_TXP0 15 ML_VGA_TXN0 DP0_TXP2 DP0_TXN2 DP0_AUXP DP0_AUXN HDMI_CLKP HDMI_CLKN HDMI_CLKP J3 HDMI_CLKN J2 DISPLAY PORT MISC HDMI_TX0P K2 HDMI_TX0N K1 TEST HDMI_TX0P HDMI_TX0N HDMI DISPLAY PORT 29 29 DP0_TXP1 DP0_TXN1 DISPLAY PORT HDMI_TX1P HDMI_TX1N DP0_TXP0 DP0_TXN0 DISPLAY PORT 29 29 HDMI_TX1P K5 HDMI_TX1N K4 29 29 L3 L2 CTRL HDMI_TX2P HDMI_TX2N HDMI_TX2P HDMI_TX2N 0_0402_5% EC_THERMTRIP# 37 T9 T10 Y10 AA10 Y12 K21 SENSE 29 29 LOTES_ACA-ZIF-109-P12-A_FS1R2 CONN@ 3 CPU TSI interface level shift R37 1 R48 @ @ @ 1K_0402_5% 1K_0402_5% 1K_0402_5% APU_SVT APU_SVC +3VS 31.6K_0402_1% R33 @ 31.6K_0402_1% ALERT_L 1K_0402_5% ALLOW_STOP 1K_0402_5% APU_SIC Q4 EC_SMB_DA R43 D @ 0_0402_5% EC_SMB_DA2 19,27,37 To EC BSH111 1N_SOT23-3 @ 1K_0402_5% R41 1 @ 300_0402_5% APU_RST# R68 @ 300_0402_5% APU_PWRGD G R89 APU_SIC R49 0_0402_5% 10K_0402_5% 11 R47 10K_0402_5% 13 R50 10K_0402_5% 15 Q5 17 EC_SMB_CK R54 D S +1.5VS @ 0_0402_5% R44 APU_SID R608 APU_TRST# APU_SID 0_0402_5% +1.5V JHDT1 R36 1K_0402_5% APU_SVD 1K_0402_5% HDT Debug conn +1.5V S R607 0.1U_0402_16V4Z R34 @ 30K_0402_1% G R45 @ 1 10 11 12 13 14 15 16 17 18 19 20 APU_TCK R31 1K_0402_5% APU_TMS R38 1K_0402_5% APU_TDI R39 1K_0402_5% APU_TDO 10 APU_PWRGD 12 APU_RST# 14 APU_DBRDY APU_DBREQ# R51 300_0402_5% R35 R32 C63 R59 +1.5VS +1.5V BSH111, the Vgs is: = 0.4V Max = 1.3V @ +1.5V EC_SMB_CK2 19,27,37 To EC 19 16 18 R52 0_0402_5% APU_TEST19 20 R55 0_0402_5% APU_TEST18 BSH111 1N_SOT23-3 R53 300_0402_5% APU_RST# R56 R58 300_0402_5% APU_PWRGD R57 1K_0402_5% APU_SIC R46 1K_0402_5% APU_SID R613 1K_0402_5% ALERT_L 1K_0402_5% ALLOW_STOP R582 @ A @ SAMTE_ASP-136446-07-B CONN@ 0_0402_5% 2011/07/29 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/07/29 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B C D Title FS1r2 Display/MISC/HDT Size Document Number Custom Date: Rev 0.2 QML70 LA-8371P Wednesday, October 19, 2011 Sheet E of 53 A Power Name VDD +CPU_CORE 60A VDDNB +CPU_CORE_NB 29A VDDIO +1.5V C D E JCPU1F VDDNB_13 VDDNB_14 VDDNB_15 VDDNB_16 VDDNB_17 VDDNB_18 VDDNB_19 VDDNB_20 VDDNB_21 VDDNB_22 VDDNB_23 +APU_CORE_NB K13 K12 +APU_CORE_NB_CAP T23 T26 U22 U25 U28 Y26 T20 R28 R25 R22 V20 V23 V26 W22 W25 W28 Y24 G28 +1.5V 2 C64 22U_0603_6.3V6K 4.7U_0402_6.3V6M A Demo Board Capacitor +VDDA_APU C69 10U_0603_6.3V6K C68 10U_0603_6.3V6K C65 10U_0603_6.3V6K 0.22U_0402_6.3V6K C67 10U_0603_6.3V6K 2 VDDR decoupling C358 0.22U_0402_6.3V6K C111 LOTES_ACA-ZIF-109-P12-A_FS1R2 CONN@ 1000P_0402_50V7K VDDA C109 C66 10U_0603_6.3V6K +1.2VS 180P_0402_50V8J C70 10U_0603_6.3V6K 1 40mil C114 0.22U_0402_6.3V6K C113 3300P_0402_50V7K C112 22U_0603_6.3V6M C108 22U_0603_6.3V6M C107 L1 FBMA-L11-201209-221LMA30T_0805 1 180P_0402_50V8J C94 0.22U_0402_6.3V6K C93 0.22U_0402_6.3V6K C92 0.22U_0402_6.3V6K C91 0.22U_0402_6.3V6K C90 0.22U_0402_6.3V6K C89 0.22U_0402_6.3V6K +APU_CORE_NB_CAP 180P_0402_50V8J C99 180P_0402_50V8J C98 1 C88 C87 4.7U_0603_6.3V6K C86 4.7U_0603_6.3V6K C85 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K C84 22U_0603_6.3V6M C83 22U_0603_6.3V6M C82 22U_0603_6.3V6M C81 AG10 AH8 AH9 AH10 C105 AB10 VDDR_1 VDDR_2 VDDR_3 VDDR_4 A19 A21 A23 A25 A7 AA4 AA7 AB13 AB15 AB19 AB21 AB23 AB25 AB27 AB9 AC14 AC16 AC18 AC20 AC24 AC26 AC28 AC4 AC7 AD9 AE13 AE15 AE17 M9 N10 N4 N7 R10 R4 T11 T9 U10 U18 U4 U7 V11 AE19 AE23 AE25 AE27 AE4 AE7 AF14 AF16 AF18 AF20 AF22 AF26 AF28 AF9 AG4 AG7 AH13 AH15 AH17 AH19 AH21 P9 C18 D21 W14 P11 C7 E8 K18 W12 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 CONN@ 180P_0402_50V8J VDDP_1 VDDP_2 VDDP_3 VDDP_4 VDDP_5 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 LOTES_ACA-ZIF-109-P12-A_FS1R2 C104 1000P_0402_50V7K C359 0.22U_0402_6.3V6K C103 0.22U_0402_6.3V6K C102 C101 180P_0402_50V8J C100 180P_0402_50V8J AH6 AH5 AH4 AH3 AH7 2 across VDDIO and VSS split +1.5V 1 0.22U_0402_6.3V6K VDDP decoupling 22U_0603_6.3V6M +1.2VS VDDIO_19 VDDIO_20 VDDIO_21 VDDIO_22 VDDIO_23 VDDIO_24 VDDIO_25 VDDIO_26 VDDIO_27 VDDIO_28 VDDIO_29 VDDIO_30 VDDIO_31 VDDIO_32 VDDIO_33 VDDIO_34 VDDIO_35 VDDIO_36 C97 VDDIO_1 VDDIO_2 VDDIO_3 VDDIO_4 VDDIO_5 VDDIO_6 VDDIO_7 VDDIO_8 VDDIO_9 VDDIO_10 VDDIO_11 VDDIO_12 VDDIO_13 VDDIO_14 VDDIO_15 VDDIO_16 VDDIO_17 VDDIO_18 C80 H26 K20 J28 K23 K26 L22 L25 L28 M20 M23 M26 N22 N25 N28 P20 P23 P26 AA28 +1.5V 0.22U_0402_6.3V6K VDDNB_CAP_1 VDDNB_CAP_2 @ 22U_0603_6.3V6M VDDNB_1 VDDNB_2 VDDNB_3 VDDNB_4 VDDNB_5 VDDNB_6 VDDNB_7 VDDNB_8 VDDNB_9 VDDNB_10 VDDNB_11 VDDNB_12 C11 C12 D9 D8 D12 D11 B11 A12 B10 E12 B9 +1.5V C96 C8 D10 B8 B12 C9 A9 A10 A8 A11 E10 E11 C10 +APU_CORE_NB R11 T10 H8 G1 U11 W11 W13 W15 W17 W19 AB3 AD3 AD6 AE1 L1 Y6 M6 N11 N1 T3 T6 U19 U1 Y16 Y18 Y3 D4 F4 AF6 AF3 L11 C79 +APU_CORE VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55 VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62 0.5A VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 JCPU1E F8 H6 J1 J14 P6 P10 J16 J18 J9 K19 K3 K17 M3 K6 V10 V18 V3 F3 L18 V6 W1 T18 Y14 AA1 AB6 AC1 R1 P3 K10 H3 M19 +APU_CORE 5A / 3.5A VDDA +2.5VS +2.5VS J20 L4 R7 W18 A15 AB17 AC22 AE21 AF24 AH23 AH25 B7 C14 C16 C2 C20 C22 C24 C26 C28 D13 D15 D17 D19 D23 D25 D27 E4 E9 F14 F16 F18 F20 F22 F26 F28 G13 G15 G17 G19 G21 G23 G25 G4 J22 J24 J4 J7 K11 K14 K9 AC11 L19 L7 M11 AF11 V19 V9 W16 W4 W7 Y11 Y20 Y22 Y9 A17 A13 K16 F24 G8 H7 J8 3.2A VDDP / VDDR +1.2VS B Consumption CORE_NB 22uF x 10uF x 0.22uF x 180pF x CORE_NB_CAP 22uF x VDDP 22uF x 10uF x 0.22uF x 180pF x 1nF x VDDR 10uF x 0.22uF x 1nF x 180pF x VDDA 4.7uF x 0.22uF x 3.3nF x 2011/07/29 2012/07/29 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B C Compal Electronics, Inc Compal Secret Data Security Classification Issued Date APU_CORE 22uF x 0.22uF x 0.01uF x 180pF x D Title FS1r2 PWR/GND Size Document Number Custom Date: Rev 0.2 QML70 LA-8371P Wednesday, October 19, 2011 Sheet E of 53 Panel PWM +3VS 1 HPD D R61 47K_0402_5% From FCH 0_0402_5% ML_VGA_HPD Q8 2 2.2K_0402_5% B R65 DP_INT_PWM C E R66 4.7K_0402_5% R626 1 FCH_CRT_HPD D APU_INVT_PWM 27,28 MMBT3904_NL_SOT23-3 15 FCH_CRT_HPD D R62 4.7K_0402_5% 2 CRT HPD S G Q6 2N7002K_SOT23-3 Translator HPD From Translator C 27 LVDS_HPD LVDS_HPD R627 0_0402_5% +1.5VS C Panel ENBKL LVDS_HPD_R DP_ENBKL DP_ENBKL R624 0_0402_5% ENBKL ENBKL 37 @ R630 4.7K_0402_5% HDMI HPD From HDMI Conn APU_HDMI_HPD 29 APU_HDMI_HPD R659 @ R711 0_0402_5% HDMI_DET 100K_0402_5% B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/07/29 2012/07/29 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title FS1r2 Signal Level Shifter Size Document Number Custom Date: Rev 0.2 QML70 LA-8371P Wednesday, October 19, 2011 Sheet 10 of 53 D S SSM3K7002FU_SC70-3 R732 100K_0402_5% D S +5VALW R733 100K_0402_5% SUSP# S Q61 SSM3K7002FU_SC70-3 Q75 G D S 2 R734 10K_0402_5% Q76 G SUSP S SSM3K7002FU_SC70-3 Q77 SUSP 37,44 SUSP 1 D SUSP 2 26,29,33 D G R748 100K_0402_5% R735 470_0603_5% 1 C829 1U_0402_6.3V4Z C828 C827 10U_0603_6.3V6M 37 FCH_3.3PWR_EN 3VS_GATE 47K_0402_5% R767 +VSBP C826 0.1U_0402_16V7K 10U_0603_6.3V6M +3VS FCH_3.3PWR_EN# +3VALW U71 SI4178DY-T1-GE3_SO8 +5VALW C825 0.1U_0603_25V7K R718 100K_0402_5% +3VALW TO +3VS (3A) SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 Q72 G SYSON R729 10K_0402_5% 37,44 SSM3K7002FU_SC70-3 VLDT_EN# SSM3K7002FU_SC70-3 S Q74 G Q71 G SYSON# VLDT_EN# S 37,46 VLDT_EN D 1.1VS_GATE 47K_0402_5% D R725 100K_0402_5% C824 0.1U_0603_25V7K R731 +VSBP Q69 G 1 3 4 Q73 G S SSM3K7002FU_SC70-3 D VLDT_EN# R728 470_0603_5% S SUSP 2 C823 SUSP C822 Q70 G 1 1U_0402_6.3V4Z R727 1K_0402_5% R766 100K_0402_5% 10U_0603_6.3V6M D 5VS_GATE 47K_0402_5% R730 +1.1VS C821 R726 470_0603_5% 10U_0603_6.3V6M C818 1U_0402_6.3V4Z 1 +VSBP +5VALW +1.1VALW +5VALW U70 AO4430L_SO8 C817 C820 E +1.1VALW TO +1.1VS (4A) +5VS 10U_0805_10V4Z 0.1U_0402_16V7K C819 10U_0805_10V4Z U69 SI4178DY-T1-GE3_SO8 +5VALW D +5VALW TO +5VS (5.35A) C SSM3K7002FU_SC70-3 B A D G S SSM3K7002FU_SC70-3 Instant On +3VALW TO +3V_FCH (1A) +3VALW C830 0.1U_0603_25V7K +3V_FCH R737 @ 0_0805_5% Q79 AO3404AL_SOT23 D 10mil R743 D S SSM3K7002FU_SC70-3 3 Q84 FCH_3.3PWR_EN# G SSM3K7002FU_SC70-3 FCH_3.3PWR_EN# S SUSP S Q82 G 200K_0402_5% 3V_GATE +VSBP D Q81 G S G D R741 470_0603_5% 20mil R769 470_0603_5% 2 C834 1U_0603_10V4Z C833 10U_0805_10V4Z S SSM3K7002FU_SC70-3 C836 0.22U_0603_16V4Z Q83 G PX@ C832 10U_0805_10V4Z R744 47K_0402_5% C831 10U_0603_6.3V6M R739 100K_0402_5% SUSP# +1.5VS AP2301GN-HF_SOT23-3 Q78 40mil D +1.5V +1.5V TO +1.5VS (0.5A) SSM3K7002FU_SC70-3 C837 0.1U_0603_25V7K 2 +1.2VS 1 R745 470_0603_5% D Q85 G VLDT_EN# S SSM3K7002FU_SC70-3 +0.75VS +2.5VS SYSON# G SUSP S S SUSP Q87 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 A B G D 1 D Q86 S G Q51 SSM3K7002FU_SC70-3~D R747 470_0603_5% +DDR_CHG R746 470_0603_5% D R623 22_0603_5%~D 2 +1.5V 4 2011/07/29 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/07/29 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC C D Title DC Interface Size B Date: Document Number Rev 0.11 QML70 LA-8371P Wednesday, October 19, 2011 Sheet E 39 of 53 A B PL1 HCB2012KF-121T50_0805 D PH901 under CPU botten side : CPU thermal protection at 90 degree C Recovery at 50 degree C VIN ADP_I 2 @ PR2 5.62K_0402_1% 1 37 Turbo_V NTC_V 37 @ PR3 @ PC13 1U_0402_16V7K PH1 100K_0402_1%_TSM0B104F4251RZ 13.7K_0402_1% 1 PC5 100P_0402_50V8J PC3 1000P_0402_50V7K PR1 13.7K_0402_1% PJPDC1 Change DC040007T0L to DC040004L00 ( Use DC040001V00 symbol ) 37,41 +3VLP 2 CONN@ ACES_88299-0610 GND GND 6 5 4 3 2 1 PC1 1000P_0402_50V7K ADPIN PC2 100P_0402_50V8J PL2 HCB2012KF-121T50_0805 2 DCIN jack P/N:SP02000N000, need doble confirm P/N with ME C PL3 HCB2012KF-121T50_0805 VMB PL4 HCB2012KF-121T50_0805 PR14 22K_0402_1% 100_0402_1% EC_SMB_CK1 37,41 PR31 100_0402_1% EC_SMB_DA1 37,41 PR29 100K_0402_5% PR30 1K_0402_1% PR28 1VSB_N_003 PR18 0_0402_5% 2VSB_N_002 G SPOK D 37,42 S 2 PQ3 TP0610K-T1-E3_SOT23-3 VSB_N_001 PQ4 SSM3K7002FU_SC70-3 PC10 1U_0402_16V7K 2 PR16 100K_0402_1% @ PD2 PJSOT24CW _SOT323-3 PC8 0.22U_0603_25V7K VL @ +VSBP PC9 0.1U_0603_25V7K B+ PR13 100K_0402_1% PC6 1000P_0402_50V7K PC7 0.01U_0402_25V7K PC128 10U_0805_25V6K PR27 1K_0402_1% BATT+ SUYIN_200275MR009G186ZL 2 EC_SMCA EC_SMDA TS_A PD1 PJSOT24CW_SOT323-3 GND GND 10 11 @ PJP2 +3VALW BATT_TEMPA 37 PJ3 +CHGRTC 1 +3VLP JUMP_43X39 VIN @ PD3 RLS4148_LL34-2 + PR20 68_1206_5% 1 PC11 0.22U_0603_25V7K 51_ON# 2 36 22K_0402_1% Must close PBJ1 SP07000H700 VS_N_002 Compal Secret Data Security Classification Issued Date For KB9012 > Remove all 51_ON# circuit A +RTCBATT Change RTC For Cost Down @ PR24 + LOTES_AAA-BAT-054-K01 CONN@ PC12 0.1U_0603_25V7K 2 PR23 100K_0402_1% - VS N1 PR19 68_1206_5% PQ5 TP0610K-T1-E3_SOT23-3 PBJ1 1 2 BATT+ RTC Battery VS_N_001 @ PD4 LL4148_LL34-2 2011/07/29 Deciphered Date 2012/07/29 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B C Title Size Compal Electronics, Inc PWR-DCIN / BATT CONN / OTP Document Number Rev 0.2 QML70 LA-8371P Date: W ednesday, October 19, 2011 D Sheet 40 of 53 A B C D for reverse input protection SI1304BDL-T1-E3_SC70-3 PQ106 D G S PR103 2 3M_0402_5% P2 0.01_2512_1% B+ PL102 1UH_FDSD0630-H-1R0M-P3_11A_20% PR101 DH_CHG PR125 0_0402_5% 1 PC109 0.01U_0402_50V7K PC108 2200P_0402_50V7K PC107 10U_0805_25V6K CSON1 CSOP1 1 @ @ PC124 0.1U_0603_16V7K ILIM Remember to change PC124 from SE000006S80 to SE025104K80 (2011-02-22) +3VALW 10 SCL SDA IOUT ACDET PR126 PC106 10U_0805_25V6K 11 BQ24725_BATDRV 10K_0402_1% PC120 10U_0805_25V6K 12 PR102 0.02_1206_1% SRN BATDRV PC122 0.1U_0402_25V6 ACDRV 13 SRP CMSRC @ BQ24725_ACDRV ACOK CHG PC121 0.1U_0402_25V6 DL_CHG GND 14 PC123 PR114 680P_0402_50V7K 4.7_1206_5% 15 16 REGN 17 BTST 18 PL101 2.2UH_ETQP3W2R2WFN_8.5A_20% BQ24725_LX BQ24725_CMSRC PR106 0_0402_5% BATT+ PQ105 AO4468L_SO8 LODRV ACP +3VL @ PR117 2DH_CHG1 PC119 BQ24725RGRR_VQFN20_3P5X3P5 +3VALW PQ104 SIS412DN-T1-GE3_POW ERPAK8-5 PR115 10_0603_1% SRP1 CSOP1 PR116 6.8_0603_5% SRN1 CSON1 BQ24725_ACOK 10K_0402_1% @ BQ24725_REGN2 PR111 0_0603_5% BQ24725_BST PD102 RB751V-40_SOD323-2 2 PC114 0.01U_0402_50V7K PC101 0.1U_0402_25V6 PC102 0.1U_0402_25V6 PC103 10U_0805_25V6K PC104 10U_0805_25V6K PC105 10U_0805_25V6K 2 20 19 HIDRV ACN PHASE PAD VCC PU101 2BQ24725_BATDRV_1 1U_0603_25V6K 21 PR107 4.12K_0603_1% PC116 DH_CHG 1U_0603_25V6K BQ24725_BATDRV 0.047U_0402_25V7K BQ24725_LX BQ24725_VCC BQ24725_ACP 2 PR109 4.12K_0603_1% PC118 BQ24725_ACN PR108 4.12K_0603_1% PC117 0.1U_0603_25V7K PC113 0.1U_0402_25V6 PC111 10U_0805_25V6K 1 @ PD101 BAS40CW_SOT323-3 PR110 10_1206_1% BQ24725_ACDRV_1 PQ103 MDS2659URH_SO8 VIN PC115 0.1U_0402_25V6 PC110 0.1U_0402_25V6 @ PR105 0_0402_5% 2 PC112 2200P_0402_50V7K PQ102 MDS2659URH_SO8 PC130 10U_0805_25V6K P1 PQ101 MDS2659URH_SO8 VIN 1M_0402_5% PC129 10U_0805_25V6K 1 PR104 PR119 ILIM and external DPM 3.97A PC125 0.01U_0402_25V7K PR121 100K_0402_1% 2 210K_0402_1% EC_SMB_CK1 37,40 PC127 100_0402_5% 2 Max Typ 17.23V 17.63V H >L L > H PC126 0.1U_0402_25V6 Vin Dectector Min 2 PR120 255K_0402_1% 1 BQ24725_ACDET 10K_0402_1% PR124 VIN PR122 154K_0402_1% PR118 PR123 66.5K_0402_1% 19,37 ACIN BQ24725_ILIM EC_SMB_DA1 37,40 ADP_I 37,40 100P_0402_50V8J Please locate the RC Near EC chip 2011-02-22 4 Compal Secret Data Security Classification Issued Date 2011/07/29 Deciphered Date 2012/07/29 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title Compal Electronics, Inc PWR-CHARGER Size Document Number Rev 0.2 QML70 LA-8371P Date: W ednesday, October 19, 2011 D Sheet 41 of 53 A B C D E 2VREF_51125 PC308 1U_0603_16V6K 2 PC318 4.7U_0805_10V6K + @ @ +5VALWP 150U_V_6.3VM_R18 1 PC320 1U_0603_10V6K PR315 95.3K_0402_1% @ 1 VL PC305 RT8205LZQW(2)_WQFN24_4X4 PQ304 AO4468L_SO8 PR313 4.7_1206_5% SNUB_5V 37,40 PC317 680P_0402_50V7K 18 17 SPOK FDMC7692S_MLP8-5 LG_5V LX_5V PR323 0_0402_5% 20 19 PL305 2.2UH_ETQP3W2R2WFN_8.5A_20% PQ306 PR314 499K_0402_1% 21 UG_5V NC LGATE1 PC306 10U_0805_25V6K ENTRIP1 FB1 REF LGATE2 VREG5 PHASE1 VIN UGATE1 PHASE2 PR309 PC315 2.2_0402_5% 0.1U_0402_10V7K BST_5V BST1_5V ENTRIP1 TONSEL FB2 UGATE2 PQ305 SIS412DN-T1-GE3_POWERPAK8-5 EN0 22 13 @ BOOT1 16 B++ BOOT2 15 12 + LG_3V 24 23 EN PC316 PR312 680P_0402_50V7K 4.7_1206_5% SNUB_3V PC303 150U_V_6.3VM_R18 11 VO1 PGOOD GND LX_3V B++ PR307 174K_0402_1% VREG3 VO2 14 PL303 4.7UH_ETQP3W4R7WFN_5.5A_20% PC314 0.1U_0402_10V7K PR308 BST1_3V 1 2 BST_3V 2.2_0402_5% UG_3V 10 ENTRIP2 PR318 0_0402_5% 1 +3VALWP P PAD PQ303 SIS412DN-T1-GE3_POWERPAK8-5 25 ENTRIP2 PU301 PC313 10U_0805_6.3V6M PR303 133K_0402_1% PC304 4.7U_0805_25V6-K PC310 2200P_0402_50V7K @ +3VLP PC309 0.1U_0402_25V6 PC322 680P_0603_50V7K 1 PR306 20K_0402_1% FB_5V FB_3V SKIPSEL PL301 HCB2012KF-121T50_0805 PR302 20K_0402_1% B++ B+ PR305 30.9K_0402_1% PC312 2200P_0402_50V7K PR301 13.7K_0402_1% PC311 0.1U_0402_25V6 1 ENTRIP2 D PQ307A SSM6N7002FU_US6 G N_3_5V_001 D ENTRIP1 B++ S PQ307B SSM6N7002FU_US6 G S PC319 0.1U_0603_25V7K 2VREF_51125 +3VLP +3VL PJP302 PAD-OPEN 2x2m PR322 100K_0402_1% PR321 0_0402_5% PJP305 PQ308 DRC5115E0L_SOD323-3 +5VALWP +3VALWP +5VALW (5A,200mils ,Via NO.= 10) +3VALW (4A,120mils ,Via NO.= 8) PAD-OPEN 4x4m PC321 4.7U_0805_25V6-K @ @ PR319 100K_0402_1% PAD-OPEN 4x4m PJP303 N_3_5V_002 2 PR320 42.2K_0402_1% VS VL 36,37 EC_ON 37 MAINPWON PR317 100K_0402_5% 4 For KB930 > Keep PR319, Remove PR322 For KB9012 (Red square) > Remove PR319 Keep PR322 Compal Secret Data Security Classification 2011/07/29 Issued Date 2012/07/29 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Compal Electronics, Inc PWR-3.3VALWP/5VALWP Size Document Number Custom Date: Rev 0.01 QML70 LA-8371P Wednesday, October 19, 2011 Sheet E 42 of 51 D PC402 22U_0805_6.3V6M SY8033BDBC_DFN10_3X3 FB=0.6Volt PR401 20K_0402_1% PC401 22U_0805_6.3V6M +1.8VSP PC404 22P_0402_50V8J TP NC FB EN SVIN PL401 1UH_FMJ-0630T-1R0 HF_11A_20% 11 @ PD401 C FB_1.8V ISS355_SOD323-2 2 20,26,49 VGA_PWR_ON 200K_0402_1% EN_1.8V PC405 0.1U_0402_10V7K PR404 PR405 1M_0402_5% C LX LX_1.8V PVIN PC406 PR403 680P_0603_50V7K 4.7_1206_5% LX NC PVIN PC403 22U_0805_6.3V6M 10 PU401 +5VALW PG PL402 HCB1608KF-121T30_0603 D PR402 10K_0402_1% B B PJP401 +1.8VSP @ 1 +1.8VSG JUMP_43X118 A A Compal Secret Data Security Classification 2011/07/29 Issued Date Title Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Compal Electronics, Inc +1.8VP Size Document Number Rev 0.01 QML70 LA-8371P Date: Wednesday, October 19, 2011 Sheet 43 of 51 BOOT_1.5V DH_1.5V_1 PR511 0_0402_5% DH_1.5V VDD VTTGND VTTSNS GND VTTREF VDDQ 37,39 SYSON PC517 10U_0805_6.3V6K +1.5VP PR508 0_0402_5% 1.5V_B+ PC511 0.033U_0402_16V7K FB C PR501 10.2K_0402_1% FB_1.5V +1.5VP PR503 887K_0402_1% PR502 10K_0402_1% PC513 1U_0402_16V7K VTTREF_1.5V off on on VTTREF_1.5V +0.75VSP off off on @ EN_1.5V Level L L H @ PC512 680P_0402_50V7K TON_1.5V Mode S5 S3 S0 PC508 10U_0805_6.3V6K 20 VTT 19 18 BOOT 21 +5VALW PC510 1U_0603_10V6K PAD RT8207MZQW _W QFN20_3X3 +5VALW PQ502 FDMC7692S_MLP8-5 17 11 VLDOIN VDDP UGATE CS 12 S3 VDD_1.5V 13 @ PR506 4.7_1206_5% PGND PU501 PR507 5.1_0603_5% 2 PC501 + SNUB_+1.5VP C 330U_D2_2.5VY_R15M 14 S5 PC509 1U_0603_10V6K LGATE TON PR505 20K_0402_1% 2CS_1.5V 15 PGOOD PQ501 SIS412DN-T1-GE3_POW ERPAK8-5 PHASE 16 DL_1.5V PC507 10U_0805_6.3V6K +0.75VSP SW _1.5V PL501 1UH_VMPI0703AR-1R0M-Z01_11A_20% +1.5V 10 PR504 2.2_0402_5% PC506 0.22U_0402_10V6K @ 1 PC503 4.7U_0805_25V6-K PC502 10U_0805_25V6K PC505 2200P_0402_50V7K D BST_1.5V +1.5VP 1.5V_B+ PC504 0.1U_0402_25V6 @ 0.75Volt +/- 5% TDC 0.525A Peak Current 0.75A OCP Current 0.9A PL502 HCB1608KF-121T30_0603 B+ PC516 680P_0603_50V7K D @ PC514 0.1U_0402_10V7K B EN_0.75VSP Note: S3 - sleep ; S5 - power off PJP501 37,39 SUSP# B PR510 0_0402_5% 1 PAD-OPEN 4x4m PJP502 +1.5V (9A,360mils ,Via NO.= 18) +0.75VS (2A,80mils ,Via NO.= 4) +1.5VP PAD-OPEN 4x4m @ PC515 0.1U_0402_10V7K PJP503 +0.75VSP PAD-OPEN 3x3m A A Compal Secret Data Security Classification Issued Date 2011/07/29 Deciphered Date 2012/07/29 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc PWR-1.5VP / +0.75VSP Size Document Number Custom Date: Rev 0.01 QML70 LA-8371P Wednesday, October 19, 2011 Sheet 44 of 51 D D 2 PC806 22U_0805_6.3V6M SNUB_+1.1V +1.1VALWP PC805 22U_0805_6.3V6M LX SS PR804 2 FB_+1.1V PC804 22U_0805_6.3V6M FB PC803 22U_0805_6.3V6M C 8.45K_0402_1% PR805 10K_0402_1% PC808 22P_0402_50V8J PJP801 +1.1VALWP PAD-OPEN 4x4m +1.1VALW PC809 680P_0603_50V7K @ +1.1VALWP LX PL802 0.47UH_FDVE0630-H-R47M=P3_17.7A_20% LX_+1.1V EN 2 SVIN PG @ @ PD801 PR803 ISS355_SOD323-2 LX PC807 0.1U_0402_10V7K EN_1.1V 0_0402_5% C 47K_0402_5% PVIN 11 PR801 37 FCH_1.1PWR_EN SY8036DBC_DFN10_3X3 1 PC802 22U_0805_6.3V6M TP @ PC801 22U_0805_6.3V6M PU801 10 PVIN 1.1V_B+ HCB1608KF-121T30_0603 PR802 4.7_1206_5% PL801 +5VALW +1.1VALWP Iocp=4.94A (6A,240mils ,Via NO.= 12) B B A A Compal Secret Data Security Classification 2011/07/29 Issued Date Title Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Compal Electronics, Inc +1.1VALWP Size Document Number Rev 0.01 QML70 LA-8371P Date: Wednesday, October 19, 2011 Sheet 45 of 51 PL701 HCB1608KF-121T30_0603 PR702 2.2_0603_5% RF +1.2VSP_5V LG_+1.2VSP DRVL V5IN TP 11 TPS51212DSCR_SON10_3X3 PQ702 PC707 1U_0603_6.3V6M PR705 470K_0402_1% 2 @ C PR707 @ PC710 2 1000P_0402_50V7K PL702 1UH_ETQP3W 1R0W FN_11.8A_20% +1.2VSP +5VALW @ PC701 SW _+1.2VSP PC708 330U_D2_2.5VY_R15M RF_+1.2VSP SW SIS412DN-T1-GE3_POW ERPAK8-5 @ PR704 4.7_1206_5% VFB DRVH UG_+1.2VSP 10 @ PC709 1000P_0603_50V7K FB_+1.2VSP BST_+1.2VSP VBST FDMC7692S_MLP8-5 EN 0.1U_0402_16V7K @ TRIP PR701 0_0402_5% VLDT_EN PR710 47K_0402_1% 37,39 PGOOD 1 PR703 TRIP_+1.2VSP 27.4K_0402_1% EN_+1.2VSP D 0.1U_0603_25V7K PR711 0_0402_5% PU701 PC706 B+ PC704 10U_0805_25V6K PQ701 D PC703 2200P_0402_50V7K PC702 0.1U_0402_25V6 +1.2VSP_B+ + C PR706 PJP701 1.2K_0402_1% +1.2VSP 7.15K_0402_1% @ +1.2VS 1 JUMP_43X118 +1.2VSP Iocp=13A PR708 10K_0402_1% B B PU702 APL5508-25DC-TRL_SOT89-3 PC711 1U_0603_10V6K +2.5VSP +2.5VSP 2 +2.5VS @ JUMP_43X39 @ PR709 10K_1206_5% (0.38A,20mils ,Via NO.=1) GND PJP702 OUT IN 2 PC712 4.7U_0805_6.3V6K +3VS A A Compal Secret Data Security Classification 2011/07/29 Issued Date Title Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Compal Electronics, Inc +1.2VSP/+2.5VSP Size Document Number Rev 0.01 QML70 LA-8371P Date: W ednesday, October 19, 2011 Sheet 46 of 51 LGATE PC234 PR249 1 PR257 10_0402_5% PR256 0_0402_5% 0.1U_0603_25V7K PC201 100U_25V_M PC209 100U_25V_M PC218 4.7U_0805_25V6-K PR230 1_0402_1% PJP201 PC230 10U_0805_25V6K PC228 4.7U_0805_25V6-K PQ209 PAD-OPEN 4x4m CPU_B+ VSUM-1 0.36UH_ETQP4LR36WHC_24A_20% PL204 +APU_CORE_NB PR244 3.65K_0402_1% VSUM+_NB PR248 1_0402_1% VSUM-_NB @ PC246 680P_0402_50V7K +APU_CORE 10_0402_5% APU_VDD_SEN Compal Secret Data 2011/07/29 Issued Date Title Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B PR229 3.65K_0402_1% VSUM+ @PR253 @ PR253 32.4K_0402_1% Security Classification APU_VDD_RUN_FB_L PR225 10K_0402_1% ISEN1 PR258 PR255 0_0402_5% PC242 2 1 0.01U_0402_50V7K 820P_0402_50V7K 2 137K_0402_1% 390P_0402_50V7K @ PR252 2K_0402_1% PC245 100_0402_1% @ PC244 1 @ PR254 PR250 2.74K_0402_1% PR224 10K_0402_1% ISEN21 2 @ 1000P_0402_50V7K 301_0402_1% 100P_0402_50V8J PC241 PR251 590_0402_1% PC217 4.7U_0805_25V6-K 1 2 PC240 2 PC208 4.7U_0805_25V6-K 0.22U_0603_25V7K 1U_0603_16V6K FCCM_NB PC235 PR247 0.36UH_ETQP4LR36WHC_24A_20% PL203 +APU_CORE MDV1525URH_PDFN33-8-5 VCC GND PR242 4.7_1206_5% PC238 680P_0603_50V7K PWM +5VS MDU1512RH 1N POWERDFN56-8 BOOT FCCM PR241 2.2_0603_5% PC231 2 MDV1525URH_PDFN33-8-5 PQ205 PWM_Y 14,37 UGATE PHASE 1 49 PU202 10P_0402_50V8J A PR223 PC223 4.7_1206_5% 680P_0603_50V7K PR262 0_0603_5% +3VS 1 PR214 10K_0402_1% ISEN2 NB_B+ PR259 100K_0402_1% +APU_CORE PC227 1U_0603_16V6K ISL6208BCRZ-T_QFN8_2X2 PC237 @ PR216 1_0402_1% 2 UGATE1 2 PHASE1 VGATE 330P_0402_50V8J PC239 0.022U_0402_16V7K PC236 0.22U_0402_10V6K 11K_0402_1% PC243 0.1U_0402_25V6 26 25 LGATE1 PC226 1U_0603_16V6K PWM_Y VSUM- PH204 10K_0402_5%_ERTJ0ER103J PR246 2 2.61K_0402_1% PR245 TP BOOT1 24 PGOOD COMP 23 22 FB 21 20 RTN 28 27 VSUM+ 29 VSUM- LGATE2 PR201 1_0603_5% 2 PC232 PR264 @ 10K_0402_1% PC224 0.22U_0603_50V7K +5VS 30 BOOT1 ISEN2 FB2 UGATE1 VSEN PHASE1 NTC PQ204 37 UGATEX 39 38 LGATEX PHASEX 40 42 43 41 45 IMON +5VS 0_0402_5% @1 PR240 44 LGATE1 470K_0402_5%_TSM0B474J4702RE 47 PWROK PH203 46 VDD 19 12 LGATE2 PWM_Y 18 11 27.4K_0402_1% PHASE2 ENABLE 13 PR238 9.76K_0402_1% 10 SVT ISUMN 2PR237 107K_0402_1% PR239 32 31 VDDP ISUMP 13 APU_PWRGD_L ISL6277HRTZ-T_TQFN48_6X6 VDDIO 17 VR_ON UGATE2 LGATE2 16 APU_SVT 37 BOOT2 33 PHASE2 PC233 0.22U_0402_16V7K 35 34 SVD ISEN1 100K_0402_1% PC225 1000P_0402_50V7K +1.5VS VIN VSUM-1 MDV1525URH_PDFN33-8-5 PC221 0.22U_0603_25V7K PR226 0_0603_5% CPU_B+ 36 BOOT2 VR_HOT_L ISEN1 15 APU_SVD BOOTX UGATE2 ISEN3 PR260 PR220 2.2_0603_5% BOOT2 SVC ISEN2 PR228 0_0402_5% PR231 0_0402_5% PR232 0_0402_5% PR233 0_0402_5% PR234 0_0402_5% PR235 0_0402_5% PR236 0_0402_5% 14 APU_SVC PWM2_NB FCCM_NB 2PR227 107K_0402_1% COMP_NB IMON_NB PGOOD_NB NTC_NB FB_NB VSEN_NB ISEN2_NB ISUMN_NB 48 9.76K_0402_1% PH201 PC222 1000P_0402_50V7K 470K_0402_5%_TSM0B474J4702RE 8,37 H_PROCHOT#_EC +3VS ISEN1_NB +5VS 0.22U_0402_16V7K PR222 27.4K_0402_1% ISUMP_NB PU201 PR221 + PR215 3.65K_0402_1% VSUM+ PR261 0_0603_5% PHASE2 PC207 4.7U_0805_25V6-K PC206 4.7U_0805_25V6-K 2 PR212 4.7_1206_5% PC214 680P_0603_50V7K MDV1525URH_PDFN33-8-5 5 UGATE2 B+ CPU_B+ PQ203 FCCM_NB PR263 10K_0402_1% + PR213 10K_0402_1% ISEN11 PQ208 PR219 41.2K_0402_1% 220P_0402_50V7K 0.36UH_ETQP4LR36WHC_24A_20% PL202 PQ206 @ PC216 1 @ PR218 100_0402_1% MDV1525URH_PDFN33-8-5 VSUM-_NB MDV1525URH_PDFN33-8-5 PQ207 PQ202 PC213 0.1U_0402_25V6 0.047U_0402_16V7K LGATE1 PR217 649_0402_1% 2 PC212 11K_0402_1% 1 PC211 0.22U_0603_25V7K PR211 2 MDU1512RH 1N POWERDFN56-8 VSUM+_NB PC215 0.1U_0402_25V6 MDU1512RH 1N POWERDFN56-8 PR209 2.2_0603_5% BOOT1 330P_0402_50V7K PH202 10K_0402_5%_ERTJ0ER103J PHASE1 100P_0402_50V8J 2.61K_0402_1% PR210 PQ201 UGATE1 @ PR208 32.4K_0402_1% PR243 0_0603_5% PC205 PL201 HCB2012KF-121T50_0805 PL205 HCB2012KF-121T50_0805 CPU_B+ PR204 3.57K_0402_1% +APU_CORE_NB PR206 PC204 10_0402_1% 0_0402_5% 1000P_0402_50V7K 2 PR207 APU_VDDNB_SEN @ PC210 301_0402_1% E PC299 D @PR202 @ PR202 @ PC202 2K_0402_1% 330P_0402_50V7K 1 PR205 PC203 137K_0402_1% 390P_0402_50V7K 2 PR203 C PC219 4.7U_0805_25V6-K B PC229 4.7U_0805_25V6-K A C D Compal Electronics, Inc +CPU_CORE/VDDNBP Size Document Number Custom Date: Rev 0.01 QML70 LA-8371P Wednesday, October 19, 2011 Sheet E 47 of 51 Security Classification Issued Date 2011/07/29 PC933 10U_0603_6.3V6M PC943 1U_0402_6.3V6K PJP902 JUMP_43X79 @ Compal Secret Data Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size A3 Date: W ednesday, October 19, 2011 Sheet 48 PC973 1U_0402_6.3V6K +VGA_CORE PC972 1U_0402_6.3V6K 2 PC967 1U_0402_6.3V6K +VDDC PC936 1U_0402_6.3V6K 2 PC267 330U_D2_2V_Y + PC956 1U_0402_6.3V6K PC266 330U_D2_2V_Y PC968 1U_0402_6.3V6K 1 @ PC260 22U_0805_6.3V6M PC954 1U_0402_6.3V6K 1 PC929 10U_0603_6.3V6M PC942 1U_0402_6.3V6K 2 PC927 10U_0603_6.3V6M PC941 1U_0402_6.3V6K PC284 180P_0402_50V8J PC256 10U_0805_6.3V6K 2 PC928 10U_0603_6.3V6M PC940 1U_0402_6.3V6K PC283 180P_0402_50V8J + PC935 1U_0402_6.3V6K PC953 1U_0402_6.3V6K PC963 1U_0402_6.3V6K PC926 10U_0603_6.3V6M PC969 1U_0402_6.3V6K PC255 22U_0805_6.3V6M 1 PC930 10U_0603_6.3V6M PC952 1U_0402_6.3V6K PC962 1U_0402_6.3V6K PC925 10U_0603_6.3V6M PC938 1U_0402_6.3V6K +VGA_CORE PC254 22U_0805_6.3V6M PC253 22U_0805_6.3V6M @ PC282 180P_0402_50V8J PC276 0.22U_0402_16V7K PC252 22U_0805_6.3V6M PC251 22U_0805_6.3V6M PC250 22U_0805_6.3V6M PC249 22U_0805_6.3V6M +APU_CORE_NB PC939 1U_0402_6.3V6K PC951 1U_0402_6.3V6K PC961 1U_0402_6.3V6K PC924 10U_0603_6.3V6M PC937 1U_0402_6.3V6K @ PC275 0.22U_0402_16V7K PC259 22U_0805_6.3V6M PC262 22U_0805_6.3V6M PC261 22U_0805_6.3V6M +APU_CORE PC922 10U_0603_6.3V6M PC950 1U_0402_6.3V6K PC960 1U_0402_6.3V6K PC923 10U_0603_6.3V6M PC964 1U_0402_6.3V6K PC265 22U_0805_6.3V6M PC264 22U_0805_6.3VAM PC263 22U_0805_6.3V6M PC248 22U_0805_6.3V6M +APU_CORE PC934 1U_0402_6.3V6K PC949 1U_0402_6.3V6K PC959 1U_0402_6.3V6K PC931 10U_0603_6.3V6M PC966 1U_0402_6.3V6K PC281 180P_0402_50V8J PC280 180P_0402_50V8J PC279 0.01U_0402_50V7K PC278 0.01U_0402_50V7K PC258 22U_0805_6.3V6M PC247 22U_0805_6.3V6M PC921 10U_0603_6.3V6M PC948 1U_0402_6.3V6K PC932 10U_0603_6.3V6M PC965 1U_0402_6.3V6K B PC958 1U_0402_6.3V6K 2 PC947 1U_0402_6.3V6K + PC957 1U_0402_6.3V6K 2 PC946 1U_0402_6.3V6K + PC971 1U_0402_6.3V6K 2 PC945 1U_0402_6.3V6K + PC271 330U_D2_2V_Y Local PC955 1U_0402_6.3V6K 2 @ PC944 1U_0402_6.3V6K + PC277 0.01U_0402_50V7K @ PC970 1U_0402_6.3V6K 1 PC270 330U_D2_2V_Y +APU_CORE PC269 330U_D2_2V_Y PC274 0.22U_0402_16V7K PC257 22U_0805_6.3V6M D PC268 330U_D2_2V_Y PC273 0.22U_0402_16V7K +APU_CORE_NB +APU_CORE_NB Local D capacitors under processor on bottom side of board C C +VGA_CORE +VDDCI +VDDCI +VDDCI of B A A Compal Electronics, Inc Document Number PROCESSOR DECOUPLING QML70 LA-8371P 51 Rev 0.01 A B PL901 HCB2012KF-121T50_0805 PC909 2.2U_0603_6.3V6K PR908 470K_0402_1% PR907 4.7_1206_5% + + PR919 SSM3K7002FU_SC70-3 @ GCORE_SEN 22 PR917 5.1K_0402_1% 19 GPU_VID0 @ PR918 10K_0402_5% S GPU_VID0_1 PC913 0.1U_0402_16V7K G PQ906 PR914 10K_0402_1% D @ PR916 10K_0402_5% 100_0402_1% GPU_VID1 + +3VSG +VGA_CORE1 5.1K_0402_1% @ PC912 0.1U_0402_16V7K S 1 2GPU_VID1_1 G SSM3K7002FU_SC70-3 PQ905 FB0_VGA @ PR915 5.1K_0402_1% 19 D @ PR913 10K_0402_1% @ Rtrip = 73.2K, OCP = 34.42A 35.7K_0402_1% PR910 23.7K_0402_1% FB1_VGA1 17.8K_0402_1% PR912 PR909 +3VSG + PC911 680P_0402_50V7K PR911 PC984 330U_D2_2V_Y TPS51212DSCR SON 10P PQ904 1SNUB_VGA PQ903 11 +5VALW MDU1512RH 1N POWERDFN56-8 TP 0_0603_5% RF V5IN_VGA DL_VGA PC920 330U_D2_2V_Y DRVL PC919 330U_D2_2V_Y +VGA_CORE PC910 330U_D2_2V_Y V5IN PR901 VFB PL902 0.36UH_PDME104T-R36MS0R825_37A_20% 2 SW LX_VGA PC974 0.1U_0402_10V7K EN MDV1525URH_PDFN33-8-5 TRIP PR904 PC906 2BST1_VGA 2.2_0603_5% 0.1U_0603_25V7K PR905 0_0603_5% MDU1512RH 1N POWERDFN56-8 DRVH DH_VGA BST_VGA VBST @ FB_VGA 10 PGOOD PC907 0.1U_0402_16V7K 0_0402_5% RF_VGA 20,26 1.5_VDD_PW REN PR9032TRIP_VGA 73.2K_0402_1% EN_VGA 3 PU901 13,20 VGA_PW RGD PQ902 PQ901 PR902 10K_0402_1% PR906 MDV1525URH_PDFN33-8-5 2 PC903 4.7U_0805_25V6-K 10U_0805_25V6K PC902 2 PC905 2200P_0402_50V7K PC904 0.1U_0402_25V6 +3VS D VGA_B+ 10U_0805_25V6K PC901 B+ C Rrf = 470K, FSW = 290KHz +5VALW 3 VGA_PCIE +1.5V PC914 1U_0402_6.3V6K +5VALW GPU_VID0 PR922 1.15K_0402_1% APL5912-KAC-TRL_SO8 PR924 4.53K_0402_1% 1.0V PJP901 +VGA_PCIEP 2 1 +1.0VSG JUMP_43X79 @ Compal Secret Data Security Classification Issued Date 2011/07/29 Deciphered Date 2012/07/29 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A PC916 0.01U_0402_25V7K 22U_0805_6.3V6M PC917 FB VIN Core Voltage Level 0.9V 3K +VGA_PCIEP VOUT VIN VOUT 4.53K GND EN PR923 47K_0402_5% 1 POK Thames 1.1 V PC915 4.7U_0805_6.3V6K 2 PR925 1K_0402_5% PC918 0.1U_0603_25V7K VGA_PW R_ON 20,26,43 VGA_PW R_ON PR921 40.2K_0402_1% 2 RB751V-40_SOD323-2 VCNTL PU902 For Whistler (Thames) 1/2Delta I=4.05A Vtrip=36.5K*10uA=0.365V Iocpmin=0.365V/(8*1.6m)+1/2Delta I=28.51A+4.05A =32.56A 1 PR924 PR920 0_0402_5% @ PD901 1.0V B C Title Compal Electronics, Inc VGA_CORE Size Document Number Rev 0.01 QML70 LA-8371P Date: W ednesday, October 19, 2011 D Sheet 49 of 51 V ersion Change L ist ( P I R L ist ) for Pow er Circuit P age# T itle D ate R equest O w ner Issue D escription Solution D escription Compal Secret Data Security Classification Issued Date 2011/07/29 Deciphered Date 2012/07/29 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc Power PIR Size Document Number Custom Date: Rev 0.2 QML70 LA-8371P Wednesday, October 19, 2011 Sheet 50 of 53 Version change list (P.I.R List) Item Fixed Issue D Rev PG# 0.02 22 0.02 Base on GPU Reference schematic These components are for VGA Date Phase Reserve pull-up / pull-down resistor 100ohm on GCORE_SEN 08/30 SR 15 Modify Netname of SPI signal of U5 08/30 SR 0.02 26 Change Q91.2 from 1.5_VDDC_PWREN# to 1.5VSG_PWREN# 08/30 SR 0.02 26 Change BOM Structure of R349, R350, R354, R355, Q95, Q96 to PX@ 08/30 SR 08/30 SR Base on AMD Comal CRB 0.02 For EMI request 0.02 15 Reserve R559, R561, C624, C625 @ FCH_SDCLK / FCH_SDWP 08/30 SR 0.02 36 Remove USB3.0 Host contorller circuit 09/01 SR 0.02 17 Remove componets of HUDSON_M2 09/01 SR 0.02 19 Modify GPU Straps: GPU_GPIO0 pull-high 09/01 SR 0.02 23 Reserve pull-high and pull-down resistor of MAA14/MBB14 09/01 SR 0.02 21 Modify U7.U13, U7.14 to NC 09/01 SR 19 Add THM_ALERT# to from U7.AG30 (GPU_THERMAL INT) to U34.6 (ADM1032) Add GPU_CTF from U7.AM17 (GPU_CTF) to U72.97 (EC) 09/02 SR Set PCIE FULL TX OUTPUT SWING to High (Full Swing) 10 Base on Thames M2 datasheet 11 B 12 0.02 13 0.02 31 Reserve Analog mircophone circuit 09/02 SR 14 0.02 9, 39,45 Change contorl singal of 1.1VALWP from SPOK to FCH_1.1PWR_EN Change +1.1V_FCH to +1.1VALW 09/02 SR 15 0.02 15,37 Connect U72.92 (EC) to U2.V1 (FCH)for SYS ROM Write Protect 09/02 SR 16 0.02 35 Co-lay AI Charger 09/02 SR 17 0.03 31 Modify Analog Microhpone circut base on Vendor suggestion 09/05 SR 18 0.03 22 Add decoupling cap base on GPU check list 09/06 SR 19 0.03 17 Change decoupling cap base on FCH check list 09/06 SR 20 0.03 27 Change LVDS translator to RTD2136 09/06 SR 21 0.03 28 Add pull-up resistor R129, R132 (2.2K) of FCH_CRT_DDC_SDA / SCL 09/06 SR 13 Change R99 to 22ohm (CLK_SD_48M) 09/07 SR 0.03 22 A Modify List Change pull-up voltage of APU_RST#, APU_PWRGD, APU_SVT, APU_SVC, APU_SVD, ALERT_L, ALLOW_STOP from +1.5V to +1.5VS C Page of for HW Reason for change 1 23 0.03 14 Pull-down PEG_CLKREQ# 09/08 SR 24 0.03 37 Change Board ID, R398: 0ohm 09/08 SR 25 0.03 34 Change Power source of ODD from +5VS to +5VALW 09/09 SR 26 0.03 33 Change Power source of WLAN from +3VALW to +3VS 09/09 SR 27 0.03 32 Add power source for none Card Reader IC solution 09/09 SR Compal Secret Data Security Classification Issued Date 2011/07/29 2012/07/29 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title D C B A Compal Electronics, Inc HW-PIR1 Size Document Number Custom Date: Rev 0.2 QML70 LA-8371P Wednesday, October 19, 2011 Sheet 51 of 53 Version change list (P.I.R List) Item D C Page of for HW Rev PG# Date Phase 0.2 15 Change U5 power from +3V_PCH to +3V_FCH 10/11 SR2 0.2 15 Change GBE_MDIO pull-up voltage from +3VALW to +3V_FCH 10/11 SR2 0.2 25 SWAP QSB7 and QSB#7 10/11 SR2 0.2 32 Delete Net SDCD, SDWP# that connect to EC Add MOSFET inverter of SDWP# 10/11 SR2 0.2 Un-mount pull-high resistor of APU_SVT, APU_SVC, APU_SVD 10/11 SR2 0.2 28 Follow QCL70 pin define 10/11 SR2 0.2 38 Modify Touch Pad pin define 10/11 SR2 Change pull-high voltage of APU_PROCHOT#, APU_THERMTRIP#, APU_SVT, APU_SVC, APU_SVD, ALERT_L, ALLOW_STOP, APU_RST#, APU_PWRGD, APU_SIC, APU_SID 10/11 SR2 Change R299, R300, R309, R310, R319, R320, R325, R326 from 56ohm to 40.2ohm 10/11 SR2 Fixed Issue Reason for change Blue Screen after install VGA Driver For voltage leakage 0.2 Base on AMD recommend 0.2 Modify List 24, 25 10 0.2 37 Change Board ID to "1" for SR2 10/13 SR2 11 0.2 22 Seperate VDDC and VDDCI of VGA 10/14 SR2 12 0.2 23 Reserve R611, R612 for MAA14, MAB14 10/14 SR2 D C 13 14 15 16 17 B B 18 19 20 21 22 23 24 25 A A 26 27 Compal Secret Data Security Classification Issued Date 2011/07/29 2012/07/29 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc HW-PIR2 Size Document Number Custom Date: Rev 0.2 QML70 LA-8371P Wednesday, October 19, 2011 Sheet 52 of 53 www.s-manuals.com ... AC20 AC 22 AC24 AC27 AD18 AD21 AD23 AD26 AF17 AF20 AF 22 AG16 AG18 AG21 AH 22 AH27 AH28 M26 N24 N27 R18 R21 R23 R26 T17 T20 T 22 T24 T27 U16 U18 U21 U23 U26 V17 V20 V 22 V24 V27 Y16 Y18 Y21 Y23 Y26... L 22 L24 L6 M17 M 22 M24 N16 N18 N2 N21 N23 N26 N6 R15 R17 R2 R20 R 22 R24 R27 R6 T11 T13 T16 T18 T21 T23 T26 U15 U17 U2 U20 U 22 U24 U27 U6 V11 V16 V18 V21 V23 V26 W2 W6 Y15 Y17 Y20 Y 22 Y24 Y27... VDDNB_19 VDDNB _20 VDDNB _21 VDDNB _22 VDDNB _23 +APU_CORE_NB K13 K 12 +APU_CORE_NB_CAP T23 T26 U 22 U25 U28 Y26 T20 R28 R25 R 22 V20 V23 V26 W 22 W25 W28 Y24 G28 +1.5V 2 C64 22 U_0603_6.3V6K 4.7U_04 02_ 6.3V6M