A B C D E 1 2 Tang/TangBTO Schematics Document uFCBGA/uFCPGA Coppermine-T or Tualatin 2001-11-16 3 REV: 2.0 4 Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC D CONTAINS AN CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF MPETENT THE CO DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE RMATION INFO CONTAINS MAY BE Size USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OFALCOMP ELECTRONICS,INC Date: A B C D Cover Sheet Document Number Rev ADY11 LA-1181 Friday, November 16, 2001 Sheet E of 41 A B C D E Block Diagram Compal confidential Model Name :ADY11(Tang) File Name : LA-1181 Coppermine-T or Tualatin uFCBGA/uFCPGA CPU CPU Bypass & CPUVID page Thermal Sensor page 4,5 ITP Connector Fan Control HA#(3 31) page page W320-04 page page 14 HD#(0 63) PSB 133MHz CRT Connector Almador-M GMCH-M page 15 DVO Link Memory BUS 3.3V 133MHz SO-DIMM X2 BANK 0, 1, 2, page 12,13 625 BGA VCH Conn VCH Board Clock Generator MAX6654 page 8,9,10 page 15 HUB Link 2 1.8V 66MHz PCI debug port page 27 PCI BUS IDSEL:AD20 (PIRQA/B#,GN T#2,REQ#2) IDSEL:AD17 (PIRQA#,GNT# 3,REQ#3) 3.3V 48MHz 421 BGA 3.3V 24.576MHz USB conn page 30 CardBus Controller LAN 3COM -3C920 AC-LINK MDC 3.3V ATA100 page 25 page 16,17 OZ 6912 page 20 page 21 RJ45 ICH3-M 3.3V 33MHz LPC BUS Slot page 20 IDE Connector (HDD/CR-ROM) 3.3V 33MHz page 22 page 19 Power On/Off Reset & RTC page 30 LPC to X-BUS & Super I/O page 31 page 24 SIO page 27 page 27 Touch Pad page 27 BIOS FDD Int.KBD page 29 page 29 Power Circuit DC/DC page 32,33,34,35,36,37 PIO page 28 EC I/O Buffer page 23 AMP& Phone Jack page 26 EC 87570 DC/DC Interface Suspend page 19 PS/2 conn page 29 page 27 Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I NC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY THEOFCOMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NORINFORMATION THE CONTAINS MAY BE Size USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL OF ELECTRONICS,INC Date: A NS PC87393 X BUS 14M_5V AC97 Codec STAC9700 B C D Block Diagram Document Number Rev ADY11 LA-1181 Friday, November 16, 2001 Sheet E of 41 Note:"@" means all model depop "#" means Tang depop CHIPS Rev CHIPS Rev 3C920-ST06 FW82830MG FW82801CAM SST-Build QB88 QB63 Lot:M28010 DC:C0117 SST2-Build QC34 QB62 QC34 QB62 QC34 QC42 Model Function D M2P3 YES FDD Tang NO PS/2 YES YES Series port NO NO Parallel port YES YES RJ45 YES NO 3Com Lan chipset(3C920) YES NO PT-Build ST-Build C Lot:M28010 DC:C0117 D Lot:M28010 DC:C0117 Lot:M28010 DC:C0117 Note:"@" means all model depop "&" means M2P3 depop "#" means Tang depop C B B A A Compal Electronics, Inc Title Note & Revision Size Document Number Rev ADY11 LA-1181 Date: Friday, November 16, 2001 Sheet of 41 A B C D E 1 HREQ#[0 4] HREQ#[0 4] HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 HADS# +1.5VS R108 1.5K R121 10_0402 R1 L3 T1 U1 L1 T4 AA3 W2 AB3 P3 C14 AF23 AF4 HBPRI# HBNR# HLOCK# A7 C4 C22 AD23 R2 L2 V3 HIT# HITM# HDEFER# AA2 U2 T3 A#3 A#4 A#5 A#6 A#7 A#8 A#9 A#10 A#11 A#12 A#13 A#14 A#15 A#16 A#17 A#18 A#19 A#20 A#21 A#22 A#23 A#24 A#25 A#26 A#27 A#28 A#29 A#30 A#31 A#32 A#33 A#34 A#35 VCC Address Lines Mobile Tualatin REQ#0 REQ#1 REQ#2 REQ#3 REQ#4 RP# ADS# AERR# AP#0 AP#1 BERR# BINIT# IERR# BREQ0# NC NC NC BPRI# BNR# LOCK# HIT# HITM# DEFER# TUALATIN Data Signals Request Signals Error Interface Arbitration Signals Snoop Signals VSS VCC VCC_80 VCC_79 VCC_78 VCC_77 VCC_76 VCC_75 VCC_74 VCC_73 K1 J1 G2 K3 J2 H3 G1 A3 J3 H1 D3 F3 G3 C2 B5 B11 C6 B9 B7 C8 A8 A10 B3 A13 A9 C3 C12 C10 A6 A15 A14 B13 A12 HD#[0 63] D#0 D#1 D#2 D#3 D#4 D#5 D#6 D#7 D#8 D#9 D#10 D#11 D#12 D#13 D#14 D#15 D#16 D#17 D#18 D#19 D#20 D#21 D#22 D#23 D#24 D#25 D#26 D#27 D#28 D#29 D#30 D#31 D#32 D#33 D#34 D#35 D#36 D#37 D#38 D#39 D#40 D#41 D#42 D#43 D#44 D#45 D#46 D#47 D#48 D#49 D#50 D#51 D#52 D#53 D#54 D#55 D#56 D#57 D#58 D#59 D#60 D#61 D#62 D#63 A16 B17 A17 D23 B19 C20 C16 A20 A22 A19 A23 A24 C18 D24 B24 A18 E23 B21 B23 E26 C24 F24 D25 E24 B25 G24 H24 F26 L24 H25 C26 K24 G26 K25 J24 K26 F25 N26 J26 M24 U26 P25 L26 R24 R26 M25 V25 T24 M26 P24 AA26 T26 U24 Y25 W26 V26 AB25 T25 Y24 W24 Y26 AB24 AA24 V24 HD#[0 63] HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63 P6 M6 AC5 AA5 AB6 W5 Y6 U5 HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 VCC_0 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 U5A HA#[3 31] E16 VSS_0 R4 VSS_1 E25 VSS_2 G25 VSS_3 J25 VSS_4 L25 VSS_5 N25 VSS_6 R25 VSS_7 U25 VSS_8 W25 VSS_9 AA25VSS_10 AC25VSS_11 AF25VSS_12 AE26VSS_13 C23 VSS_14 F23 VSS_15 H23 VSS_16 K23 VSS_17 M23 VSS_18 P23 VSS_19 T23 VSS_20 V23 VSS_21 Y23 VSS_22 AB23VSS_23 AE23VSS_24 B22 VSS_25 D21 VSS_26 F21 VSS_27 E22 VSS_28 H21 VSS_29 G22 VSS_30 K21 VSS_31 J22 VSS_32 M21 VSS_33 L22 VSS_34 P21 VSS_35 N22 VSS_36 T21 VSS_37 R22 VSS_38 V21 VSS_39 U22 VSS_40 Y21 VSS_41 W22 VSS_42 AB21VSS_43 AA22VSS_44 AC22VSS_45 AE21VSS_46 B20 VSS_47 D19 VSS_48 AB19VSS_49 AA20VSS_50 AC20VSS_51 AE19VSS_52 B18 VSS_53 D17 VSS_54 F17 VSS_55 E18 VSS_56 AB17VSS_57 HA#[3 31] D22 F22 E21 H22 G21 K22 J21 M22 L21 P22 N21 T22 R21 V22 U21 Y22 W21 AB22 AA21 AC21 D20 F20 E19 AB20 AA19 AC19 D18 F18 E17 AB18 AA17 AC17 D16 F16 E15 AB16 AA15 AC15 D14 F14 E13 AB14 AA13 AC13 D12 F12 E11 AB12 AA11 AC11 D10 F10 E9 AB10 AA9 AC9 D8 F8 E7 AB8 AA7 AC7 D6 F6 E5 H6 G5 K6 J5 N5 T6 V6 +CPU_CORE +CPU_CORE 4 Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I NC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY THEOFCOMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NORINFORMATION THE CONTAINS MAY BE Size USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL OF ELECTRONICS,INC Date: A B C D Mobile Tualatin uFCPGA Document Number Rev ADY11 LA-1181 Friday, November 16, 2001 Sheet E of 41 A B C D E VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 H_RESET# W3 Y1 H_DBSY# H_DRDY# +1.5VS H_THERMDA H_THERMDC H_BSEL0 H_BSEL1 AE12 AF10 AF16 110_1% AD19 AD17 AF20 CLK_CPU_APIC 8P4R_1.5K ITP_TDI ITP_TMS ITP_TRST# ITP_TCK +VTT 1.5K 1 R38 56.2_1% C38 R35 @33_0402 @10PF_0402 ITP_PREQ# ITP_PRDY# AF22 AE20 AD22 AD21 ITP_TCK ITP_TDI ITP_TDO ITP_TMS ITP_TRST# ITP_PREQ# ITP_PRDY# ITP_TCK ITP_TDI ITP_TDO ITP_TMS ITP_TRST# ITP_PREQ# ITP_PRDY# +VS_CMOSREF R136 2 Mobile Tualatin SELFSB0 SELFSB1 EDGECTRLP R34 PICD0 PICD1 THERMDA THERMDC R30 AD10 AD7 AD11 AF7 AF15 AF19 AE22 AF12 AD5 AE16 56.2_1% L5 PM_CPUPERF# APIC RP2# RP3# BPM0# BPM1# Debug Break Point TCK TDI TDO TMS TRST# PREQ# PRDY# R9 1K_0402 +CPU_CORE R15 0_0402 TESTLO1 +VTT_PLL L22 FLM-201209-4R7K C22 33UF_D2_16V CLK_HCLK CLK_HCLK# TESTLO2 CLK_HCLK CLK_HCLK# Test Access PORT VCCT VID TESTHI1 TESTHI2 AD4 A5 D1 AD13 B1 P26 A11 VTT_PWRGD E3 VTTPWRGOOD D26 NC GHI# 14_1% P4 NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 ( ITP ) R134 AF18 AD16 AF11 AE8 N24 AE10 E2 NC NCHCTRLP TESTHI NC NC NC TESTHI CMOSREF_1 CMOSREF_0 RTTIMPDEP +VTT TESTLO2 +VTT AC1 AD1 M1 CLK0 CLK0# TESTLO NC 1K_0402 +VTT PICD0 PICD1 PICCLK Note : GHI# Pull-Up internally If used ITP port mu st depop TESTLO1 +V_AGTLREF Y4 R5 N3 N2 P1 P5 E1 F1 TESTLO VCC PLL1 PLL2 NC NC NC NC Analog R37 150 R36 150 RP6 AF13 AF14 DBSY# DRDY# 1K_0402 R7 + +1.5VS VTT Ref R10 VSS_142 VSS_141 VSS_140 VSS_139 VSS_138 VSS_137 VSS_136 VSS_135 VSS_134 VSS_133 VSS_132 VSS_131 VSS_130 H_INTR H_NMI TESTHI2 AF21 AB26 H26 A21 AF9 A4 N1 AA1 VREF_1 VREF_2 VREF_3 VREF_4 VREF_5 VREF_6 VREF_7 VREF_8 F19 E20 C25 A25 AE1 AD2 AB2 Y2 V2 T2 P2 M2 K2 H_STPCLK# H_DPSLP# H_INTR H_NMI H_INIT# C1 NC AF17NC N4 NC H_PWRGD Data Signals A20M# FERR# FLUSH# IGNNE# SMI# PWRGOOD STPCLK# DPSLP# Compatibility INTR/LINT0 NMI/LINT1 INIT# RESET# B26 VSS M4 VSS AF26VSS H_IGNNE# H_IGNNE# H_SMI# AC3 AF6 AF5 AD9 AD3 AB4 AE4 AF8 AD15 AE14 AE6 B15 AE24 AD25 AE25 AC24 AF24 AD26 AC26 AD24 DEP#0 DEP#1 DEP#2 DEP#3 DEP#4 DEP#5 DEP#6 DEP#7 GND VID0 VID1 VID2 VID3 VID4 H_A20M# H_A20M# H_FERR# Request Signals 2 2 H_TRDY# RS#0 RS#1 RS#2 RSP# TRDY# 1K_0402 +VTT_C Y3 V1 U3 M5 W1 H_RS#0 H_RS#1 H_RS#2 R24 1.5K AB1 AC2 AE2 AF3 R3 R19 3K 1 R18 1.5K A26 VCCT_1 G23 VCCT_2 J23 VCCT_3 L23 VCCT_4 N23 VCCT_5 R23 VCCT_6 U23 VCCT_7 W23 VCCT_8 AA23VCCT_9 C21 VCCT_10 C19 VCCT_11 AD20VCCT_12 C17 VCCT_13 AD18VCCT_14 C15 VCCT_15 C13 VCCT_16 AD14VCCT_17 C11 VCCT_18 AD12VCCT_19 C9 VCCT_20 C7 VCCT_21 AD8 VCCT_22 C5 VCCT_23 AD6 VCCT_24 AC23VCCT_25 AA4 VCCT_26 E4 VCCT_27 G4 VCCT_28 J4 VCCT_29 L4 VCCT_30 AC4 VCCT_31 V4 VCCT_32 AE3 VCCT_33 AF2 VCCT_34 AF1 VCCT_35 AE18VCCT_36 D5 VCCT_37 E6 VCCT_38 R28 56.2_1% Place R_K