A B C D E 1 Compal Confidential 2 ZAWBA/ZAWBB DIS M/B Schematics Document AMD Beema SOC with DDR3L AMD Jet LE 2014-03-03 3 LA-B291P REV： ：1.0 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/03 Deciphered Date 2015/03/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Cover Page Size C Date: A B C D Document Number Rev 1.0 LA-B291P Monday, March 03, 2014 Sheet E of 46 A B C VRAM 1G/2G 256M16 x (2G) 128M16 x (1G) DDR3L D E AMD Beema AMD Jet LE PCIe x Gen2 VRAM 1GB/2GB DDR3L x4 Memory BUS(DDR3L) 204pin DDR3L SO-DIMM X2 Single Channel GFX BANK 0, 1, 1.35V DDRIIIL 1600MHz eDP Conn DP0 HDMI Conn CMOS Camera DP1 AMD FT3b APU CRT Conn GPP0 Card Reader Realtek GPP2 NGFF (WLAN/BT) USB Port 8111G/8106E (reserved) In IO/B Port Port Port Port MB 3.0 Conn LP2 Port USB Right USB 2.0 Conn Touch screen Port MB 3.0 Conn LP1 BGA 769-balls Transformer RJ45 Finger Print Port USB3.0 HDA HD Audio SPI ROM (8MB) SPI Nuvoton NPCE288NB0DX Int.KBD USB2.0 GPP1 LAN 10/100/1G Realtek RTS5229 Port DAC GPP WLAN/BT Combo SATA Gen3 Port Port HDD Conn ODD Conn Audio Realtek ALC233VB LPC Thermal Sensor Touch Pad Int MIC Int Speaker Conn Audio Combo Jacks In IO/B 15" Sub-borad 14" Sub-borad IO/B USB2.0 x Combo Jack Novo button IO/B USB2.0 x Combo Jack Novo button ODD/B LED/B LED/B Battery/B 14" Power/B 2014/03/03 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 15" Power/B 2015/03/03 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Block Diagram Document Number Rev 1.0 LA-B291P Monday, March 03, 2014 Sheet E of 46 A B C Voltage Rails Description S0 S3 S5 VIN Adapter power supply (19V) ON ON ON B+ AC or battery power rail for power circuit ON ON ON Board ID +APU_CORE Core voltage for APU ON OFF OFF +APU_CORE_NB Voltage for On-die VGA of APU ON OFF OFF +VGA_CORE 0.95-1.2V switched power rail ON OFF OFF +VDDCI 0.95-1.2V switched power rail ON OFF OFF +3VALW 3.3V always on power rail ON ON OFF +3VS 3.3V switched power rail ON OFF OFF +1.8VALW 1.8V always on power rail ON ON ON* +1.8VS 1.8V switched power rail ON OFF OFF +0.95VALW 0.95V always on power rail ON OFF OFF +0.95VS 0.95V switched power rail ON OFF OFF +1.35V 1.35V power rail for APU and DDR ON ON OFF Board ID +1.5VS 1.5V switched power rail ON OFF OFF +3VGS 3.3V switched power rail for VGA ON OFF OFF +1.8VGS 1.8V switched power rail for VGA ON OFF OFF +1.35VGS 1.35V switched power rail for VGA ON OFF OFF +0.95VGS 0.95V switched power rail for VGA ON OFF OFF +5VALW 5V always on power rail ON ON ON +5VS 5V switched power rail ON OFF OFF +RTC_APU RTC power ON ON ON +0.675VS 0.675V switched power rail for DDR terminator ON OFF PCB Revision MP PVT DVT EVT 3.3V +/- 5% 100K +/- 5% R1564 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V SOURCE 288N +3VALW VGA BATT KB9012 X V +3VALW X X X X X APU X +3VS X X X V +3VS V +3VS X X X X 288N V X X X X V X V X APU_SCLK0 APU_SDATA0 SMB_EC_CK2 SMB_EC_DA2 +3VS APU +3VS +3VS +3VS HIGH ON ON ON ON HIGH ON ON ON LOW S3 (Suspend to RAM) HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW ON OFF OFF OFF V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V EC SM Bus2 address Device Address HEX Device Address HEX Smart Battery 0001 011X b 16H Thermal Sensor 1001 101X b 9AH SB-TSI (APU) 1001 100X b 98H VGA Internal Thermal USB 2.0 USB 3.0 1000 001X b Card Reader LAN WLAN XHCI Device Address HEX DDR DIMM1 1010 000Xb A0H DDR DIMM2 1010 001Xb A2H Port USB20 port1,2,8,9 External USB Port Touch Screen RIGHT USB Camera WLAN/BT Combo Finger Print LEFT USB3.0 LEFT USB3.0 2014/03/03 2015/03/03 Deciphered Date Date: B C BTO Item for HDMI Logo for 14" componect for 15" componect 15W 2.4GHz BGA APU 15W 1.8GHz BGA APU 15W 1.5GHz BGA APU 10W 1.5GHz BGA APU 10W 1.35GHz BGA APU UMA part Common VGA circuit Jet LE GPU Topaz XT GPU CMOS Camera part HDMI part Realtek RTL8106E with LDO mode Realtek RTL8106E with SWR mode Realtek RTL8111G with LDO mode Realtek RTL8111G with SWR mode Touch Screen Zero Power ODD part Non-Zero Power ODD part USB Charger function Non-USB Charger function Full HD Panel VRAM Dual Rank VRAM Single Rank USB 2.0 USB 3.0 Realtek ALC233-VB Audio IC ME part EMI pop component EMI Un pop component ESD pop component ESD Un pop component EMI Un pop for LAN GIGA function Unpop Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A USB30 port0,1 Compal Electronics, Inc Compal Secret Data Security Classification Issued Date USB Port USB20 port0 BOM Structure 45@ 14@ 15@ B5@ B4@ B3@ B2@ B1@ UMA@ PX@ JET@ TOPAZ@ CMOS@ HDMI@ 8106ELDO@ 8106ESW@ 8111GLDO@ 8111GSW@ TS@ ZODD@ NOZODD@ CHG@ NOCHG@ FHD@ DR@ SR@ USB2@ USB3@ 233VB@ ME@ EMIP@ EMIU@ ESDP@ ESDU@ GIGAEMIP@ @ Device 82H APU SM Bus address BOM Structure Table USB Port Table EC SM Bus1 address Clock HIGH OC# X +VS USB OC MAPPING Port RTD2132 +V HIGH OFF Thermal Sensor FCH +VALW S1(Power On Suspend) APU PCIE PORT LIST WLAN SODIMM WWAN SLP_S3# SLP_S5# Full ON Board ID / SKU ID Table for AD channel Vcc R1562 SIGNAL STATE SMBUS Control Table SMB_EC_CK1 SMB_EC_DA1 E BOARD ID Table Power Plane D D NOTES LIST Document Number Rev 1.0 LA-B291P Monday, March 03, 2014 Sheet E of 46 Jet LE VRAM STRAP X76@ Vendor ZZZ10 1GBytes JM1G@ PS_3[ ] PS_3[ ] PS_3[ ] ID UV5, UV6, UV7, UV8 D Power-Up/Down Sequence X76@ ZZZ09 1GBytes JH1G@ Hynix 2048Mbits SA00006H400 128Mx16 H5TC2G63FFR-11C Micron 2048Mbits SA000067500 128Mx16 MT41J128M16JT-093G:K R_pu RV21 0 0 NC R_pd RV24 4.75K 0 8.45K 2K ZZZ11 1GBytes JS1G@ Samsung 2048Mbits SA000068U40 128Mx16 K4W2G1646Q-BC1A 4.53K 2K ZZZ12 2GBytes JH2G@ Hynix 4096Mbits SA00006E800 256Mx16 H5TC4G63AFR-11C 1 6.98K 4.99K ZZZ13 2GBytes JS2G@ Samsung 4096Mbits SA000076P00 256Mx16 K4W4G1646D-BC1A 0 4.53K 4.99K ZZZ14 2GBytes JM2G@ Micron 4096Mbits SA000077K00 256Mx16 MT41J256M16HA-093G:E 1 3.24K 5.62K 1 3.4K 10K 1 4.75K "Jet" has the following requirements with regards to power-supply sequencing to avoid damaging the ASIC: All the ASIC supplies must reach their respective nominal voltages within 20ms of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred The maximum slew rate on all rails is 50 mV/ s It is recommended that the 3.3-V rail ramp up frist It is recommended that the 0.95-V rail reach at least 90% of its nominal value no later than 2ms from the start of VDDC ramping up The power rails that are shared with other components on the system should be gated for the dGPU so that when dGPU is powered down (for example AMD PowerXpressTM idle state), all the power rails are removed from the dGPU The gate circuits must meet the slew rate requirement (such as 50mV/us) VDDC and VDD_CT should not ramp up simultaneously For example, VDDC should reach 90% before VDD_CT starts to ramp up (or vice versa) For power down, reversing the ramp-up sequence is recommended ‧ ‧‧ ‧ D ≦ ‧ ‧ Micron 4096Mbits ZZZ08 SA000065D00 2GBytes JM2G2@ 256Mx16 MT41K256M16HA-107G:E ZZZ16 1GBytes JM1G2@ Micron 2048Mbits SA00005XB00 128Mx16 MT41K128M16JT-107G:K VDDR3(+3VGS) NC PCIE_VDDC(+0.95VGS) C ZZZ ZZZ ZZZ C ZZZ VDDR1(+1.35VGS) JH1G@ 1G HYNIX X7653638L07 JM1G@ 1G MICRON X7653638L08 JS1G@ 1G SAMSUNG X7653638L09 JH2G@ VDDC/VDDCI(+VGA_CORE) 2G HYNIX X7653638L04 VDD_CT(+1.8VGS) PERSTb REFCLK Straps Reset Straps Valid B B Global ASIC Reset T4+16clock A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/03 Deciphered Date 2015/03/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title VGA Notes List Size C Date: Document Number Rev 1.0 LA-B291P Monday, March 03, 2014 Sheet of 46 A B DDRAB_SDQ[63 0] MEMORY M_ADD0 M_DATA0 M_ADD1 M_DATA1 M_ADD2 M_DATA2 M_ADD3 M_DATA3 M_ADD4 M_DATA4 M_ADD5 M_DATA5 M_ADD6 M_DATA6 M_ADD7 M_DATA7 M_ADD9 M_DATA8 M_ADD10 M_DATA9 M_ADD11 M_DATA10 M_ADD12 M_DATA11 M_ADD13 M_DATA12 M_ADD14 M_DATA13 M_ADD15 M_DATA14 B32 B38 G40 N41 AG40 AN41 AY40 AY34 Y40 M_BANK1 M_DATA16 M_BANK2 M_DATA17 M_DM0 M_DATA19 M_DM1 M_DATA20 M_DM2 M_DATA21 M_DM3 M_DATA22 M_DM4 M_DATA23 M_DM6 M_DATA24 M_DM7 M_DATA25 M_DM8 M_DATA26 M_DQS_H0 M_DATA28 M_DQS_L0 M_DATA29 M_DQS_H1 M_DATA30 M_DQS_L1 M_DATA31 M_DQS_L2 M_DATA32 M_DQS_H3 M_DATA33 M_DQS_L3 M_DATA34 M_DQS_H4 M_DATA35 M_DQS_L4 M_DATA36 M_DQS_H5 M_DATA37 M_DQS_L5 M_DATA38 M_DQS_H6 M_DATA39 M_DQS_H7 M_DATA40 M_DQS_L7 M_DATA41 M_DQS_H8 M_DATA42 M_DQS_L8 M_DATA43 DDRA_CKE0 DDRA_CKE1 DDRB_CKE0 DDRB_CKE1 DDRA_ODT0 DDRA_ODT1 DDRB_ODT0 DDRB_ODT1 DDRA_SCS0# DDRA_SCS1# DDRB_SCS0# DDRB_SCS1# M_CLK_H0 M_DATA45 M_CLK_L0 M_DATA46 M_CLK_H1 M_DATA47 AJ34 AR38 AL38 AN35 M_DATA48 M_CLK_L2 M_DATA49 M_CLK_H3 M_DATA50 M_CLK_L3 M_DATA51 M_RESET_L M_DATA53 M_EVENT_L M_DATA54 AJ37 AL34 AL35 +MEM_VREF +VREF_DQ_APU AD40 AC38 M0_CKE1 M_DATA56 M1_CKE0 M_DATA57 M1_CKE1 M_DATA58 M0_ODT0 M_DATA60 M0_ODT1 M_DATA61 M1_ODT0 M_DATA62 M1_ODT1 M_DATA63 M0_CS_L0 M_CHECK0 M0_CS_L1 M_CHECK1 M1_CS_L0 M_CHECK2 M1_CS_L1 M_CHECK3 M_RAS_L M_CHECK5 M_CAS_L M_CHECK6 M_WE_L M_CHECK7 14@ LAB291P DA60014S000 AM41 AN40 AT41 AU40 AL40 AM40 AR40 AT40 DDRAB_SDQ40 DDRAB_SDQ41 DDRAB_SDQ42 DDRAB_SDQ43 DDRAB_SDQ44 DDRAB_SDQ45 DDRAB_SDQ46 DDRAB_SDQ47 AV41 AW40 BA38 AY37 AU41 AV40 AY39 AY38 DDRAB_SDQ48 DDRAB_SDQ49 DDRAB_SDQ50 DDRAB_SDQ51 DDRAB_SDQ52 DDRAB_SDQ53 DDRAB_SDQ54 DDRAB_SDQ55 BA36 AY35 BA32 AY31 BA37 AY36 BA33 AY32 DDRAB_SDQ56 DDRAB_SDQ57 DDRAB_SDQ58 DDRAB_SDQ59 DDRAB_SDQ60 DDRAB_SDQ61 DDRAB_SDQ62 DDRAB_SDQ63 15@ DA60014S100 AD41 M_ZVDDIO EDP_TXP1 EDP_TXN1 A11 B11 TDP1_TXP2 A12 B12 TDP1_TXP3 TDP1_TXN1 TDP1_TXN2 TDP1_AUXN D17 E17 TDP1_HPD H19 TDP1_AUXP TDP1_TXN3 A4 B4 LTDP0_TXP0 LTDP0_AUXP LTDP0_TXN0 LTDP0_AUXN D15 E15 A5 B5 LTDP0_TXP1 LTDP0_HPD H17 DAC_RED B14 A6 B6 LTDP0_TXP2 LTDP0_TXN2 DAC_GREEN A14 A7 B7 LTDP0_TXP3 R1644 R1645 R1646 APU_SVT APU_SVC APU_SVD R1124 R1127 EC_SMB_CK2 EC_SMB_DA2 DAC_BLUE B15 DAC_HSYNC G19 E19 DISP_CLKIN_H @ @ APU_SVT_R APU_SVC_R APU_SVD_R G31 D27 E29 0_0402_5% 0_0402_5% APU_SIC APU_SID B22 B21 SIC APU_RST# TEMPIN1 B20 A20 APU_RST_L APU_PWRGD TEMPIN2 B19 A19 APU_PWROK A22 B18 PROCHOT_L APU_PWRGD R118 KABINI@ 0_0402_5% 0_0402_5% APU_PROCHOT# R1120 @ H_PROCHOT# APU_ALERT# 1 APU_TDI ESDU@ ESDU@ APU_TDO C186 C175 APU_TCK 100P_0402_50V8J 100P_0402_50V8J 2 APU_TMS HDT APU_TRST# APU_DBRDY APU_DBREQ# D29 D31 D35 D33 G27 B25 A25 D23 G23 E25 E23 APU_VDDNB_SEN APU_VDD_SEN APU_VDD_RUN_FB_L AV33 AU33 ENBKL APU_ENVDD APU_INVT_PWM HDMI_CLK HDMI_DATA HDMI_DET DAC_VSYNC DAC_SDA D19 D21 SVT EDP_HPD DAC_ZVSS A16 DAC_BLU LDT_PWROK ALERT_L TDI TDO CRT CRT_HSYNC CRT_VSYNC CRT_DDC_CLK CRT_DDC_DATA R416 DAC_ZVSS 499_0402_1% +3VS H27 THERMDC H29 DIECRACKMON D25 BP0 A27 BP1 B27 BP2 A26 BP3 B26 PLLTEST1 B28 PLLTEST0 A28 BYPASSCLK_H B24 BYPASSCLK_L A24 PLLCHRZ_H AV35 PLLCHRZ_L AU35 M_TEST E33 LDT_RST_L APU_BP0 APU_BP1 APU_BP2 APU_BP3 APU_PLLTEST1 APU_PLLTEST0 APU_BPCLK_H APU_BPCLK_L Test14 EDP_AUXP EDP_AUXN R255 R256 @ @ 4.7K_0402_5% 4.7K_0402_5% RP23 T39 T40 T41 DAC_BLU DAC_GRN DAC_RED DP_150_ZVSS 150_0804_8P4R_1% TCK TMS A29 FREE_2 TEMPIN0 APU_SCLK APU_CLKINT GIO_TSTDTM0_SERIALCLK H21 TRST_L DBRDY GIO_TSTDTM0_CLKINIT H25 T42 DBREQ_L VDDCR_NB_SENSE USB_ATEST1 VDDCR_CPU_SENSE M_ANALOGIN VDDIO_MEM_S_SENSE M_ANALOGOUT VSS_SENSE TMON_CAL AJ10 AJ8 R32 N32 AP29 HDMI_EN/DP_STEREOSYNCE21 VDD_095_FB_H T45 T43 T44 T46 T47 DP_STEREOSYNC T48 VDD_095_FB_L FT3 REV 0.51 A6@ PU +3VS A6-6400 AM6400ITJ44JBA 2.4G BGA 769P APU_PWRGDC1270 ESDU@ 22P_0402_50V8J +3VS APU_RST# ESDU@ 22P_0402_50V8J C1273 +3VS RP4 APU_ALERT# APU_SID APU_PROCHOT# APU_SIC 1K_0804_8P4R_5% PU +1.8VS +1.8VS RP5 @ PU +1.8VS + PD APU_TRST# RP11 13 15 10K_0804_8P4R_5% 17 19 10 11 12 13 14 15 16 17 18 19 R1080 R1082 R1018 APU_RST# APU_PWRGD APU_BPCLK_L 1K_0804_8P4R_5% 300_0402_5% 300_0402_5% 511_0402_1% +1.8VS JHDT2 2 APU_SVT APU_SVC APU_SVD +1.8VS RP2 20 APU_TCK APU_TMS APU_TDI APU_TDO RP6 APU_TDI APU_TMS APU_TCK APU_DBREQ# APU_SCLK APU_CLKINT APU_SCLK APU_CLKINT 1K_0804_8P4R_5% 10 APU_PWRGD 12 APU_RST# 14 APU_DBRDY 16 APU_DBREQ# 18 APU_PLLTEST0 20 APU_PLLTEST1 +1.8VS RP3 @ 8 1K_0804_8P4R_5% PD RP7 @ APU_BP2 APU_BP3 APU_BP0 APU_BP1 APU_TRST# APU_PLLTEST0 APU_PLLTEST1 1K_0804_8P4R_5% RP8 +1.8VS 1K_0804_8P4R_5% RP11, RP6 will @ when MP R1019 APU_BPCLK_H 511_0402_1% +MEM_VREF C1371 0.1U_0402_16V7K MEM_MAB_EVENT# @ SAMTE_ASP-136446-07-B 1K_0804_8P4R_1% 2 C337 1U_0402_6.3V6K 2014/03/03 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification C1163 0.1U_0402_16V7K 2015/03/03 Deciphered Date Title FT3 DDR3/DISP/MISC//HDT THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A DAC_GRN THERMDA SID DAC_RED SVC SVD EDP_AUXP EDP_AUXN DISP_CLKIN_L 33_0402_5% 33_0402_5% 33_0402_5% R117 KABINI@ 0_0402_5% 2K_0402_1% LTDP0_TXN3 DAC_SCL R400 LTDP0_TXN1 HDT+ UAPU ESDU@ C1195 E1-6050 ZM1332M2J2370 1.35G BGA769P 0.1U_0402_16V7K E1@ ESDP@ TDP1_TXP1 R1113 1K_0402_5% UAPU E2-6200 ZM151103J4470 1.5G BGA 769P E2@ EDP_TXP0 EDP_TXN0 A10 B10 K15 H15 11 DP_150_ZVSS DP_2K_ZVSS +1.35V R1074 39.2_0402_1% A6-6400 AM6400ITJ44JBA 2.4G BGA 769P M_ZVDDIO_MEM_S MEMORY VREF DP2_TXP3 DP2_TXN3 EDP use Lane for FHD +1.35V V41 W40 AB40 AC40 U41 V40 AA41 AB41 UAPU A4-6300 ZM181103J4470 1.8G BGA 769P A4@ LAB291P DP2_TXP2 DP2_TXN2 DP_2K_ZVSS CRT_HSYNC M_VREFDQ A6@ DAX DDRAB_SDQ32 DDRAB_SDQ33 DDRAB_SDQ34 DDRAB_SDQ35 DDRAB_SDQ36 DDRAB_SDQ37 DDRAB_SDQ38 DDRAB_SDQ39 B16 A21 B17 DP_DIGON A17 DP_VARY_BL A18 DP_150_ZVSS TDP1_TXN0 DP_BLON M_VREF FT3 REV 0.51 DAX AF40 AF41 AK40 AK41 AE40 AE41 AJ40 AJ41 DP2_TXP1 DP2_TXN1 UAPUC DISPLAY/SVI2/JTAG/TEST TDP1_TXP0 M0_CKE0 M_CHECK4 DDRAB_SRAS# DDRAB_SCAS# DDRAB_SWE# DDRAB_SDQ24 DDRAB_SDQ25 DDRAB_SDQ26 DDRAB_SDQ27 DDRAB_SDQ28 DDRAB_SDQ29 DDRAB_SDQ30 DDRAB_SDQ31 A9 B9 USB_ATEST0 M_CLK_H2 M_DATA59 AN38 AU38 AN37 AR37 M41 N40 T41 U40 L40 M40 R40 T40 EDP DP2_TXP0 DP2_TXN0 M_CLK_L1 M_DATA55 L34 J38 J37 J34 DDRAB_SDQ16 DDRAB_SDQ17 DDRAB_SDQ18 DDRAB_SDQ19 DDRAB_SDQ20 DDRAB_SDQ21 DDRAB_SDQ22 DDRAB_SDQ23 M_DQS_L6 M_DATA52 G38 MEM_MAB_EVENT# AE34 MEM_MAB_RST# MEM_MAB_EVENT# AC35 AC34 AA34 AA32 AE38 AE37 AA37 AA38 DDRA_CLK0 DDRA_CLK0# DDRA_CLK1 DDRA_CLK1# DDRB_CLK0 DDRB_CLK0# DDRB_CLK1 DDRB_CLK1# F40 F41 K40 K41 E40 E41 J40 J41 M_DQS_H2 M_DATA44 DDRAB_SDQ8 DDRAB_SDQ9 DDRAB_SDQ10 DDRAB_SDQ11 DDRAB_SDQ12 DDRAB_SDQ13 DDRAB_SDQ14 DDRAB_SDQ15 E M_DM5 M_DATA27 B33 A33 B40 A40 H41 H40 P41 P40 AH41 AH40 AP41 AP40 BA40 AY41 AY33 BA34 AA40 Y41 DDRAB_SDQS0 DDRAB_SDQS0# DDRAB_SDQS1 DDRAB_SDQS1# DDRAB_SDQS2 DDRAB_SDQS2# DDRAB_SDQS3 DDRAB_SDQS3# DDRAB_SDQS4 DDRAB_SDQS4# DDRAB_SDQS5 DDRAB_SDQS5# DDRAB_SDQS6 DDRAB_SDQS6# DDRAB_SDQS7 DDRAB_SDQS7# B37 A38 D40 D41 B36 A37 B41 C40 HDMI M_BANK0 M_DATA18 DDRAB_SDM0 DDRAB_SDM1 DDRAB_SDM2 DDRAB_SDM3 DDRAB_SDM4 DDRAB_SDM5 DDRAB_SDM6 DDRAB_SDM7 DDRAB_SDQ0 DDRAB_SDQ1 DDRAB_SDQ2 DDRAB_SDQ3 DDRAB_SDQ4 DDRAB_SDQ5 DDRAB_SDQ6 DDRAB_SDQ7 M_ADD8 M_DATA15 AJ38 AG35 N34 DDRAB_SBS0# DDRAB_SBS1# DDRAB_SBS2# DDRAB_SDM[7 0] B30 A32 B35 A36 B29 A30 A34 B34 D HDMI & LVDS should be reverse in KABINI: APU TX0 to Connector TX2 ; APU TX1 to Connector TX1 APU TX2 to Connector TX0 ; APU TX3 to Connector CLK DDRAB_SMA0 AG38 DDRAB_SMA1 W35 DDRAB_SMA2 W38 DDRAB_SMA3 W34 DDRAB_SMA4 U38 DDRAB_SMA5 U37 DDRAB_SMA6 U34 DDRAB_SMA7 R35 DDRAB_SMA8 R38 DDRAB_SMA9 N38 DDRAB_SMA10 AG34 DDRAB_SMA11 R34 DDRAB_SMA12 N37 DDRAB_SMA13 AN34 DDRAB_SMA14 L38 DDRAB_SMA15 L35 C UAPUA DDRAB_SMA[15 0] B C D Rev 1.0 LA-B291P Monday, March 03, 2014 Sheet E of 46 A B C D UAPUB APU POWER SEQUENCE PCIE Card Reader PCIE_DTX_C_ARX_P0 PCIE_DTX_C_ARX_N0 LAN PCIE_DTX_C_ARX_P1 PCIE_DTX_C_ARX_N1 WLAN R10 R8 P_GPP_RXP0 P_GPP_TXP0 P_GPP_RXN0 P_GPP_TXN0 R5 R4 P_GPP_RXP1 P_GPP_TXP1 P_GPP_RXN1 P_GPP_TXN1 N5 N4 P_GPP_RXP2 P_GPP_TXP2 P_GPP_RXN2 P_GPP_TXN2 N10 N8 P_GPP_RXP3 P_GPP_TXP3 P_GPP_RXN3 P_GPP_TXN3 PCIE_DTX_C_ARX_P2 PCIE_DTX_C_ARX_N2 E L2 L1 PCIE_ATX_DRX_P0 PCIE_ATX_DRX_N0 C1021 C1022 1 2 0.1U_0402_16V7K 0.1U_0402_16V7K K2 K1 PCIE_ATX_DRX_P1 PCIE_ATX_DRX_N1 C1019 C1020 1 2 0.1U_0402_16V7K 0.1U_0402_16V7K J2 J1 PCIE_ATX_DRX_P2 PCIE_ATX_DRX_N2 C1017 C1018 1 2 0.1U_0402_16V7K 0.1U_0402_16V7K PCIE_ATX_C_DRX_P0 PCIE_ATX_C_DRX_N0 Card Reader PCIE_ATX_C_DRX_P1 PCIE_ATX_C_DRX_N1 LAN PCIE_ATX_C_DRX_P2 PCIE_ATX_C_DRX_N2 WLAN +RTC G-A EC_ON +3VALW/+5VALW G-B H2 H1 +1.8VALW 1 +0.95VALW +0.95VS_APU_GFX VGA P_TX_ZVDD_095 R404 1.69K_0402_1% PCIE_GTX_C_ARX_P0 PCIE_GTX_C_ARX_N0 PCIE_GTX_C_ARX_P1 PCIE_GTX_C_ARX_N1 PCIE_GTX_C_ARX_P2 PCIE_GTX_C_ARX_N2 PCIE_GTX_C_ARX_P3 PCIE_GTX_C_ARX_N3 W8 P_RX_ZVDD_095 W7 P_TX_ZVDD_095 L5 L4 P_GFX_RXP0 P_GFX_TXP0 P_GFX_RXN0 P_GFX_TXN0 J5 J4 P_GFX_RXP1 P_GFX_TXP1 P_GFX_RXN1 P_GFX_TXN1 G5 G4 P_GFX_RXP2 P_GFX_TXP2 P_GFX_RXN2 P_GFX_TXN2 D7 E7 P_GFX_RXP3 P_GFX_TXP3 P_GFX_RXN3 P_GFX_TXN3 P_RX_ZVDD_095 R73 1K_0402_1% +0.95VS_APU_GFX G2 G1 PCIE_ATX_GRX_P0 PCIE_ATX_GRX_N0 C1001 PX@ C1002 PX@ 2 0.1U_0402_16V7K 0.1U_0402_16V7K F2 F1 PCIE_ATX_GRX_P1 PCIE_ATX_GRX_N1 C1003 PX@ C1004 PX@ 2 0.1U_0402_16V7K 0.1U_0402_16V7K E2 E1 PCIE_ATX_GRX_P2 PCIE_ATX_GRX_N2 C1005 PX@ C1006 PX@ 2 0.1U_0402_16V7K 0.1U_0402_16V7K D2 D1 PCIE_ATX_GRX_P3 PCIE_ATX_GRX_N3 C1007 PX@ C1008 PX@ 2 0.1U_0402_16V7K 0.1U_0402_16V7K SYSON +1.5V G-C PCIE_ATX_C_GRX_P0 PCIE_ATX_C_GRX_N0 SUSP# +3VS G-D PCIE_ATX_C_GRX_P1 PCIE_ATX_C_GRX_N1 +1.8VS VGA PCIE_ATX_C_GRX_P2 PCIE_ATX_C_GRX_N2 +1.5VS +0.95VS PCIE_ATX_C_GRX_P3 PCIE_ATX_C_GRX_N3 VR_ON +APU_CORE G-E FT3 REV 0.51 A6@ +APU_CORE_NB A6-6400 AM6400ITJ44JBA 2.4G BGA 769P UAPUE 2 CLK/SATA/USB/SPI/LPC SATA_ATX_DRX_P1 SATA_ATX_DRX_N1 SATA_DTX_C_ARX_N1 SATA_DTX_C_ARX_P1 R90 R96 +0.95VS 2 BA16 AY16 SATA_TX0N USB_ZVSS AG4 USB_HSD0P AL4 AL5 SATA_RX0P SATA_TX1N USB_HSD1P AY17 BA17 SATA_RX1N AR19 AP19 SATA_ZVSS BA30 SATA_ACT_L/GPIO67 AY12 SATA_X1 BA12 SATA_X2 SATA_RX1P USB_HSD2P USB_HSD2N SATA_ZVDD_095 USB_HSD3P USB_HSD3N SATALED# SATALED# USB_HSD4P USB_HSD4N USB_HSD5P USB_HSD5N USB_HSD6P USB_HSD6N VGA Card Reader LAN WLAN CLK_PCIE_GPU CLK_PCIE_GPU# CLK_PCIE_CR CLK_PCIE_CR# U4 U5 CLK_PCIE_LAN CLK_PCIE_LAN# CLK_PCIE_WLAN CLK_PCIE_WLAN# GFX_CLKP USB_HSD7P GFX_CLKN USB_HSD7N AC8 AC10 GPP_CLK0P USB_HSD8P GPP_CLK0N USB_HSD8N AE4 AE5 GPP_CLK1P USB_HSD9P GPP_CLK1N USB_HSD9N AC4 AC5 GPP_CLK2P AA5 AA4 GPP_CLK3P USB_SS_0TXP GPP_CLK3N USB_SS_0TXN X14M_25M_48M_OSC USB_SS_0RXP AP13 USB_SS_ZVSS USB_SS_1TXN N1 R1133 R1134 LPC_CLK0_EC LPC_CLK1 @ @ 0_0402_5% 0_0402_5% AY2 AW2 T50 AT2 AT1 AR2 AR1 AP2 AP1 AV29 AP25 AV2 SERIRQ USB20_P1 USB20_N1 Right USB port AG1 AG2 USB20_P3 USB20_N3 CAMERA USB20_P5 USB20_N5 WLAN/BT combo AE1 AE2 48M_X2 AC1 AC2 AB1 AB2 AA1 AA2 AE10 USBSS_ZVSS R644 USBSS_ZVDD R645 T2 T1 Finger Print USB30_P8 USB30_N8 MB USB3.0 port0 USB30_P9 USB30_N9 MB USB3.0 port1 1K_0402_1% 1K_0402_1% V2 V1 SPI_DO/GPIO163 AR11 SPI_DI/GPIO164 AR7 SPI_HOLD_L/GEVENT9_LAU11 SPI_WP_L/GPIO161 AU9 LAD1 LAD2 LAD3 LFRAME_L +0.95VALW USB30_MTX_C_DRX_P1 USB30_MTX_C_DRX_N1 APU_SPI_CLK APU_SPI_CS1# APU_SPI_AOSI APU_SPI_AISO APU_SPI_HOLD# APU_SPI_WP# T51 APU_SPI_AISO APU_SPI_AOSI_U APU_SPI_CLK_U APU_SPI_CS1#_U EC_SPI_AISO EC_SPI_AOSI EC_SPI_CLK EC_SPI_CS1# 0_0804_8P4R_5% R109,R110,R111 close to APU R110 R111 33_0402_5% APU_SPI_CLK_U 33_0402_5% APU_SPI_CS1#_U R109 33_0402_5% APU_SPI_AOSI_U EC_SPI_AISO EC_SPI_AOSI EC_SPI_CLK EC_SPI_CS1# +3VALW RP13 APU_SPI_CS1#_U1 APU_SPI_WP# APU_SPI_HOLD# C794 6P_0402_50V8 C795 6P_0402_50V8 +3VALW 10K_0804_8P4R_5% 8MB SPI ROM U1 APU_SPI_AISO R108 33_0402_5% R108 close to ROM SERIRQ/GPIO48 APU_SPI_CS1#_U APU_SPI_AISO_U APU_SPI_WP# LPC_CLKRUN_L A6@ @ LDRQ0_L LPC_PD_L/GEVENT5_L/SPI_TPM_CS_L Y2 48MHZ_8PF_X3S048000D81H-W RP12 USB30_MRX_DTX_P1 USB30_MRX_DTX_N1 SPI_CS2_L/GPIO166 AR4 48M_X1 USB30_MRX_DTX_P0 USB30_MRX_DTX_N0 R1 R2 AU7 USB30_MTX_C_DRX_P0 USB30_MTX_C_DRX_N0 EMIP@ SPI_CLK/GPIO162 R938 1M_0402_5% USB20_P7 USB20_N7 LPCCLK0 LAD0 48MHz CRYSTAL AD1 AD2 USB_SS_1RXP LPCCLK1 Touch Screen (reserved) AF1 AF2 W1 USB_SS_1RXN W2 X48M_X2 FT3 REV 0.51 AG7 AG8 SPI_CS1_L/GPIO165 AW9 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# USB20_P0 USB20_N0 X48M_X1 USB_SS_1TXP 48M_X2 AJ4 AJ5 AE8 USB_SS_ZVDD_095_USB3_DUAL GPP_CLK2N USB_SS_0RXN N2 48M_X1 11.8K_0402_1% SATA_TX1P USB_HSD1N 1K_0402_1% SATA_ZVSS 1K_0402_1% SATA_ZVDD R641 SATA_RX0N USB_HSD0N AY19 BA19 USB_ZVSS SATA_DTX_C_ARX_N0 SATA_DTX_C_ARX_P0 W4 USBCLK/14M_25M_48M_OSC SATA_TX0P BA14 AY14 ODD SATA_ATX_DRX_P0 SATA_ATX_DRX_N0 HDD APU->EC->ROM must route as Daisy Chain for Share ROM quality (RP12 was request to added for the recoverable solution as original method) /CS DO(IO1) /WP(IO2) GND VCC /HOLD(IO3) CLK DI(IO0) APU_SPI_CLK_U 2 R617 EMIU@ C636 EMIU@ 10_0402_5% 10P_0402_50V8J Compal Electronics, Inc Compal Secret Data 2014/03/03 Issued Date C635 0.1U_0402_16V4Z APU_SPI_HOLD# APU_SPI_CLK_U APU_SPI_AOSI_U W25Q64FVSSIQ_SO8 A6-6400 AM6400ITJ44JBA 2.4G BGA 769P Security Classification 2015/03/03 Deciphered Date Title FT3 PCIE/SATA/CLK/USB/SPI THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 LA-B291P Date: A B C D Monday, March 03, 2014 Sheet E of 46 A B C ACPI/SD/AZ/GPIO/RTC/MISC EC_RSMRST#_R AY4 AY9 LPC_RST_L AY5 RSMRST_L SD_PWR_CTRL PCIE_RST_L SD_CLK/GPIO73 SD_CMD/GPIO74 SD_CD/GPIO75 PBTN_OUT# APU_PCIE_WAKE# BA8 AM19 AY7 AW11 PWR_GOOD_APU SYS_RESET_L APU_PCIE_WAKE# AY3 BA5 SLP_S3# SLP_S5# KBRST# EC_SCI# EC_SMI# SD_WP/GPIO76 TEST0 CS_JTAG_TMS_TEST1 TEST2 AU13 AY10 AY6 AR23 AR31 AN5 AL7 GATEA20 SD_DATA3/GPIO80 BA22 AY21 AY24 BA24 SD_LED/GPIO45 AY25 TEST1/TMS SCL0/GPIO43 TEST2 SDA0/GPIO47 AU25 AV25 SYS_RESET_L/GEVENT19_L SD_DATA0/GPIO77 WAKE_L/GEVENT8_L SD_DATA1/GPIO78 SLP_S3_L KBRST_L SCL1/GPIO227 GA20IN/GEVENT0_L R290 VGA_CLKREQ# 0_0402_5% @ USB_OC0# USB_OC1# ODD_PLUGIN# AY8 AW1 AV1 AY1 T54 HDA_SDIN0 T55 T56 T57 AN2 AN1 AK2 AK1 AM1 AL2 AM2 AL1 HDA_BITCLK HDA_SDOUT HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 HDA_SYNC HDA_RST# SDA1/GPIO228 LPC_SMI_L/GEVENT23_L GPIO49 AC_PRES/IR_RX0/GEVENT16_L GPIO55 IR_TX0/GEVENT21_L GPIO57 IR_TX1/GEVENT6_L GPIO58 IR_RX1/GEVENT20_L GPIO59 IR_LED_L/LLB_L/GPIO184 GPIO64 CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/GPIO60 GPIO68 CLK_REQ1_L/GPIO61 GPIO69 CLK_REQ2_L/GPIO62 GPIO70 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/GPIO63 GPIO71 CLK_REQG_L/GPIO65/OSCIN GPIO174 AJ2 USB_OC1_L/TDI/GEVENT13_L USB_OC2_L/TCK/GEVENT14_L USB_OC3_L/TDO/GEVENT15_L AZ_BITCLK AZ_SDOUT AZ_SDIN0/GPIO167 GENINT1_L/GPIO32 AZ_SDIN3/GPIO170 GENINT2_L/GPIO33 AJ1 BA29 AP23 R2122 @ FANOUT0/GPIO52 BT_OFF# ODD_EN UMA@ 0_0402_5% R661 @ APU_GPIO174 H_PROCHOT# PX5.5 UMA PX@ R912 10K_0402_5% 32.768KMHz CRYSTAL GEVENT2# 32K_X1 ODD_DA#_APU_R BLINK EC_LID_OUT# R292 0_0402_5% @ EC_LID_OUT# DGPU_PWROK ODD_DA#_APU DGPU_PWROK 2 Y1 32.768KHZ_12.5P_1TJF125DP1A000D AV31 AU31 AV11 32K_X2 R914 20M_0402_5% X32K_X1 X32K_X2 R911 10K_0402_5% Board_ID1 Function Board_ID1 PXS_RST# APU_SPKR DGPU_PWR_EN DGPU_PWR_EN AZ_SYNC AZ_RST_L If use as SMBUS : Pulled-up to VDD_33(port0) , VDD_33_ALW(port1) with a resistor of: Qty: 1; Value: 2.2 K ; Tol: 5% If no use : Pulled-up to VDD_33(port0) , VDD_33_ALW(port1) with a resistor of: Qty: 1; Value: 10 K ; Tol: 5% USE Board_ID1 0_0402_5% AZ_SDIN1/GPIO168 AZ_SDIN2/GPIO169 APU_PCIE_RST# +3VS APU_SCLK0 APU_SDATA0 APU_SCLK1 APU_SDATA1NO AP27 AY28 BA28 AV23 AP21 BA26 AV19 AY27 BA27 AU21 AY26 AV21 AM21 BA3 GEVENT2_L RTCCLK 32K_X2 APU_SCLK0 APU_SDATA0 AY11 BA11 AV17 GEVENT4_L BA4 GEVENT7_L AR15 GEVENT10_L AP17 GEVENT11_L AP11 GEVENT17_L AN8 BLINK/GEVENT18_L AU17 GEVENT22_L BA6 USB_OC0_L/SPI_TPM_CS_L/TRST_L/GEVENT12_L FANIN0/GPIO56 32K_X1 C912 150P_0402_50V8J LPC_PME_L/GEVENT3_L SPKR/GPIO66 AU29 AW29 AR27 AV27 VGA_CLKREQ#_R AY29 CR_CLKREQ# LAN_CLKREQ# WLAN_CLKREQ# CR_CLKREQ# LAN_CLKREQ# WLAN_CLKREQ# R907 33_0402_5% TEST0 GPIO51 AP15 AV13 BA9 BA10 AV15 APU_PCIE_RST#_BUF SLP_S5_L GPIO50 C1376 1000P_0402_50V7K ESDP@ AY23 AY20 BA20 PWR_GOOD SD_DATA2/GPIO79 ATE Test PWR_BTN_L BA23 AY22 LPC_RST_A# APU_PCIE_RST#_BUF 2 R602 33_0402_5% 1 LPC_RST# E UAPUD C615 150P_0402_50V8J D 2 RTC_CLK C682 22P_0402_50V8J C686 18P_0402_50V8J FT3 REV 0.51 A6@ STRAPS OF APU A6-6400 AM6400ITJ44JBA 2.4G BGA 769P HDA for AUDIO RP15 +3VALW HDA_BITCLK_AUDIO HDA_SYNC_AUDIO HDA_RST_AUDIO# HDA_SDOUT_AUDIO PU +3VALW + PD R691 HDA_BITCLK HDA_SYNC HDA_RST# HDA_SDOUT LPC_FRAME# 33_0804_8P4R_5% EMIU@ C264 22P_0402_50V8J 10K_0402_5% @ R686 10K_0402_5% LPC_CLK0_EC LPC_CLK1 GEVENT2_L SYS_RESET_L RTC_CLK H SPI ROM (DEFAULT) BOOT FAIL TIMER ENABLED CLKGEN ENABLE (DEFAULT) 1.8V SPI ROM NORMAL POWR UP/RESET TIMING (DEFAULT) L LPC ROM BOOT FAIL TIMER DISABLED (DEFAULT) CLKGEN DISABLED 3.3V SPI ROM (DEFAULT) EMI APU_GPIO174 reserved Coin Battery Direct DC 3 HDA_SDIN0 TEST0 CS_JTAG_TMS_TEST1 TEST2 15K_0804_8P4R_5% B 1 2 1 1 1 1 2014/03/03 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2015/03/03 Deciphered Date Title FT3 GPIO/AZ/MISC/STRAPS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 LA-B291P Date: A 1 2 RP10 @ VGA_CLKREQ#_R @ 2 10K_0402_5% PX@ 10K_0402_5% @ R689 @ R688 1K_0804_8P4R_5% HDA_BITCLK 2 10K_0402_5% @ @ 2.2K_0402_5% R684 @ 2.2K_0402_5% BT_OFF# 2.2K_0402_5% 10K_0402_5% @ 2.2K_0402_5% @ RTC_CLK +3VALW RP9 @ 2K_0402_5% R687 PU +3VALW + PD GEVENT2# 2K_0402_5% VGA_CLKREQ#_R 1U_0402_6.3V6K C212 2K_0402_5% R618 UMA@ 8.2K_0402_5% 2 LAN_CLKREQ# APU_SCLK0 APU_SDATA0 R953 8.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% R951 @ R950 R621 R673 R674 1U_0402_6.3V6K C209 R929 CR_CLKREQ# WLAN_CLKREQ# R927 8.2K_0402_5% 8.2K_0402_5% LPC_FRAME# LPC_CLK0_EC LPC_CLK1 R926 @ @ 2 BLINK RB751V-40TE17_SOD323-2 R623 R622 10K_0402_5% PWR_GOOD_APU R903 PD SYS_RESET_L SCS00005C00 R954 SYS_PWRGD_EC 10K_0402_5% D15 +3VS EC_RSMRST#_R R952 PU +3VS RB751V-40TE17_SOD323-2 @ 10K_0402_5% EC_RSMRST# R949 @ 10K_0402_5% 0_0402_5% EC_LID_OUT# USB_OC0# USB_OC1# R928 100K_0402_5% 100K_0402_5% 100K_0402_5% @ 10K_0402_5% @ D13 R685 10K_0402_5% R925 R656 R650 R651 R345 47K_0402_5% SCS00005C00 10K_0402_5% R1650 @ R1649 +1.8VALW Must connected to 10 ms RC delay circuit on +1.8-V S5 power rail R904 10K_0402_5% @ EC_RSMRST# , POWER_GOOD follow CRB (APU side 1.8V power rail) 10K_0402_5% @ APU_SCLK1 APU_SDATA1 APU_PCIE_WAKE# DGPU_PWR_EN 0_0402_5% R902 R1648 10K_0804_8P4R_5% RP14 +3VALW +3VS +3VALW PU +3VALW C D Monday, March 03, 2014 Sheet E of 46 B C VDDBT_RTC_G U102 180P_0402_50V8J C1365 0.22U_0402_10V6K +3VALW @ VDD_33 1U_0402_6.3V6K C1253 1U_0402_6.3V6K 2 C1252 180P_0402_50V8J 1U_0402_6.3V6K 180P_0402_50V8J C1257 C1249 C1197 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K C1194 C1193 C1191 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K C1192 C1202 C1201 C1200 2 R582 0_0603_5% 0_0402_5% UAPUF C1232 180P_0402_50V8J 1U_0402_6.3V6K C1255 1U_0402_6.3V6K @ 1U_0402_6.3V6K 4.7U_0603_6.3V6K 1 C1254 C1256 C1161 0.1U_0402_16V7K ESDP@ C1373 2 C1233 180P_0402_50V8J 1U_0402_6.3V6K 1U_0402_6.3V6K C1240 1U_0402_6.3V6K C1239 1U_0402_6.3V6K C1238 1U_0402_6.3V6K 10U_0603_6.3V6M C1237 C1236 +0.95VALW AL10 AL11 +1.5VS B1 B2 +1.8VALW VDDIO_MEM_S_7 VDDIO_MEM_S_8 VDDIO_MEM_S_9 VDDIO_MEM_S_10 VDDIO_MEM_S_11 VDDIO_MEM_S_12 VDDIO_MEM_S_13 VDDIO_MEM_S_14 VDDIO_MEM_S_15 VDDIO_MEM_S_16 VDDIO_MEM_S_17 VDDIO_MEM_S_18 VDDIO_MEM_S_19 VDDIO_MEM_S_20 VDDIO_MEM_S_21 VDDIO_MEM_S_22 VDDIO_MEM_S_23 L13 VDDCR_NB_2 L17 VDDCR_NB_3 N11 VDDCR_NB_4 N13 VDDCR_NB_5 N17 VDDCR_NB_6 R11 VDDCR_NB_7 R13 VDDCR_NB_8 R17 VDDCR_NB_9 U13 VDDCR_NB_10 U17 VDDCR_NB_11 W13 VDDCR_NB_12 W17 VDDCR_NB_13 AA13 VDDCR_NB_14 AA17 VDDCR_NB_15 AC13 VDDCR_NB_16 AC17 VDDCR_NB_17 AE15 VDDCR_NB_18 AE17 VDDCR_NB_19 AE19 VDDCR_NB_20 AG17 VDDCR_NB_21 AG21 180P_0402_50V8J C1245 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K VDDIO_AZ_ALW_1 AL13 AM13 AR5 AU4 AV7 AW5 AE11 AE13 AJ11 AJ13 +0.95VALW VDD_18_ALW_1 VDD_18_1 VDD_18_ALW_2 VDD_18_2 VDD_33_ALW_1 VDD_33_1 VDD_33_ALW_2 VDD_33_2 VDD_095_1 VDD_095_USB3_DUAL_2 VDD_095_USB3_DUAL_3 VDD_095_USB3_DUAL_4 VDD_095_ALW_1 VDD_095_ALW_2 VDD_095_ALW_3 VDD_095_ALW_4 VDD_095_GFX_2 W10 AN4 +APU_CORE_NB +1.8VS +3VS +0.95VS A8 A13 A23 A31 A35 A39 B8 B13 B23 B31 B39 C1 C2 C5 C7 C9 C11 C13 C15 C17 C19 C21 C23 C25 C27 C29 C31 C33 C35 C37 C39 C41 D9 D11 D13 E3 E4 E9 E11 E13 E27 E31 E35 E38 E39 G3 G7 G11 G13 G15 G17 G21 G25 G29 G35 G37 G39 G41 H11 H13 H23 H31 GND VSS_1 VSS_63 VSS_2 VSS_64 VSS_3 VSS_65 VSS_4 VSS_66 VSS_5 VSS_67 VSS_6 VSS_68 VSS_7 VSS_69 VSS_8 VSS_70 VSS_9 VSS_71 VSS_10 VSS_72 VSS_11 VSS_73 VSS_12 VSS_74 VSS_13 VSS_75 VSS_14 VSS_76 VSS_15 VSS_77 VSS_16 VSS_78 VSS_17 VSS_79 VSS_18 VSS_80 VSS_19 VSS_81 VSS_20 VSS_82 VSS_21 VSS_83 VSS_22 VSS_84 VSS_23 VSS_85 VSS_24 VSS_86 VSS_25 VSS_87 VSS_26 VSS_88 VSS_27 VSS_89 VSS_28 VSS_90 VSS_29 VSS_91 VSS_30 VSS_92 VSS_31 VSS_93 VSS_32 VSS_94 VSS_33 VSS_95 VSS_34 VSS_96 VSS_35 VSS_97 VSS_36 VSS_98 VSS_37 VSS_99 VSS_38 VSS_100 VSS_39 VSS_101 VSS_40 VSS_102 VSS_41 VSS_103 VSS_42 VSS_104 VSS_43 VSS_105 VSS_44 VSS_106 VSS_45 VSS_107 VSS_46 VSS_108 VSS_47 VSS_109 VSS_48 VSS_110 VSS_49 VSS_111 VSS_50 VSS_112 VSS_51 VSS_113 VSS_52 VSS_114 VSS_53 VSS_115 VSS_54 VSS_116 VSS_55 VSS_117 VSS_56 VSS_118 VSS_57 VSS_119 VSS_58 VSS_120 VSS_59 VSS_121 VSS_60 VSS_122 VSS_61 VSS_123 VSS_62 VSS_124 J3 J7 J8 J39 K11 K13 K17 K19 K21 K23 K25 K27 K29 K31 L3 L7 L8 L10 L11 L15 L19 L31 L39 L41 M1 M2 N3 N7 N15 N19 N25 N29 N31 N39 P1 P2 R3 R7 R15 R19 R25 R29 R39 R41 U1 U2 U3 U7 U8 U11 U15 U19 U25 U29 U31 U39 W3 W5 W11 W15 W19 W25 W29 W39 W41 Y1 Y2 AA3 AA7 AA8 AA11 AA15 AA19 AA25 AA29 AA39 AC3 AC7 AC11 AC15 AC19 AC25 AC29 AC31 AC39 AC41 AE3 AE7 AE25 AE29 AE32 AE39 AG3 AG5 AG10 AG11 AG13 AG15 AG19 AG25 AG29 AG31 AG39 AG41 AH1 AH2 AJ3 AJ7 AJ15 AJ17 AJ19 AJ23 AJ25 AJ29 AJ31 AJ32 AJ39 AL3 AL8 AL15 AL17 AL19 AL25 AL29 VSS_188 VSS_127 VSS_189 VSS_128 VSS_190 VSS_129 VSS_191 VSS_130 VSS_192 VSS_131 VSS_193 VSS_132 VSS_194 VSS_133 VSS_195 VSS_134 VSS_196 VSS_135 VSS_197 VSS_136 VSS_198 VSS_137 VSS_199 VSS_138 VSS_200 VSS_139 VSS_201 VSS_140 VSS_202 VSS_141 VSS_203 VSS_142 VSS_204 VSS_143 VSS_205 VSS_144 VSS_206 VSS_145 VSS_207 VSS_146 VSS_208 VSS_147 VSS_209 VSS_148 VSS_210 VSS_149 VSS_211 VSS_150 VSS_212 VSS_151 VSS_213 VSS_152 VSS_214 VSS_153 VSS_215 VSS_154 VSS_216 VSS_155 VSS_217 VSS_156 VSS_218 VSS_157 VSS_219 VSS_158 VSS_220 VSS_159 VSS_221 VSS_160 VSS_222 VSS_161 VSS_223 VSS_162 VSS_224 VSS_163 VSS_225 VSS_164 VSS_226 VSS_165 VSS_227 VSS_166 VSS_228 VSS_167 VSS_229 VSS_168 VSS_230 VSS_169 VSS_231 VSS_170 VSS_232 VSS_171 VSS_233 VSS_172 VSS_234 VSS_173 VSS_235 VSS_174 VSS_236 VSS_175 VSS_237 VSS_176 VSS_238 VSS_177 VSS_239 VSS_178 VSS_240 VSS_179 VSS_241 VSS_180 VSS_242 VSS_181 VSSBG_DAC VSS_182 VBURN VSS_183 PSEN AL39 AL41 AM11 AM27 AM31 AN3 AN7 AN39 AP31 AR3 AR13 AR17 AR21 AR25 AR29 AR39 AR41 AU1 AU2 AU3 AU15 AU19 AU23 AU27 AU39 AV9 AW3 AW7 AW13 AW15 AW17 AW19 AW21 AW23 AW25 AW27 AW31 AW33 AW35 AW37 AW39 AW41 AY13 AY15 AY18 AY30 BA2 BA7 BA13 BA15 BA18 BA21 BA25 BA31 BA35 BA39 A15 AL31 AM29 VSS_184 VSS_185 VSS_186 FT3 REV 0.51 A6@ FT3 REV 0.51 A6-6400 AM6400ITJ44JBA 2.4G BGA 769P A6-6400 AM6400ITJ44JBA 2.4G BGA 769P A6@ +0.95VS_APU_GFX A6-6400 AM6400ITJ44JBA 2.4G BGA 769P Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/03 2015/03/03 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: B VSS_187 VSS_126 FT3 REV 0.51 Issued Date A VSS_125 VDD_095_GFX_3 AA10 VDDBT_RTC_G A6@ VDD_18_ALW AM15 AM17 AG23 VDD_095_2 AG27 VDD_095_3 AJ21 VDD_095_4 AJ27 VDD_095_5 AL21 VDD_095_6 AL23 VDD_095_7 AL27 VDD_095_8 AM23 VDD_095_9 AM25 VDD_095_USB3_DUAL_1 @ VDD_095_ALW A2 A3 B3 C3 VDD_095_GFX_1 U10 +RTCBATT_R +APU_CORE VDDIO_AZ_ALW_2 VDD_18_4 C1248 C1246 1U_0402_6.3V6K 4.7U_0603_6.3V6K C1250 C1244 C1160 1U_0402_6.3V6K 1U_0402_6.3V6K C1222 1U_0402_6.3V6K VDDIO_MEM_S_6 VDD_18_3 +1.8VALW C1219 1U_0402_6.3V6K C1217 VDD_095_USB3_DUAL C1220 @ 180P_0402_50V8J 1U_0402_6.3V6K 1U_0402_6.3V6K C1218 C1221 C1214 10U_0603_6.3V6M 1U_0402_6.3V6K 10U_0603_6.3V6M VDDIO_MEM_S_5 +3VALW_APU C1216 C938 C937 VDDIO_MEM_S_4 VDD_18 +1.8VS +0.95VALW VDDIO_MEM_S_3 VDDCR_NB_1 @ +0.95VALW VDDCR_CPU_2 L23 VDDCR_CPU_3 L25 VDDCR_CPU_4 L27 VDDCR_CPU_5 L29 VDDCR_CPU_6 N21 VDDCR_CPU_7 N23 VDDCR_CPU_8 N27 VDDCR_CPU_9 R21 VDDCR_CPU_10 R23 VDDCR_CPU_11 R27 VDDCR_CPU_12 U21 VDDCR_CPU_13 U23 VDDCR_CPU_14 U27 VDDCR_CPU_15 W21 VDDCR_CPU_16 W23 VDDCR_CPU_17 W27 VDDCR_CPU_18 AA21 VDDCR_CPU_19 AA23 VDDCR_CPU_20 AA27 VDDCR_CPU_21 AC21 VDDCR_CPU_22 AC23 VDDCR_CPU_23 AC27 VDDCR_CPU_24 AE21 VDDCR_CPU_25 AE23 VDDCR_CPU_26 AE27 VDDIO_MEM_S_2 UAPUH GND VDDCR_CPU_1 L21 VDDIO_MEM_S_1 +1.8VALW/+1.8VS OF APU C933 2 0.1U_0402_16V7K ESDP@ C1372 1U_0402_6.3V6K 10U_0603_6.3V6M C1203 C936 1 @ VDD_095_GFX L22 FBMA-L11-201209-121LMA50T_0805 180P_0402_50V8J @ 180P_0402_50V8J C1259 180P_0402_50V8J C1258 C1231 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J C1230 C1207 C1208 180P_0402_50V8J 1U_0402_6.3V6K C1213 C1260 1U_0402_6.3V6K C1206 @ 1U_0402_6.3V6K 1U_0402_6.3V6K C1204 1U_0402_6.3V6K C1205 10U_0603_6.3V6M 1U_0402_6.3V6K C1199 +0.95VS_APU_GFX VDD_095 C1198 10U_0603_6.3V6M C934 C935 @ +0.95VALW/+0.95VS OF APU +0.95VS 180P_0402_50V8J 0.1U_0402_16V7K C1210 180P_0402_50V8J C1211 0.1U_0402_16V7K C932 0.1U_0402_16V7K C930 C931 0.1U_0402_16V7K 0.1U_0402_16V7K C929 C928 0.1U_0402_16V7K 0.1U_0402_16V7K C927 0.1U_0402_16V7K 10U_0603_6.3V6M 10U_0603_6.3V6M C926 C923 C949 10U_0603_6.3V6M C925 C924 @ +1.5VS VDDIO_MEM_S UAPUG POWER J35 L32 L37 N35 R31 R37 U32 U35 W31 W32 W37 AA31 AA35 AC32 AC37 AE31 AE35 AG32 AG37 AJ35 AL32 AL37 AR35 +1.35V VDD_33_ALW PLANE SPLIT R131 KABINI@ TEMPINRETUNE 1 VDDIO_AZ_ALW (Could be S0 or S5 power rail) +1.35V AP2138N-1.5TRG1_SOT23-3 Need use+3.3V transfer to +1.5V LDO to APU side for Beema +3VALW/+3VS OF APU +3VALW_APU 需需LDO轉1.5V, 20130930 added +3VS 1 +RTCBATT VDDCR_NB Need OPEN Vin GND for Clear CMOS INTEGRATED GPU POWER OF APU CLRP1 @ SHORT PADS Vout @ +APU_CORE_NB 10K_0402_5% 1 1 2 R93 C1190 1U_0402_6.3V6K C1189 1U_0402_6.3V6K 1U_0402_6.3V6K C1188 C1187 1U_0402_6.3V6K C1186 1U_0402_6.3V6K 1U_0402_6.3V6K C1184 C1183 1U_0402_6.3V6K 1U_0402_6.3V6K C1182 C1181 1U_0402_6.3V6K 1U_0402_6.3V6K C1180 C1179 W=20mils +RTCBATT_R +RTCBATT +RTCBATT C810 680P_0603_50VK VDDBT_RTC_G VDDCR_CPU +APU_CORE E +RTCBATT_3V RTC OF APU CORE POWER OF APU D C811 0.1U_0603_25V7K A C D FT3 PWR/GND Rev 1.0 LA-B291P Monday, March 03, 2014 Sheet E of 46 B +1.35V DDRAB_SDQS1# DDRAB_SDQS1 DDRAB_SDQS1# DDRAB_SDQS1 DDRAB_SDQ10 DDRAB_SDQ11 DDRAB_SDQ16 DDRAB_SDQ17 DDRAB_SDQS6# DDRAB_SDQS6 DDRAB_SDQS6# DDRAB_SDQS6 DDRAB_SDQ50 DDRAB_SDQ51 DDRAB_SDQ56 DDRAB_SDQ57 DDRAB_SDM7 DDRAB_SDQ58 DDRAB_SDQ59 R69 10K_0402_5% +3VS +0.675VS 205 R70 +3VS GND2 DDRA_ODT1 2 +1.35V +1.35V R65 1K_0402_1% DDRA_CLK1 DDRA_CLK1# DDRAB_SBS1# DDRAB_SRAS# R66 1K_0402_1% +VREF_CA +VREF_DQ DDRA_SCS0# DDRA_ODT0 DDRA_ODT1 R68 1K_0402_1% R67 1K_0402_1% 15mil +VREF_CA DDRAB_SDQ36 DDRAB_SDQ37 DDRAB_SDM4 DDRAB_SDQ38 DDRAB_SDQ39 DDRAB_SDQ44 DDRAB_SDQ45 DDRAB_SDQS5# DDRAB_SDQS5 2 DDRAB_SDQS5# DDRAB_SDQS5 DDRAB_SDQ46 DDRAB_SDQ47 DDRAB_SDQ52 DDRAB_SDQ53 DDRAB_SDM6 DDRAB_SDQ54 DDRAB_SDQ55 DDRAB_SDQ60 DDRAB_SDQ61 DDRAB_SDQS7# DDRAB_SDQS7 DDRAB_SDQS7# DDRAB_SDQS7 DDRAB_SDQ62 DDRAB_SDQ63 MEM_MAB_EVENT# MEM_MAB_EVENT# APU_SDATA0 APU_SCLK0 +0.675VS 206 10K_0402_5% C1135 2.2U_0603_6.3V6K GND1 DDRA_SCS0# DDRA_ODT0 @ DDRAB_SMA2 DDRAB_SMA0 DDRAB_SBS1# DDRAB_SRAS# 4.7U_0603_6.3V6K DDRAB_SMA6 DDRAB_SMA4 DDRA_CLK1 DDRA_CLK1# 0.1U_0402_16V4Z DDRAB_SDQ48 DDRAB_SDQ49 C1127 DDRAB_SDQ42 DDRAB_SDQ43 @ C1126 DDRAB_SDM5 @ 0.1U_0402_16V4Z DDRAB_SDQ40 DDRAB_SDQ41 @ C1167 DDRAB_SDQ34 DDRAB_SDQ35 @ VREF for DIMM1,2 DDRAB_SMA11 DDRAB_SMA7 C1134 DDRAB_SDQS4# DDRAB_SDQS4 DDRAB_SDQS4# DDRAB_SDQS4 0.1U_0402_25V6K DDRA_CKE1 DDRAB_SMA15 DDRAB_SMA14 1000P_0402_50V7K DDRAB_SDQ32 DDRAB_SDQ33 DDRA_CKE1 0.1U_0402_16V4Z DDRAB_SMA13 DDRA_SCS1# DDRA_SCS1# @ 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 C1123 DDRAB_SDQ30 DDRAB_SDQ31 0.1U_0402_16V4Z DDRAB_SWE# DDRAB_SCAS# DDRAB_SDQS3# DDRAB_SDQS3 C1122 DDRAB_SBS0# DDRAB_SWE# DDRAB_SCAS# DDRAB_SDQS3# DDRAB_SDQS3 0.1U_0402_16V4Z DDRAB_SMA10 DDRAB_SBS0# DDRAB_SDQ28 DDRAB_SDQ29 C1121 DDRA_CLK0 DDRA_CLK0# DDRAB_SDQ22 DDRAB_SDQ23 0.1U_0402_16V4Z DDRA_CLK0 DDRA_CLK0# +0.675VS C1120 DDRAB_SMA3 DDRAB_SMA1 +1.35V DDRAB_SDM2 0.1U_0402_16V4Z DDRAB_SMA8 DDRAB_SMA5 CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT DDRAB_SDQ20 DDRAB_SDQ21 C1119 DDRAB_SMA12 DDRAB_SMA9 CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT +1.35V/+0.675VS OF DIMM1 0.1U_0402_16V4Z DDRAB_SBS2# MEM_MAB_RST# DDRAB_SDQ14 DDRAB_SDQ15 C1118 DDRA_CKE0 DDRAB_SBS2# 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 DDRAB_SDM1 MEM_MAB_RST# 0.1U_0402_16V4Z DDRA_CKE0 C1117 DDRAB_SDQ26 DDRAB_SDQ27 DDRAB_SMA[0 15] DDRAB_SDQ12 DDRAB_SDQ13 0.1U_0402_16V4Z DDRAB_SDM3 DDRAB_SMA[0 15] 0.1U_0402_16V4Z DDRAB_SDQ24 DDRAB_SDQ25 DDRAB_SDM[0 7] DDRAB_SDQ6 DDRAB_SDQ7 C1116 DDRAB_SDQ18 DDRAB_SDQ19 DDRAB_SDQS0# DDRAB_SDQS0 DDRAB_SDQ[0 63] DDRAB_SDM[0 7] C1115 DDRAB_SDQS2# DDRAB_SDQS2 DDRAB_SDQS0# DDRAB_SDQS0 DDRAB_SDQ[0 63] C1114 DDRAB_SDQS2# DDRAB_SDQS2 DDRAB_SDQ4 DDRAB_SDQ5 DDRAB_SDQ8 DDRAB_SDQ9 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 1 VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS DDRAB_SDQ2 DDRAB_SDQ3 VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS DDRAB_SDM0 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 DDRAB_SDQ0 DDRAB_SDQ1 C1142 C1176 1000P_0402_50V7K 0.1U_0402_25V6K E 15mil JDIMM2 Reverse Type Near CPU +1.35V JDIMM2 D +VREF_DQ C A 1 2 C1136 0.1U_0402_16V4Z ARGOS_DS2RK-20401-TP4B ME@ SP070014D00 2014/03/03 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification DIMM_A H:4mm 2015/03/03 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D DDR3 SODIMM-I Socket Rev 1.0 LA-B291P Monday, March 03, 2014 Sheet E of 46 A B +VREF_DQ +1.35V C1143 C1177 1000P_0402_50V7K 0.1U_0402_25V6K DDRAB_SDQ0 DDRAB_SDQ1 DDRAB_SDM0 DDRAB_SDQ2 DDRAB_SDQ3 DDRAB_SDQ8 DDRAB_SDQ9 DDRAB_SDQS1# DDRAB_SDQS1 DDRAB_SDQS1# DDRAB_SDQS1 DDRAB_SDQ10 DDRAB_SDQ11 DDRAB_SDQ16 DDRAB_SDQ17 DDRAB_SDQS6# DDRAB_SDQS6 DDRAB_SDQS6# DDRAB_SDQS6 DDRAB_SDQ50 DDRAB_SDQ51 DDRAB_SDQ56 DDRAB_SDQ57 DDRAB_SDM7 DDRAB_SDQ58 DDRAB_SDQ59 R71 10K_0402_5% 10K_0402_5% +3VS R72 +0.675VS 205 207 GND1 BOSS1 2 4.7U_0603_6.3V6K DDRAB_SDQ48 DDRAB_SDQ49 @ 0.1U_0402_16V4Z DDRAB_SDQ42 DDRAB_SDQ43 C1158 DDRAB_SDM5 C1175 DDRAB_SDQ40 DDRAB_SDQ41 @ 1 @ + C250 330U_D3_2.5VY_R6M @ DDRAB_SMA6 DDRAB_SMA4 DDRAB_SMA2 DDRAB_SMA0 DDRB_CLK1 DDRB_CLK1# DDRAB_SBS1# DDRAB_SRAS# DDRB_SCS0# DDRB_ODT0 DDRB_ODT1 DDRB_CLK1 DDRB_CLK1# DDRAB_SBS1# DDRAB_SRAS# DDRB_SCS0# DDRB_ODT0 DDRB_ODT1 15mil +VREF_CA DDRAB_SDQ36 DDRAB_SDQ37 DDRAB_SDM4 DDRAB_SDQ38 DDRAB_SDQ39 DDRAB_SDQ44 DDRAB_SDQ45 DDRAB_SDQS5# DDRAB_SDQS5 C1174 DDRAB_SDQ34 DDRAB_SDQ35 DDRAB_SMA11 DDRAB_SMA7 C1139 DDRAB_SDQS4# DDRAB_SDQS4 DDRAB_SDQS4# DDRAB_SDQS4 0.1U_0402_25V6K +1.35V DDRAB_SMA15 DDRAB_SMA14 1000P_0402_50V7K DDRAB_SDQ32 DDRAB_SDQ33 DDRB_CKE1 0.1U_0402_16V4Z DDRB_SCS1# @ DDRB_CKE1 0.1U_0402_16V4Z DDRAB_SMA13 DDRB_SCS1# DDRAB_SDQS3# DDRAB_SDQS3 DDRAB_SDQ30 DDRAB_SDQ31 C1172 DDRAB_SWE# DDRAB_SCAS# DDRAB_SDQS3# DDRAB_SDQS3 0.1U_0402_16V4Z DDRAB_SWE# DDRAB_SCAS# DDRAB_SDQ28 DDRAB_SDQ29 C1171 DDRAB_SBS0# DDRAB_SDQ22 DDRAB_SDQ23 0.1U_0402_16V4Z DDRAB_SMA10 DDRAB_SBS0# +0.675VS C1170 DDRB_CLK0 DDRB_CLK0# +1.35V DDRAB_SDM2 0.1U_0402_16V4Z DDRB_CLK0 DDRB_CLK0# DDRAB_SDQ20 DDRAB_SDQ21 C1169 DDRAB_SMA3 DDRAB_SMA1 +1.35V/+0.675VS OF DIMM2 0.1U_0402_16V4Z DDRAB_SMA8 DDRAB_SMA5 CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT MEM_MAB_RST# DDRAB_SDQ14 DDRAB_SDQ15 C1168 DDRAB_SMA12 DDRAB_SMA9 CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT DDRAB_SDM1 MEM_MAB_RST# 0.1U_0402_16V4Z DDRAB_SBS2# 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 DDRAB_SMA[0 15] C1165 DDRB_CKE0 DDRAB_SBS2# 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 DDRAB_SDQ12 DDRAB_SDQ13 0.1U_0402_16V4Z DDRB_CKE0 DDRAB_SMA[0 15] DDRAB_SDM[0 7] DDRAB_SDQ6 DDRAB_SDQ7 C1162 DDRAB_SDQ26 DDRAB_SDQ27 DDRAB_SDQS0# DDRAB_SDQS0 E DDRAB_SDQ[0 63] DDRAB_SDM[0 7] 0.1U_0402_16V4Z DDRAB_SDM3 DDRAB_SDQS0# DDRAB_SDQS0 DDRAB_SDQ[0 63] 0.1U_0402_16V4Z DDRAB_SDQ24 DDRAB_SDQ25 DDRAB_SDQ4 DDRAB_SDQ5 C1132 DDRAB_SDQ18 DDRAB_SDQ19 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS C1155 DDRAB_SDQS2# DDRAB_SDQS2 VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS C1133 DDRAB_SDQS2# DDRAB_SDQS2 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 D JDIMM1 Standard Type Near User +1.35V JDIMM1 15mil C DDRAB_SDQS5# DDRAB_SDQS5 DDRAB_SDQ46 DDRAB_SDQ47 DDRAB_SDQ52 DDRAB_SDQ53 DDRAB_SDM6 DDRAB_SDQ54 DDRAB_SDQ55 DDRAB_SDQ60 DDRAB_SDQ61 DDRAB_SDQS7# DDRAB_SDQS7 DDRAB_SDQS7# DDRAB_SDQS7 DDRAB_SDQ62 DDRAB_SDQ63 MEM_MAB_EVENT# APU_SDATA0 APU_SCLK0 +0.675VS 206 208 GND2 BOSS2 ARGOS_DS2SK-20401-TP4B ME@ SP070014E00 2014/03/03 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification DIMM_B H:4mm 2015/03/03 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D DDR3 SODIMM-II Socket Rev 1.0 LA-B291P Monday, March 03, 2014 Sheet E 10 of 46 B C D E +3VS +3VDD_CODEC +IOVDD_CODEC +1.5VS RA2 RA3 +5VS_PVDD External DMIC DMIC_DAT DMIC_CLK EMIP@ LA1 RA8 31 30 +LINE1-VREFO-R SM01000I000 0_0402_5% DMIC_CLK_R 10K_0402_5% RA11 @ EC_MUTE# HDA_RST_AUDIO# 0_0402_5% 47 11 12 PC_BEEP PLUG_IN_R CA15 13 14 37 35 1U_0402_6.3V6K 36 +3VDD_CODEC @ CA17 +3VLP 4.7U_0603_6.3V6K 233VB@ RA161 100K_0402_5% CA19 RA18 1 2.2U_0402_6.3V6M @ 0_0402_5% RA18 pop on ALC283, NC on ALC233 20 19 49 MIC2-L(PORT-F-L) /RING2 MIC2-R(PORT-F-R) /SLEEVE LINE1-VREFO-L LINE1-VREFO-R GPIO0/DMIC-DATA GPIO1/DMIC-CLK PDB RESETB ALC233-CG HPOUT-L(PORT-I-L) HPOUT-R(PORT-I-R) SYNC BCLK SPK_R2+ SPK_R1- 32 33 PCBEEP MONO-OUT SENSE A SENSE B MIC2-VREFO HP_OUTL HP_OUTR HDA_RST_AUDIO# Headphone 10 HDA_SYNC_AUDIO HDA_BITCLK_AUDIO LDO3-CAP LDO2-CAP LDO1-CAP HDA_SDIN0_AUDIO VREF CPVREF JDREF CPVEE CA12 EMIU@ RA12 HDA_SDOUT_AUDIO HDA_SDIN0 AVSS1 AVSS2 29 39 27 LDO3 LDO2 LDO1 28 15 34 CA14 2.2U_0402_6.3V6M CA16 2.2U_0402_6.3V6M 25 38 100K_0402_5% CA5 CA6 QA1 MESS138W-G_SOT323-3 233@ +3VS 233VB@ RA38 100K_0402_5% RA13 233@ PLUG_IN_R 1U_0402_6.3V6K RA17 20K_0402_1% W=40mils W=40mils 233@ S Combo Jack (Normal Open) EXT_MIC_SLEEVE EXT_MIC_RING2 HP_OUTL HP_OUTR EMIP@ EMIP@ EMIP@ EMIP@ RA19 RA20 RA22 RA23 CA20 1U_0402_6.3V6K For Universal Audio Jack 39.2K_0402_1% SM010010710 SM010010710 2 1 2 SM01000FH00 SM01000FH00 0_0603_5% 0_0603_5% 47_0402_5% 47_0402_5% PLUG_IN LINE1-L CA21 1U_0402_6.3V6K LINE1-R CA22 1U_0402_6.3V6K RA29 4.7K_0402_5% 0_0402_5% RA24 0_0402_5% RA25 0_0402_5% +LINE1-VREFO-R RA32 4.7K_0402_5% PLUG_IN EMI UA1 ALC233-VB2-CG MQFN 48P 233VB@ RA21 QA2 MESS138W-G_SOT323-3 233@ Vendor recommended 10/16 RA15 CA18 JDREF CPVEE D G For ALC233VB only 16 2.2U_0402_6.3V6M 233VB@ RA13 200K_0402_1% ALC233-CG_MQFN48_6X6 EMI +MIC2-VREFO CA13 S 22P_0402_50V8J DVSS Thermal PAD 233@ RA14 10K_0402_5% D G EMI 33_0402_5% 48 CPVDD MIC-CAP KABINI need to use this part Due to RST is 1.5V power rail Intel project can use dual 2N7002 RA101 EMIU@ 33_0402_5% SDATA-OUT SDATA-IN SPDIF-OUT/GPIO2 CBP CBN SPK_L1SPK_L2+ 45 44 SPK-OUT-R+ SPK-OUT-R- 43 42 EXT_MIC_SLEEVE SPK-OUT-LSPK-OUT-L+ 233@ RA9 100K_0402_5% 26 46 41 40 AVDD2 AVDD1 PVDD2 Place near Pin26 HGNDB HGNDA HPOUT_L HPOUT_R RA7 EMI +3VLP @ @ HGNDB HGNDA HPOUT_L HPOUT_R 10K_0402_5% RA27 17 18 2 EXT_MIC_RING2 EXT_MIC_SLEEVE Place near Pin40 0_0603_5% Place RA4 on AGND/DGND moat 2.2K_0402_5% 2.2K_0402_5% LINE2-L(PORT-E-L) LINE2-R(PORT-E-R) 1U_0402_6.3V6K 1 RA6 1 +MIC2-VREFO LINE1-L(PORT-C-L) LINE1-R(PORT-C-R) 1 24 23 PVDD1 DVDD wide 40MIL DVDD-IO CA8 0_0402_5% RA5 +3VDD_CODEC 22 21 RA4 +1.5VS LINE1-L LINE1-R Place near Pin9 +5VS +IOVDD_CODEC 233@ UA1 connect to +VDDIO_AZ_ALW CA11 Place near Pin1 +5VDDA_CODEC 2.2U_0402_6.3V6M 1 CA7 1U_0402_16V7K 1 1U_0402_16V7K CA1 2 0_0603_5% RA26 10K_0402_5% 0_0805_5% 1U_0402_16V7K CA3 4.7U_0603_6.3V6K CA2 RA1 CA4 +5VS 1U_0402_16V7K 1 1U_0402_6.3V6K 0_0603_5% 1U_0402_16V7K 1 A RA28 EMIU@ 0_0402_5% GND GNDA 11/20 Change symbol of JSPK1 to SP02000H700 EMI wide 40MIL JSPK1 RA34 CA24 CA25 PC_BEEP 1U_0402_16V7K 1K_0402_5% 1U_0402_16V7K 2 2 1000P_0402_50V7K 1U_0402_16V7K SPK_R1-_CONN SPK_R2+_CONN SPK_L1-_CONN SPK_L2+_CONN 1000P_0402_50V7K EMIP@ CA31 APU_SPKR CA23 0_0603_5% 0_0603_5% 0_0603_5% 0_0603_5% 1000P_0402_50V7K EMIP@ CA30 BEEP# 2 2 EMIP@ CA28 1 1 ESD ACES_85205-04001 ME@ SP020008X00 +5VS ESDU@ SPK_R1-_CONN G5 G6 DA3 I/O4 I/O2 VDD GND I/O3 I/O1 SPK_L2+_CONN EC Beep APU Beep LA5 LA6 LA7 LA8 1000P_0402_50V7K EMIP@ CA29 SPK_R1SPK_R2+ SPK_L1SPK_L2+ PC Beep @ RA36 10K_0402_5% 4 SPK_R2+_CONN Issued Date Compal Electronics, Inc Compal Secret Data 2014/03/03 Deciphered Date 2015/03/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title HD Audio Codec_ALC233 Size C Date: A B C D SPK_L1-_CONN AZC099-04S.R7G_SOT23-6 ESD protection needs to be placed near connector side Security Classification Document Number Rev 1.0 LA-B291P Monday, March 03, 2014 Sheet E 30 of 46 D D +AV12 +DV12S CC2 CC3 +3VS CC4 1U_0402_16V7K 4.7U_0603_6.3V6K 1U_0402_16V7K 4.7U_0603_6.3V6K CC1 CC5 4.7U_0603_6.3V6K CC6 1U_0402_16V7K UCR1 +Card_3V3 LC1 PBY160808T-301Y-N_0603 +Card_3V3 +DV33_18 +AV12 +DV12S 15 11 +Card_3V3_R 10 RC1 6.2K_0402_1% 3V3_IN DV33_18 AV12 DV12_S Card_3V3 GND 25 RREF 0_0402_5% SD_D1 RC3 SD_CLK_R RC5 RC6 RC7 0_0402_5% SD_D0 0_0402_5% 0_0402_5% 0_0402_5% SD_CMD SD_D3 SD_D2 RC2 C PCIE_ATX_C_DRX_P0 PCIE_ATX_C_DRX_N0 PCIE_DTX_C_ARX_P0 PCIE_DTX_C_ARX_N0 CC7 CC8 +DV33_18 1U_0402_6.3V6K CC10 1 1U_0402_16V7K 1U_0402_16V7K PCIE_DTX_ARX_P0 PCIE_DTX_ARX_N0 CLK_PCIE_CR CLK_PCIE_CR# 23 APU_PCIE_RST# 24 CR_CLKREQ# +3VS RC8 19 SD_GPIO1 10K_0402_5% HSIP HSIN HSOP HSON SP1 SP2 SP3 SP4 SP5 SP6 12 13 14 16 17 18 EMI RC9 EMIP@ 33_0402_5% REFCLKP REFCLKN PERST# SD_WP CLK_REQ# SD_CD# GPIO MS_INS# 20 SD_WP 21 SD_CD# SD_CLK C EMIU@ CC13 5.6P 50V D NPO 0402 EMI 22 RTS5229-GR_QFN24_4X4 +Card_3V3 JSD1 SD_D1 SD_D2 SD_D3 SD_CLK SD_CMD D0 VDD B D1 D2 D3 CLK CMD WP CD VSS1 VSS2 Shading Shading 10 SD_WP 11 SD_CD# 12 13 CC11 CC12 1U_0402_16V7K SD_D0 4.7U_0603_6.3V6K B TAITW_PSDBTC-09GLBS1N14H0 ME@ SP07000LN00 A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/03 Deciphered Date 2015/03/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Card Reader RTS5229 Size C Date: Document Number Rev 1.0 LA-B291P Monday, March 03, 2014 Sheet 31 of 46 A B +5VALW TO +5VS +3VALW TO +3VS Load switch C D E VIN 5V and 3.3V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm +3VALW VIN 1.8V and 0.95V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm +3VS SUSP# VL SUSP# +5VALW ON1 CT1 VBIAS GND ON2 CT2 VIN2 VIN2 VOUT2 VOUT2 GPAD 14 13 12 @ +3VS_LS C9 330P_0402_50V7K C10 180P_0402_50V8J 2 PAD-OPEN 4x4m C12 VOUT1 VOUT1 11 10 +5VS J5 15 PAD-OPEN 4x4m C11 1U_0402_6.3V6K +1.8VALW SUSP# VL 095VS_PWR_EN 095VS_PWR_EN +0.95VALW VOUT1 VOUT1 ON1 CT1 VBIAS GND ON2 CT2 VIN2 VIN2 VOUT2 VOUT2 GPAD 14 13 12 +1.8VS_LS C21 180P_0402_50V8J @ PAD-OPEN 4x4m C24 VIN1 VIN1 11 10 C15 330P_0402_50V7K @ J95V @ +0.95VS_LS 15 +0.95VS 2 PAD-OPEN 4x4m C22 C25 0.1U_0402_16V7K 1U_0402_6.3V6K APE8990GN3B DFN 14P @ C26 0.1U_0402_16V7K +1.35V +1.5VS discharge circuit only for Beema +0.675VS only 1.5VS from PWR R1627 470_0603_5% @ D S only for Beema R1629 470_0603_5% @ 2 +1.5VS +1.8VS J18V @ U1895P @ VIN 1.8V and 0.95V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm 1U_0402_6.3V6K +1.8VALW TO +1.8VS +0.95VALW TO +0.95VS Load switch D SYSON# G Q25 2N7002H_SOT23-3 @ SUSP G Q21 2N7002H_SOT23-3 @ S C14 0.1U_0402_16V7K 1 @ +5VS_LS APE8990GN3B DFN 14P @ C13 0.1U_0402_16V7K @ J4 VIN1 VIN1 1U_0402_6.3V6K U13 3 R1461 220_0603_5% +3VLP D +5VALW R1639 100K_0402_5% OUT SYSON SYSON @ IN R239 100K_0402_5% Q24 DTC124EKAT146_SC59-3 @ 2 @ IN GND SUSP# SUSP# SYSON# DTC124EKAT146_SC59-3 OUT @ Q101 @ R1638 100K_0402_5% SUSP GND @ R1636 100K_0402_5% S SUSP G Q23 2N7002H_SOT23-3 @ @ 4 2014/03/03 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2015/03/03 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D DC Interface Document Number Rev 1.0 LA-B291P Sheet Monday, March 03, 2014 E 32 of 46 EMI@ PL101 HCB2012KF-121T50_0805 @ PR101 PQ101A 0_0402_5% 2N7002KDW-2N_SOT363-6 PR102 750_0402_1% 2 EMI@ PC104 1000P_0402_50V7K D EMI@ PL102 HCB2012KF-121T50_0805 2 ACES_88299-0510 CONN@ VIN EMI@ PC103 100P_0402_50V8J PF101 7A_24VDC_429007.WRML APDIN1 APDIN 2 EMI@ PC102 100P_0402_50V8J EMI@ PC101 1000P_0402_50V7K JDCIN1 ADP_ID AC Adapter 90W 65W R(K ohm) open 10 ADP_ID(V) 3.3 1.65 Detection voltage >2.64 1.32~1.98 D PR104 100K_0402_5% +CHGRTC PR105 1K_0603_5% C +RTCBATT_3V PD101 S SCH DIO BAS40CW SOT-323 PC106 680P_0603_50V7K PQ101B 2N7002KDW-2N_SOT363-6 PR103 100K_0402_5% VIN 2 +3VALW PC105 0.1U_0402_16V7K ADP_ID A/D ADP_ID_CLOSE +3VLP +CHGRTC_R JBATT1 PR106 1K_0603_5% + C - LOTES_AAA-BAT-019-K01 CONN@ RTC Battery B B A A Compal Secret Data Security Classification Issued Date 2014/03/03 2015/03/03 Deciphered Date Title Compal Electronics, Inc Power Map THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev 1.0 LA-B291P Monday, March 03, 2014 Sheet 33 of 46 VL PR225 OTP@ OTP@ PR230 OTP@ PR229 OTP@ PR233 OTP@ 2 VGA 0.1U_0603_25V7K OT1 PTC_PROTECT OTP@ 1.8V 1K_0402_50% 1K_0402_50% 1K_0402_50% 1K_0402_50% CPU MOS_OTP OTP@ VCC TMSNS1 GND RHYST1 OT1 TMSNS2 OT2 RHYST2 OTP@ OTP@ TMSNS1 OTP@ OTP@ PQ202 2N7002KW_SOT323-3 D PTC_PROTECT2 G S TMSNS2 MOS_OTP: Default:High Active :Low PTC_PROTECT: Default:Low Active :High G718TM1U_SOT23-8 OTP@ OTP@ +3VALW PH201 under CPU botten side : CPU thermal protection at 93 +-3 degree C Recovery at 56 +-3 degree C VCIN1_BATT_TEMP A/D 20120314 Change to +EC_VCCA from +3VLP +EC_VCCA PR215 16.5K_0402_1% 2 PR221 100K_0402_1% ECAGND D S G PQ203 2N7002KW_SOT323-3 +3VLP 1.5M_0402_5% PH201 100K_0402_1%_TSM0B104F4251RZ PQ201B 2N7002KDW-2N_SOT363-6 B 1 1N4148WS-7-F_SOD323-2 2 PD201 O PU202A AS393MTR-E1 SO 8P OP PR226 PC206 100P_0402_50V8J P - BATT_OUT PQ201A 2N7002KDW-2N_SOT363-6 C VCIN0_PH1 VCIN1_ADP_PROCHOT PR223 75K_0402_1% 100K_0402_1% PC205 0.068U_0402_16V7K + G 1 VCIN1_BATT_TEMP 100K_0402_1% PR219 PR220 47K_0402_1% @ 2 PR218 PR217 30K_0402_1% VCOUT1_PROCHOT# +3VALW 1 ADP_I PR216 10K_0402_1% PR231 0_0402_5% @ PR222 75K_0402_1% PR209 100K_0402_1% OTP@ 1.5V +5VALW 0.01U_0402_25V7K 2 316K_0402_1% VL PC204 TMSNS21 +3VLP VL 32 PR224 0_0402_5% @ PR227 100K_0402_1% 12/23 improve DC mode S5 power consumtpion C PR207 1K_0402_50% 1K_0402_50% 1K_0402_50% GND 10 12 14 16 18 20 22 24 26 28 30 PR206 D OTP@ PU201 GND 10 12 14 16 18 20 22 24 26 28 30 31 11 13 15 17 19 21 23 25 27 29 11 13 15 17 19 21 23 25 27 29 PR212 16.49K_0402_1% PR213 @ 6.49K_0402_1% PR214 10K_0402_5% EC_SMB_DA1 Charger PC202 EMI@ 0.01U_0402_25V7K OTP@ PC203 EC_SMB_CK1 PR205 1K_0402_50% 0.95V 1K_0402_50% CONN@ JBAT3 3V PR204 OTP@ PR234 PR210 0_0402_5% PC201 EMI@ 1000P_0402_50V7K 5V PR203 1K_0402_5% 2 PR211 100_0402_1% ALLTO_C144PF-K07H9-L +3VLP 1.35V VL EMI@ PL202 HCB2012KF-121T50_0805 P/N:SP040006C00 SP040006A00 SP040006B00 Posestor PR202 EC_SMCA EC_SMDA PR201 100_0402_1% D Reserve BATT+ 2 GND GND 1 VMB PF201 12A_32VDC_0501012WR 12/23 PF201 change to 1206 SIZE VMB2 CONN@ JBAT1 PR202 pop 1k ohm EMI@ PL201 HCB2012KF-121T50_0805 PR208 100K_0402_1% B PR228 ADP_65 ECAGND BATT_LEN# D 100K_0402_1% S G PQ205 2N7002KW_SOT323-3 135W: 150W active and 135W recovery 90W : 120W active and 90W recovery 65W : 85W active and 65W recovery 45W : 65W active and 45W recovery A A Compal Secret Data Security Classification Issued Date 2014/03/03 2015/03/03 Deciphered Date Title Compal Electronics, Inc PWR- BATTERY CONN/OTP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev 1.0 LA-B291P Monday, March 03, 2014 Sheet 34 of 46 SH00000MW00 2 2ACOFF-1 PD302 PR306 200K_0402_1% PD303 1SS355_UMD2-2 2 PD301 REGN 16 PC315 0.047U_0603_16V7K 1 RB751V-40_SOD323-2 PC319 1U_0603_16V7 BQ24737VDD SRP BATT+ SRN DL_CHG PC321 1 PR318 2.2_0603_5% BST_CHG 16251_SN 17 2CHG @EMI@ PR319 4.7_1206_5% DH_CHG 18 PQ312 MDV1528URH 1N PDFN33-8 BTST LODRV ILIM @ PR323 10K_0402_5% 4.7UH_ETQP3W4R7WFN_5.5A_20% 0.01_1206_1% HIDRV SA000051W00 SCL 1U_0603_25V6K 19 4.7uH DCR = 35+/- 15% mohm Power Rating = 1W Idc~Isat = 5.5~6 A VACP~VACN spec < 81.28mV PL302 PR314 @EMI@ PC320 680P_0603_50V7K PC311 0.1U_0603_25V7K PQ310 MDV1528URH 1N PDFN33-8 ACN PR310 10_1206_5% 2 ACP CMPOUT BQ24737VCC 0_0402_5% 2PACIN_2 G S B 0.1U_0402_25V6 A @ PC322 0.1U_0402_25V6 Module model information VCIN1_AC_IN PR325 10K_0402_1% PR324 47K_0402_1% PACIN D G S PR327 ACPRN# ACPRN# PQ314 2N7002KW_SOT323-3 BQ24737_V1.mdd for dual layer PR326 10K_0402_1% 1 BQ24737VDD **Design Notes** Maximum Charging current 2.0A Battery discharge power 55W #Register Setting 0X12 bit8 set (default 1) to disable IFAULT HI if add ISN choke 0X12 bit3 set (default 0) to enable turbo boost function 0X12 bit[12:11] set 00 (default 11) to set BAT Depletion Comparator Threshold Falling Threshold = 59.19% of voltage regulation limit (~2.486V/cell) Disable turbo when AC only #Circuit Design Make sure there is pull high for SMB on HW side Use 10X10 choke and 3X3 H/L side MOSFET Charge current 2.0A Power loss : 1.82W Power density : 0.81 (15X15) If use 4S per cell 4.35V battery, need change PR313 to 59K for ACDET setting) For hybrid design, need double check PQ301,PQ302,PQ303,PQ309 component rating #Protect function ACOVP : ACDET voltage > 3.15V Charger timeout : No communication within 175s(default) ACOC : 3.33 X Input current DAC setting(default) CHGOCP : 3/4.5/6A based on current current setting BATOVP : 104% BATLOWV : 2.5V TSHUT : 155C IFAULT HI : 750mV (default) IFAULT LOW : 135mV (default) PC323 0.1U_0402_25V6 +3VALW Battery out function just for C38/A39 only, other customers please remove PQ313,PQ314,PR310,PR326 20 VILIM = 20 X (VSRP - VSRN) = 20 X ICHG X RSR @ PR313 PQ309 2N7002KW _SOT323-3 D C LX_CHG 15 Make sure this pull high Voltage is same with EC VCC PHASE PU301 BQ24727RGRR_VQFN20_3P5X3P5 GND +3VLP 10 21 PC314 14 PR317 316K_0402_1% SDA SRP EC_SMB_CK1 TP VCC 13 PR321 10_0603_5% 1SS355_UMD2-2 PQ306 DTC115EUA_SC70-3 IOUT SRN 100P_0603_50V8 EC_SMB_DA1 CMPIN BM PC313 ACDET 11 PC312 2200P_0402_25V7K ACOK ADP_I 6.8_0603_5% 12 PR322 PR312 59K_0402_1% 0.1U_0402_25V6 B S Rds(on) = 30mohm max Vgs = 20V Vds = 30V ID = 7A (Ta=70C) PC310 2 D G 2N7002KW_SOT323-3 PQ313 BATT_OUT P2 VIN S PR320 100K_0402_1% G ACPRN# BATT_OUT PR316 @ 0_0402_5% 2 10K_0402_1% VIN PQ308 PC316 0.01U_0402_25V7K ACOFF-1 D Make sure there is pull high for SMB on HW side! 1 PR315 2N7002KW_SOT323-3 PQ311 DTC115EUA_SC70-3 AC_OFF PC309 0.1U_0402_25V6 2 PR309 392K_0402_1% PQ307B PR311 47K_0402_1% PACIN P2-2 PACIN_2 2N7002KDW-2N_SOT363-6 PR308 150K_0402_1% PQ307A 2N7002KDW -2N_SOT363-6 C PC308 0.1U_0402_25V6 PR305 47K_0402_1% PR307 20K_0402_1% D PR304 200K_0402_1% ACP CELL: PR312 = 59.0k Typ Worst L => H 18.346V 18.529V H => L 17.925V 17.589V DTC115EUA_SC70-3 DISCHG_G 1DISCHG_G-1 P2-1 PQ305 ACN CELL: PR312 = 64.9k Typ Worst L => H 16.896V 17.065V H => L 16.509V 16.199V 2 @EMI@ PC303 10U_0805_25V6K ACDET V1 PC302 5600P_0402_25V7K PC301 0.1U_0603_25V7K PR303 200K_0402_1% 2 PR301 47K_0402_5% DTA144EUA_SC70-3 PQ303 AO4407AL_SO8 PC318 10U_0805_25V6K PQ304 D 35> AO4407AL Vds=-30V Rds_on=12.7~17mohm@Vgs=-6V ID = 10A (Ta=70C) CHG_B+ EMI@ PL301 1UH_NRS4018T1R0NDGJ_3.2A_30% PC317 10U_0805_25V6K PR302 0.01_1206_1% EMI@ PC307 2200P_0402_50V7K @EMI@ PC306 0.1U_0402_25V6 4 VIN Need EC write ChargeOption() bit[8]=0 to disable iFault_Hi function Isat: 4A DCR: 27mohm Power Rating = 1W VACP~VACN spec < 80.64mV PQ302 AO4455_SO8 PC305 10U_0805_25V6K PQ301 AO4407AL_SO8 2 PC304 10U_0805_25V6K P2 B+ 4 AO4423L Vds=-30V Rds_on=9.4~12mohm@Vgs=-6V P3 ID = 12.1A (Ta=70C) @RF@ PC324 0.022U_0402_25V7K AO4407AL Vds=-30V Rds_on=12.7~17mohm@Vgs=-6V ID = 10A (Ta=70C) 12K_0402_1% A For disable pre-charge circuit 2014/03/03 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2015/03/03 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: PWR- CHARGER_BQ24727 Document Number Rev 1.0 LA-B291P Monday, March 03, 2014 Sheet 35 of 46 A B C D E Module model information SY8208B_V2.mdd 1 EN1 and EN2 dont't floating Change 3V5V_EN to 3VALW_EN PC407 C407 10U_0805_25V6K IN EN1 IN EN2 BS PC403 PR403 0.01U_0402_25V7K 1K_0402_5% 2 3V5V_EN BST_3V 3V_FB PR405 2.2_0603_5% PC404 PL402 3.3V LDO 150mA~300mA PR407 2.2K_0402_5% VCOUT0_MAIN_PWR_ON @ PR408 PC411 22U_0603_6.3V6M 2 +3VALW JUMP_43X118 3V5V_EN PR410 1M_0402_1% +3VALWP B+ TDC=6A @ PJ401 0_0402_5% 0_0402_5% @PR409 @ PR409 MOS_OTP Vout is 3.234V~3.366V PC414 4.7U_0402_6.3V6M EC_ON PC410 22U_0603_6.3V6M 2 +3VLP Check pull up resistor of SPOK at HW side +3VLP PC412 4.7U_0603_6.3V6M +3VALWP LDO @EMI@ PR406 3V_SN PG SY8208BQNC_QFN10_3X3 PR402 100K_0402_1% 2 1.5UH_PCMB053T-1R5MS_6A_20% 680P_0603_50V7K 4.7_1206_5% OUT @EMI@ PC413 GND LX_3V PC409 22U_0603_6.3V6M 10 LX 3V/5VALW_PG B+ 0.1U_0603_25V7K @ @P PC408 22U_0603_6.3V6M PC406 10U_0805_25V6K EMI@ PC405 2200P_0402_50V7K 3V_VIN PR404 150K_0402_1% PU401 EMI@ PL401 HCB2012KF-121T50_0805 @EMI@ PC401 0.1U_0402_25V6 B+ PR401 499K_0402_1% ENLDO_3V5V EN1 and EN2 dont't floating EMI@ PL403 HCB2012KF-121T50_0805 5V_VIN @EMI@ PC420 0.1U_0402_25V6 EN1 EN2 BS 3V5V_EN 5V_FB BST_5V PC415 PR412 6800P_0402_25V7K 1K_0402_5% 2 PR413 2.2_0603_5% TDC=6A PC417 0.1U_0603_25V7K PL404 PC428 22U_0603_6.3V6M PC425 22U_0603_6.3V6M VL PC424 22U_0603_6.3V6M PC423 22U_0603_6.3V6M LDO +5VALWP PG SY8208CQNC_QFN10_3X3 1.5UH_PCMB053T-1R5MS_6A_20% OUT LX_5V PC422 22U_0603_6.3V6M VCC 10 680P_0603_50V7K 4.7_1206_5% LX @EMI@ PC427 @EMI@ PR414 5V_SN GND 1 PC421 4.7U_0603_6.3V6M 5V_VCC Module model information IN PC426 4.7U_0603_6.3V6M @ @P EMI@ PC419 2200P_0402_50V7K PC418 C418 10U_0805_25V6K PC416 10U_0805_25V6K Vout is 4.998V~5.202V PU402 @ PJ402 +5VALWP 1 2 +5VALW JUMP_43X118 5V LDO 150mA~300mA SY8208C_V2.mdd 4 Compal Secret Data Security Classification 2014/03/03 Issued Date 2015/03/03 Deciphered Date Title Compal Electronics, Inc PWR- 3VALW/5VALW-SY8208B/C THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev 1.0 LA-B291P Monday, March 03, 2014 Sheet E 36 of 46 Module model information RT8207M_V1.mdd RT8207M_V2.mdd For Single layer For Dual layer D D PR501 2.2_0603_5% BOOT_1.35V +0.675VSP PAD VTTGND Change CS R to your estimation value CS 12 VDDP VTTREF +0.75VSP off off on VTTREF_1.5V off on on 2 +VTTREFP +1.35VP FB PC509 0.033U_0402_16V7K FB_1.35V S3 PR506 8.2K_0402_1% +1.35VP B Change FB Rtop to 8.2K for 1.35V EN_0.675VSP TON L/S Rds(on): 9.7mohm(Typ), 11.6mohm(Max) Idsm: 15.4A@Ta=25C, 12.4A@Ta=70C SYSON PR508 10K_0402_1% @ PR509 2 Level L L H 0_0402_5% @ PC514 0.1U_0402_10V7K Choke: 7x7x3 Rdc=8.3mohm(Typ), 10mohm(Max) Mode S5 S3 S0 C Co-Lay MOSFET: 3x3 DFN H/S Rds(on): 23.2mohm(Typ), 27.8mohm(Max) Idsm: 10.1A@Ta=25C, 8.1A@Ta=70C B PR507 887K_0402_1% 1.35V_B+ EN_1.35V +5VALW 10 PC512 1U_0603_10V6K VDDQ S5 VDD TON_1.35V 11 GND RT8207MZQW _W QFN20_3X3 VDD_1.35V 13 VTTSNS PGOOD +5VALW @EMI@ PC513 680P_0402_50V7K PQ502 MDV1524_DFN8-5 PR504 5.1_0603_5% PGND 2 + @EMI@ PR503 4.7_1206_5% ESR=9m ohm ESR=15m ohm PC510 330U_6.3V_M 1 PR502 13.7K_0402_1% CS_1.35V PC508 1U_0603_10V6K 21 14 PL502 1UH_VMPI0703AR-1R0M-Z01_11A_20% PC506 10U_0805_6.3V6K 20 VTT PU501 LGATE 19 18 15 MDV1528URH 1N PDFN33-8 VLDOIN DL_1.35V BOOT PHASE PQ501 17 16 SW _1.35V PC505 0.1U_0603_25V7K PC507 10U_0805_6.3V6K DH_1.35V C +1.35VP 0.675Volt +/- 5% TDC 0.7A Peak Current 1A +1.35VP UGATE BST_1.35V PC504 10U_0805_25V6K PC503 10U_0805_25V6K EMI@ PC502 2200P_0402_50V7K 1.35V_B+ @EMI@ PC501 0.1U_0402_25V6 B+ Pin19 need pull separate from +1.35VP If you have +1.35V and +0.675V sequence question, you can change from +1.35VP to +1.35VS EMI@ PL501 HCB2012KF-121T50_0805 Note: S3 - sleep ; S5 - power off Switching Frequency: 285kHz Ipeak=10A Iocp~13A OVP: 110%~120% MOSFET footprint: SIS412DN PR510 0_0402_5% @ PJ501 +1.35VP 2 +1.35V JUMP_43X118 @ PJ502 2 SUSP# @ PC515 0.1U_0402_10V7K JUMP_43X118 PJ503 @ +0.675VSP 2 +0.675VS JUMP_43X39 A Compal Secret Data Security Classification Issued Date 2014/03/03 Deciphered Date 2015/03/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc PWR-+1.35VP/ +0.675VS Size Document Number Custom Date: A Rev 1.0 LA-B291P Monday, March 03, 2014 Sheet 37 of 46 A B C D Module model information SY8208D_V2.mdd 1 EN pin don't floating If have pull down resistor at HW side, pls delete PR2 PR601 0_0402_5% 095_18ALW_PWR_EN 3V/5VALW_PG 1 @ PR610 0_0402_5% +0.95VALW P @ PC601 0.22U_0402_10V6K PJ601 2 JUMP_43X118 +0.95VALW @ 2 1M_0402_1% PR602 @EMI@ PR603 @EMI@ PC602 4.7_1206_5% 680P_0603_50V7K 2SNB_0.95V1 2 2 PC612 22U_0603_6.3V6M FB = 0.6V PR609 Rdown 20K_0402_1% 2 +3VALW SY8208DQNC_QFN10_3X3 PR608 @ 0_0402_5% PC614 4.7U_0603_6.3V6K 0.95LDO_3V PC611 22U_0603_6.3V6M Rup FB ILMT_0.95V3 +0.95VALWP LDO TDC 8A PL602 1UH_11A_20%_7X7X3_M PC610 47U_0805_6.3V6M PG LX_0.95V BYP PC606 0.1U_0603_25V7K 2 ILMT 10 PR604 0_0603_5% PC609 47U_0805_6.3V6M LX BST_0.95V GND BS PC608 330P_0402_50V7K EN PR606 11.8K_0402_1% IN PC613 4.7U_0603_6.3V6K 10U_0805_25V6K PC605 ILMT_0.95V PR605 @ 0_0402_5% B+_0.95V 10U_0805_25V6K PC607 1 0.95LDO_3V PU601 @EMI@ PC604 0.1U_0402_25V6 EMI@ PC603 2200P_0402_50V7K B+ EMI@ PL601 HCB2012KF-121T50_0805 Pin BYP is for CS Common NB can delete The current limit is set to 8A, 12A or 16A when this pin is pull low, floating or pull high +3VALW and PC15 VFB=0.6V Vout=0.6V* (1+Rup/Rdown) 3 Vout=0.95V 4 Compal Secret Data Security Classification Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title Compal Electronics, Inc PWR- +0.95VALW THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C Rev 1.0 LA-B291P Monday, March 03, 2014 D Sheet 38 of 46 A B C D Module model information SY8003_V2.mdd 1 PR701 0_0402_5% 0.1U_0402_16V7K PC701 2 FB_1.8V FB=0.6V Note:Iload(max)=3A PR706 10K_0402_1% Rup @ 2 +1.8VALW PC705 22U_0603_6.3V6M PR705 20K_0402_1% SY8003DFC_DFN8_2X2 PJ701 1 +1.8VALWP JUMP_43X79 +1.8VALWP NC 1UH_2.8A_30%_4X4X2_F PC704 22U_0603_6.3V6M PGND PL701 LX_1.8V PC703 68P_0402_50V8J 2 22U_0603_6.3V6M LX PC702 IN Note:Iload(max)=2.5A JUMP_43X79 EN Rdown 2 1 PGND SGND PG @EMI@ PC706 680P_0402_50V7K 1 +3VALW FB @EMI@ PR704 4.7_0603_5% @ PJ702 3V/5VALW_PG PR703 1M_0402_5% @ PU701 095_18ALW_PWR_EN @ PR712 0_0402_5% +1.8VSP_ON Note: When design Vin=5V, please stuff snubber to prevent Vin damage Vout=0.6V* (1+Rup/Rdown) +3VS +5VALW 3 2 JUMP_43X79 @ PJ703 1 Ultra Low Dropout 0.23V(typical) at 3A Output Current PC707 1U_0402_6.3V6K Module model information Rdown APL5930_V2.mdd @ +1.5VSP PJ704 2 +1.5VS JUMP_43X79 PC711 22U_0603_6.3V6M Rup PC710 0.01U_0402_25V7K PR709 1.54K_0402_1% FB EN POK @ PR708 100K_0402_5% +1.5VSP PR711 1.74K_0402_1% GND +3VS PC709 0.1U_0402_16V7K 2 PR710 47K_0402_5% SUSP# PR707 100K_0402_5% 1 PU702 APL5930KAI-TRG_SO8 VCNTL VOUT VIN VIN VOUT PC708 4.7U_0603_6.3V6K 4 Vout=0.8V* (1+Rup/Rdown) Compal Secret Data Security Classification Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title Compal Electronics, Inc PWR- +1.8VALW/ +1.5VS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C Rev 1.0 LA-B291P Monday, March 03, 2014 D Sheet 39 of 46 @ PR801 UGATE_NB1 PR804 1.33K_0402_1% 10_0402_5% PC808 100P_0402_50V8J PHASE_NB1 BOOT_NB1 PR814 set 390 ohm to OCP 19A 2 @PC815 @ PC815 220P_0402_50V7K @ PR816 100_0402_1% LGATE_NB1 PC801 33U_25V_M +APU_CORE_NB @EMI@ PR811 4.7_1206_5% D PR813 3.65K_0402_1% VSUMP_NB @EMI@ PC813 PR815 1_0402_1% VSUMN_NB APU_CORE_NB TDC 13A Peak Current 17A OCP current 21.49A Load line -4mV/A FSW=300kHz +APU_CORE_NB +5VALW @ PR829 PR831 2.2_0603_1% BOOT11 1 + 2 + @ @ PC857 PC858 PC859 PC860 PC861 PC862 PC863 PC864 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M @ @ @ 2014/03/03 @ A Compal Secret Data Security Classification Issued Date @ 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M PC853 PC854 PC855 PC856 @ 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M @ PC868 1 PC850 PC851 PC852 10U_0603 * 0.01U_0402_25V7K~N @ @ B Power Dissipation: H/S 0.720W L/S 0.876W +APU_CORE_NB PC867 A + 10U_0603 *3 +APU_CORE 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 0_0402_5% @ PR846 PR847 10_0402_5% PC846 PC847 PC848 PC849 APU_VDD_RUN_FB_L PC840 330U_D2_2V_Y +APU_CORE APU_VDD_SEN +APU_CORE APU_core TDC 15A Peak Current 21A OCP current 26.32A Load line -4mV/A FSW=300kHz +APU_CORE PC865 2 PC841 0.01U_0402_50V7K MDU1511RH_POWERDFN56-8-5 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M PR1046 set 536 ohm to OCP 26.32A PC835 330P_0402_50V7K PR839 1_0402_1% VSUM- 0.1U_0402_25V7K~N @ PR845 0_0402_5% LGATE1 @EMI@ PC830 680P_0603_50V7K PC839 330U_D2_2V_Y PR843 10_0402_5% @ PC837 @ PR844 820P_0402_50V7K 100_0402_1% 2 PR1039=3.65K, PR1040=1.58K and PR1046=453 to set loadline -4mV/A while PR1013=453 to set OCP 22.54A for EDC 18A application PR841 2K_0402_1% PQ804 PR835 3.65K_0402_1% VSUM+ 0.01U_0402_25V7K~N PC836 0.1U_0603_50V7K PR838 PC832 137K_0402_1% 390P_0402_50V7K 2 PC842 PC843 PC844 PC845 PR842 536_0402_1% @ PR834 32.4K_0402_1% 2 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 330P_0402_50V7K @ PC831 PC834 0.15U_0603_16V7K PC833 0.01U_0402_50V7K 1 PR840 11K_0402_1% PR1039=3.65K, PR1040=1.87K and PR1046=536 to set loadline -4mV/A PC866 2 @ PR837 1.87K_0402_1% @EMI@ PR832 4.7_1206_5% PC828 PR833 1000P_0402_50V7K 301_0402_1% 2 PC827 0.22U_0603_25V7K PC829 100P_0402_50V8J SH00000NX00 (DCR:1.4± 5%) PL803 36UH 20% PDME064T-R36MS1R405 24A ISEN1 0.1U_0402_25V7K~N PR830 10K_0402_1% VSUM- PHASE1 PH804 10K_0402_5%_ERTJ0ER103J 2 PR836 2.61K_0402_1% B +5VS VSUM+ PH1003 near APU_CORE_NB choke 0_0402_5% UGATE1 VGATE EMI@ PC826 0.1U_0402_25V6K PR826 100K_0402_1% @EMI@ PC825 2200P_0402_50V7K PGOOD +3VS PC838 330U_D2_2V_Y BOOT1 PC824 10U_0805_25V6K 21 C CPU_B+ PC823 10U_0805_25V6K UGATE1 PQ803 MDU1516URH_POWERDFN56-8-5 22 PHASE1 LGATE1 23 1 1_0603_5% 24 25 PC821 1U_0603_10V6K PR822 PH803 470K_0402_5%_TSM0B474J4702RE Power Dissipation: H/S 0.5811W L/S 0.6756W 26 PH1002 near APU_CORE H/S mos VRHOT Assert Threshold : 0.64V TSENSE Bias Current : 30uA PH1002=27.4K, 110C active Reset Threshold: 0.66V, 98C active 110C Assert Threshold: PR1031=27.4K 100C Assert Threshold: PR1031=16.9K + PC818 330U_D2_2V_Y PC816 330U_D2_2V_Y ISL62771_V1B.mdd for SW portion 29 27 20 PR827 10.5K_0402_1% + 28 PC820 1U_0603_10V6K 32 33 31 BOOT_NB UGATE_NB 34 LGATE_NB PHASE_NB 36 37 35 PGOOD_NB COMP_NB 38 BOOT1 30 ISL62771_V1A.mdd for IC portion FB_NB UGATE1 IMON PC822 1000P_0402_50V7K PR828 27.4K_0402_1% VSEN_NB 40 39 PWROK APU_IMON COMP 10 IMON PHASE1 FB ENABLE RTN PR825 133K_0402_1% LGATE1 19 SVC, SVD, SVT, ENABLE and PWROK no need pull high for AMD KABINI VDD SVT 18 1.8VS for DDRII voltage level APU_PWRGD 1.5VS for DDRIII voltage level VDDIO 17 VR_ON ENABLE VSEN @ PR824 0_0402_5% NTC VDDIO pin: 0_0402_5% PC819 0.1U_0402_25V6K 16 VDDIO 1PR823 VDDP ISL62771HRTZ-T_TQFN40_5X5 ISUMN APU_SVT @ PR821 0_0402_5% @ LGATE2 SVD 11 +1.5VS VR_HOT_L ISUMP ISEN1 APU_SVD PHASE2 15 BOOT2 UGATE2 SVC 12 100K_0402_1% 2 C PL802 36UH 20% PDME064T-R36MS1R405 24A Module model information IMON_NB 14 NTC_NB 13 APU_SVC +1.8VS IMON_NB ISEN2 ISUMN_NB PU801 41 TP PH802 470K_0402_5%_TSM0B474J4702RE PH1001 near APU_CORE_NB H/S mos @ PR820 B+ BOOT_NB1 PR817 10.5K_0402_1% 2 ISUMP_NB PR818 27.4K_0402_1% PC817 1000P_0402_50V7K PROCHOT# + UGATE_NB1 133K_0402_1% +3VS PHASE_NB1 VRHOT Assert Threshold : 0.64V TSENSE Bias Current : 30uA PH1001=27.4K, 110C active Reset Threshold: 0.66V, 98C active 110C Assert Threshold: PR1016=27.4K 100C Assert Threshold: PR1016=16.9K LGATE_NB1 PR814 390_0402_1% 0.1U_0603_50V7K PR1012=3.65K, PR1003=1.33K and PR1013=374 to set loadline -4mV/A while PR1013=374 to set OCP 18.8A for EDC 15A application + SH00000NX00 (DCR:1.4± 5%) PR810 PC809 2.2_0603_1% 0.22U_0603_25V7K 2 PQ802 PC812 0.15U_0603_16V7K @ PC811 0.022U_0402_25V7K 2 PR812 11K_0402_1% PH801 10K_0402_5%_ERTJ0ER103J 2 PR809 2.61K_0402_1% PC814 1 PH1000 near APU_CORE_NB choke PR819 PC807 0_0402_5% 1000P_0402_50V7K 2 PR808 PC810 301_0402_1% 0.01U_0402_50V7K VSUMP_NB VSUMN_NB 0_0402_5% MDU1511RH 1N POWERDFN56-8 @ PR807 D +APU_CORE_NB @ PR806 PR805 PC806 137K_0402_1% 390P_0402_50V7K 41.2K_0402_1% 2 680P_0603_50V7K 2 PR802 2K_0402_1% PR803 APU_VDDNB_SEN PC802 33U_25V_M PR1012=3.65K, PR1003=1.5K and PR1013=432 to set loadline -4mV/A EMI@ PL801 HCB2012KF-121T50_0805 PC804 10U_0805_25V6K PQ801 MDU1516URH_POWERDFN56-8-5 PC805 330P_0402_50V7K PC803 10U_0805_25V6K CPU_B+ Deciphered Date 2015/03/03 Title Compal Electronics, Inc PWR- APU_CORE/APU_CORE_NB THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev 1.0 LA-B291P Monday, March 03, 2014 Sheet 40 of 46 +VGA_CORE AMD JET LE TDC 20A EDC 30A GPU_B+ Module model information EMI@ PL901 HCB2012KF-121T50_0805 ISL62771_V1A.mdd for IC portion PQ901 @ PR904 UGATE1 0_0402_5% G2 S1/D2 S2 G1 S2 D1 S2 PC906 0.22U_0603_25V7K B+ PC905 10U_0805_25V6K PR905 2.2_0603_1% BOOT11 PC904 10U_0805_25V6K @EMI@ PC902 0.1U_0402_25V6 PHASE1 D EMI@ PC903 2200P_0402_50V7K LGATE1 ISL62771_V1B.mdd for SW portion D PR902 LGATE_NB1 28 PHASE2 27 LGATE2 VSUM+ PR908 3.65K_0603_1% VSUM- PR910 1_0402_1% +5VALW PC909 330U_D2_2V_Y PC908 330U_D2_2V_Y PC907 390U_2.5V_M + PHASE2 PR928 2.2_0603_1% BOOT21 PC922 0.22U_0603_25V7K PQ902 PGOOD +3VS 0_0402_5% PR921 UGATE2 25W@ 25W@ PR917 100K_0402_1% G2 S1/D2 S2 G1 S2 D1 S2 @EMI@ @EMI@ BOOT1 21 C GPU_B+ LGATE2 25W@ 25W@ AON6932A_DFN5X6-8-7 25W@ +VGA_CORE @ PR923 32.4K_0402_1% PR925 PC923 137K_0402_1% 390P_0402_50V7K 2 PC926 330P_0402_50V7K 2 PR930 2K_0402_1% +VGA_CORE ISEN1 25W@ B Power Dissipation: H/S 0.720W L/S 0.876W PC944 2.2U_0402_6.3V6M PC945 2.2U_0402_6.3V6M PC959 0.1U_0402_10V7K PC960 0.1U_0402_10V7K PC946 2.2U_0402_6.3V6M PC943 2.2U_0402_6.3V6M PC958 0.1U_0402_10V7K PC942 2.2U_0402_6.3V6M PC957 1U_0402_6.3V6K PC941 2.2U_0402_6.3V6M PC937 2.2U_0402_6.3V6M PC953 10U_0603_6.3V6M PC940 2.2U_0402_6.3V6M PC936 2.2U_0402_6.3V6M PC952 10U_0603_6.3V6M 2 PC956 1U_0402_6.3V6K PC935 2.2U_0402_6.3V6M PC951 10U_0603_6.3V6M 15W@ PC925 0.1U_0603_25V7K PC939 2.2U_0402_6.3V6M PC934 2.2U_0402_6.3V6M PC950 10U_0603_6.3V6M GPU_VDD_RUN_FB_L 15W@ PR924 1K_0402_1% 25W@ PC933 2.2U_0402_6.3V6M GPU_VDD_SEN PC932 2.2U_0402_6.3V6M @ PR933 0_0402_5% @ PR935 0_0402_5% PR936 10_0402_5% 15W@ PR931 536_0402_1% PR931=536 ohm, PR924=1K ohm, PC925=0.1uF, PR944 =0 ohm, PR920=10K ohm, PC961 @, PC962 @, PR938 @ and PR939 @ while PR931=536 ohm to set OCP for GPU 15W application PR943 10K_0402_1% PR941 1_0402_1% 25W@ VSUM- 2 GPU 15W setting 25W@ PC927 @EMI@ 680P_0603_50V7K PC949 10U_0603_6.3V6M 1 PR940 10K_0402_1% PR942 3.65K_0603_1% 25W@ VSUM+ PC948 10U_0603_6.3V6M @ PC929 @ PR934 820P_0402_50V7K 100_0402_1% 2 ISEN2 +VGA_CORE PR932 10_0402_5% PR929 @EMI@ 4.7_1206_5% PC931 2.2U_0402_6.3V6M 25W@PR931 332_0402_1% PL903 0.22UH_PCME064T-R22MS_28A_20% 2 330P_0402_50V7K @ PC921 25W@PR924 1.54K_0402_1% 1 PC920 100P_0402_50V8J PC919 PR922 1000P_0402_50V7K 301_0402_1% 2 PC947 10U_0603_6.3V6M 1 PC925 0.15U_0603_16V7K PC924 0.047U_0402_25V7K 1 PR927 11K_0402_1% PC928 0.1U_0603_50V7K PC918 10U_0805_25V6K UGATE1 PC917 10U_0805_25V6K 22 PHASE1 LGATE1 23 25W@ PC930 0.01U_0402_50V7K VSUM- PH902 10K_0402_5%_ERTJ0ER103J 2 PR926 2.61K_0402_1% B + 1/7 change to H=6 CAP_SF000002O00 PC916 2200P_0402_50V7K 1 1_0603_5% 24 25 25W@ 25W@ PR913 ISEN1 ISEN2 25W@ VSUM- + 26 DGPU_PWROK PC962 0.22U_0402_10V6K 15W VSUM+ ISEN2 PC911 @EMI@ 680P_0603_50V7K 25W 10K_0402_1% 15W@ PC961 0.22U_0402_10V6K 2 PR944 15W@ +5VS VRHOT Assert Threshold : 0.64V TSENSE Bias Current : 30uA PH1002=27.4K, 110C active Reset Threshold: 0.66V, 98C active 110C Assert Threshold: PR1031=27.4K 100C Assert Threshold: PR1031=16.9K 0_0402_5% PR920 2 PH901 470K_0402_5%_TSM0B474J4702RE + 25W@PR939 25W@ PR939 10K_0402_1% PC910 390U_2.5V_M 25W@PR938 25W@ PR938 10K_0402_1% ISEN1 UGATE2 BOOT2 29 20 RTN COMP 19 18 17 PR918 10.5K_0402_1% FB BOOT1 30 PC913 1U_0603_10V6K UGATE1 IMON PR907 @EMI@ 4.7_1206_5% PHASE1 PWROK +5VALW PC912 1U_0603_10V6K 32 33 31 BOOT_NB UGATE_NB 34 LGATE_NB PHASE_NB ENABLE PL902 0.22UH_PCME064T-R22MS_28A_20% PC915 0.1U_0402_25V6 2 36 37 38 35 PGOOD_NB COMP_NB FB_NB LGATE1 PC914 1000P_0402_50V7K PR919 27.4K_0402_1% VSEN_NB 40 39 VDD SVT NTC VDDIO VSEN 10 IMON PR916 133K_0402_1% VDDP ISL62771HRTZ-T_TQFN40_5X5 16 0_0402_5% SVD 11 DGPU_PWROK ENABLE LGATE2 12 @ PR915 0_0402_5% @ PR937 PHASE2 VR_HOT_L ISUMN VDDIO 0_0402_5% GPU_SVT PC901 GPU_PWR_EN 0.1U_0402_25V6K SVC ISUMP ISEN1 BOOT2 UGATE2 15 1_0402_5% IMON_NB 14 GPU_SVC NTC_NB 13 ISUMN_NB 100K_0402_1% IMON_NB ISEN2 100K_0402_1% PR909 GPU_SVD SVC, SVD, SVT, ENABLE and PWROK no need pull high for AMD KABINI 41 TP PR901 @PR914 ISUMP_NB PU901 GPU_PROCHOT# @ PR911 100K_0402_1% +3VS @ PR912 20_0402_5% +1.8VGS +1.5VS +VGA_CORE PR906 C PR903 10K_0402_1% UGATE_NB1 BOOT_NB12 SH00000NX00 (DCR:1.4± 5%) 10K_0402_1% PHASE_NB1 PC955 1U_0402_6.3V6K VRHOT Assert Threshold : 0.64V TSENSE Bias Current : 30uA PH1001=27.4K, 110C active Reset Threshold: 0.66V, 98C active 110C Assert Threshold: PR1016=27.4K 100C Assert Threshold: PR1016=16.9K PR945 41.2K_0402_1% PC938 2.2U_0402_6.3V6M Fsw=400K Hz @ PR947 0_0402_5% PC954 1U_0402_6.3V6K @ PR946 0_0402_5% AON6932A_DFN5X6-8-7 A A Compal Secret Data Security Classification Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title Compal Electronics, Inc PWR- +VGA_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev 1.0 LA-B291P Monday, March 03, 2014 Sheet 41 of 46 A B C B+ D E +3VLP EC_ON +EC_VCCA PU401 SY8208BQNC +3VALW +3V_LAN 1 SUSP# U13 APE8990GN3B +3VS 3VGS_PWR_EN QV16 LP2301ALT1G +3VGS SUSP# PU702 APL5930KAI +1.5VS 095_18ALW_PWR_EN PU701 +1.8VALW SUSP# U1895P APE8990GN3B +1.8VS 2 GPU_PWR_EN U1895V APE8990GN3B +1.8VGS EC_ON +VL PU402 SY8208CQNC +5VALW SUSP# U13 APE8990GN3B +5VS SUSP# / SYSON +0.675VS PU501 RT8207MZQW +1.35V GPU_PWR_EN# UV3 AP4800BGM-HF +1.35VGS 095_18ALW_PWR_EN PU601 SY8208DQNC +0.95VALW 095VS_PWR_EN U1895P APE8990GN3B +0.95VS GPU_PWR_EN U1895V APE8990GN3B +0.95VGS GPU_PWR_EN PU901 ISL62771HRTZ-T +VGA_CORE VR_ON +APU_CORE PU801 ISL62771HRTZ-T +APU_CORE_NB 4 Compal Secret Data Security Classification 2014/03/03 Issued Date 2015/03/03 Deciphered Date Title Compal Electronics, Inc PWR DCIN / RTC Battery THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev 1.0 LA-B291P Sheet Monday, March 03, 2014 E 42 of 46 B+ +3VS / +1.8VS / +1.5VS / +0.95VS +3VALW +APU_CORE / +APU_CORE_NB V V 3B SYS_PWRGD_EC 17 LPC_RST# 19 V DGPU_PWR_EN 13 GPU_PWR_EN 12 +5VS / +3VS / +1.8VS 095VS_PWR_EN +3VALW +3VALW +5VALW V V V UV14 +1.35VGS +3VALW V +5VALW +0.95VALW +5VALW B+ PU501 +0.675VS V 21 QV16 +3VGS +1.5V +5VALW U1895P +1.8VS Issued Date U1895V +0.95VGS U1895P +0.95VS A Compal Secret Data Security Classification COMPAL CONFIDENTIAL LAN B +1.8VALW +5VALW +1.5V MODEL NAME: PCB NAME: REVISION: DATE: 2014/03/03 +5VS +3VS +3VS +5VALW +0.95VALW +5VALW U13 +5VS V V U13 +3VS PU702 +1.5VS A WLAN / WiMAX NGFF WLAN/BT Card +3V_LAN V BATT+ PU301 B+ PU102 +RTCBATT +1.8VALW +5VALW B+ PU501 +1.35V 11 +1.5VA PU901 +VGA_CORE V +5VALW VIN VGA_PEWGD +3VS +5VALW V +CHGRTC_R +3VLP 14 GPU Jet LE S3 C U1895V +1.8VGS SUSP# VGATE RTC Battery +CHGRTC_R B APU_PWRGD GPU_RST# 16 SYSON PU801 +APU_CORE / +APU_CORE_NB 23 AND GATE V V 15 V VR_ON 18 V BATT MODE BATT+ APU_PCIE_RST# B+ 18 APU_PWRGD 20 B+ V V V V V ON/OFF PXS_RST# V EC_ON 1B AC MODE VIN 10 V 2B ACIN +5VALW 22 3B C 4A APU KBRST# V 1A SLP_S3# / SLP_S5# D SPOK PU401 +3VALW/+3VLP 2A +VGA_CORE +3VGS V 3A PU402 +5VALW / VL PBTN_OUT# +1.8VGS / +0.95VGS V V 4A B+ V V V V 095_18ALW_PWR_EN EC_RSMRST# V V EC 3B V V 3A B+ +3VGS / +1.35VGS +RTCBATT PU601 +0.95VALW V V PU502 +1.8VALW +3VALW / +1.8VALW / +1.5VALW / +0.95VALW +3VLP D V +3VALW 2014/03/03 2015/03/03 Deciphered Date Title Compal Electronics, Inc Power Sequence Block THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev 1.0 LA-B291P Monday, March 03, 2014 Sheet 43 of 46 www.s-manuals.com ... EMIP@ EMIP@ RA19 RA 20 RA22 RA23 CA 20 1U _04 02_6.3V6K For Universal Audio Jack 39.2K _04 02_1% SM0 100 107 10 SM0 100 107 10 2 1 2 SM0 100 0FH 00 SM0 100 0FH 00 0 _06 03_5% 0_ 0 603 _5% 47 _04 02_5% 47 _04 02_5% PLUG_IN LINE1-L... 10K _04 02_5% 0_ 0 402 _5% EC_LID_OUT# USB_OC0# USB_OC1# R928 100 K _04 02_5% 100 K _04 02_5% 100 K _04 02_5% @ 10K _04 02_5% @ D13 R685 10K _04 02_5% R925 R656 R6 50 R651 R345 47K _04 02_5% SCS 000 05C 00 10K _04 02_5% R16 50. .. SPK_L2+_CONN 100 0P _04 02_50V7K EMIP@ CA31 APU_SPKR CA23 0_ 0 603 _5% 0_ 0 603 _5% 0_ 0 603 _5% 0_ 0 603 _5% 100 0P _04 02_50V7K EMIP@ CA 30 BEEP# 2 2 EMIP@ CA28 1 1 ESD ACES_85 205 -04 001 ME@ SP0 200 08X 00 +5VS