A B C D E 1 Compal Confidential 2 PBL60 Schematics Document AMD APU Zacate-FT1 + FCH Hudson-M1 + GPU Seymour XT-M2 2010-02-15 3 REV:1.0 4 2010/06/30 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/06/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title P01-Cover Page Size B Date: Document Number Rev 1.0 LA-7322P Thursday, February 17, 2011 Sheet E of 47 A B C D E Compal confidential File Name : LA-7322P AMD Seymour-XT PCI-E GPP x4 GEN2 DDR3 VRAM 512M/1G 64*16/128*16 *4 Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2 AMD Brazos APU FT1 BGA 413-Ball 19mm x 19mm page 17 ~ 24 LVDS Conn LVDS(UMA & PX) HDMI Conn HDMI(UMA & PX) CRT Conn CRT(UMA & PX) Single Channel page 10 page 8,9 BANK 0, 1, 2, 1.5V DDRIII page 11 page 10 page 5,6,7 UMI Gen.1 x4 2.5GT/s per lane Port SATA HDD Conn Port SATA page 29 SATA ODD Conn page 29 Hudson M1 PCI-E 2.0 x1 2Channel Speaker BGA 605-Ball 23mm x 23mm Port page 26 AZALIA Port Audio Codec ALC269 Audio Jacks X (Headphone, MIC) page 26 page 26 Mini Card-1 WLAN (With Bluetooth) LAN(GbE) RTL8111E page 10 page 25 page 28 page 12 ~ 16 Port Port LPC BUS RJ45 DMIC USB2.0 page 25 LS-7326P Power BD Touch Pad SPI ROM Int.KBD page 31 page 30 page 31 USB Conn Port USB Conn (LS-7322P) Port Camera ENE KB930 page 30 USB Conn page 32 page 32 page 10 Port Mini Card WLAN (With Bluetooth) page 28 Port Card Reader RTS5137 page 27 LS-7322P Audio BD Thermal Sensor page 18 2010/06/30 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/06/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title P02-Block Diagrams Size B Date: Document Number Rev 1.0 LA-7322P Thursday, February 17, 2011 Sheet E of 47 C Voltage Rails Power Plane Description VIN Adapter power supply (19V) N/A B+ AC or battery power rail for power circuit N/A S1 D S5 FCH Hudson-M1 USB Port List N/A N/A USB1.1 N/A N/A S3 +APU_CORE Core voltage for CPU (0.7-1.2V) ON OFF OFF +APU_CORE_NB 1.0V switched power rail ON OFF OFF +1.5V 1.5V power rail for CPU VDDIO and DDRIII ON ON OFF +0.75VS 0.75VS switched power rail for DDR terminator ON OFF OFF +1.0VS 1.0V switched power rail for NB VDDC & VGA ON OFF OFF +1.1VS 1.1VS switched power rail ON OFF OFF +1.8VS 1.8V switched power rail ON OFF OFF +3VALW 3.3V always on power rail ON ON ON* +3V_LAN 3.3V power rail for LAN ON ON(WOL) OFF +3VS 3.3V switched power rail ON OFF OFF +5VALW 5V always on power rail ON ON ON* +5VS 5V switched power rail ON OFF OFF +VSB VSB always on power rail ON ON ON* +RTCVCC RTC power ON ON ON +1.1VALW 1.1V always on power rail ON ON ON* E Brazos PCIE Port List PCIE0 Port0 NC Port1 NC APU B PCIE1 PCIE2 GPU PCIE x4 FCH Hudson-M1 SATA Port List SATA0 HDD SATA1 ODD SATA2 NC SATA3 NC USB2.0 Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF PCIE3 Port0 JUSB1 PCIE0 LAN SATA4 NC Port1 JUSB2 PCIE1 WLAN SATA5 NC Port2 Camera PCIE2 NC Port3 JMINI(WLAN) PCIE3 NC Port4 Card Reader Port5 JUSB3 Port6 NC Port7 NC Port8 NC Port9 NC Port10 NC Port11 NC Port12 NC Port13 NC FCH A SMBUS Control Table SOURCE MIINI1 BATT X X V X X V X X X V FCH (+3VALW) X KB930 FCH_SMCLK0 FCH_SMDAT0 FCH_SMCLK3 FCH_SMDAT3 VRAM X X V FCH (+3VS) EC_SMB_CK2 EC_SMB_DA2 SODIMM X V X V X KB930 FCH X V X X X EC_SMB_CK1 EC_SMB_DA1 APU SCL0, SCL1, SCL2, SCL3, SCL4, SDA0 SDA1 SDA2 SDA3 SDA4 (Primary SMBUS in the S0 domain) (Secondary SMBUS supporting ASF) (Primary SMBUS in the S5 domain) (Primary low-voltage SBMBUS for Processor TSI) (Primary SMBUS in the S5 domain) 3 Symbol Note : : means Digital Ground BOM Structure 15G@: 1.5G CPU (E240) 16G@: 1.6G CPU (E350) 1G@ : 1G CPU (C50) UMA@ : APU output VGA@ : GPU used LS@ : Level shift used X76@L01 :VRAM 1G X76@L03 :VRAM 512M : means Analog Ground L01 : 16G@/VGA@/LS@/X76@L03 L02 : 16G@/UMA@/LS@ L03 : 15G@/VGA@/LS@/X76@L03 L04 : 15G@/UMA@/LS@ L05 : 16G@/VGA@/LS@/X76@L01 L06 : 15G@/VGA@/LS@/X76@L01 L07 : 1G@/VGA@/LS@/X76@L03 L08 : 1G@/UMA@/LS@ L09 : 1G@/VGA@/LS@/X76@L01 2010/06/30 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/06/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title P03-Notes List Size B Date: Document Number Rev 1.0 LA-7322P Thursday, February 17, 2011 Sheet E of 47 Power-Up/Down Sequence KŽƉƚŝŽŶ͗ W ͺ'W/KϬ͗,ŝŐŚͲхEŽƌŵĂůŽƉĞƌĂƚŝŽŶ;Ě'WhŝƐŶŽƚƌĞƐĞƚŽŶKŵŽĚĞͿ W ͺ'W/Kϭ͗>ŽǁͲхĚ'WhWŽǁĞƌK&&͖,ŝŐŚͲхĚ'WhWŽǁĞƌKE;ĂůǁĂLJƐ,ŝŐŚͿ VDDR3 should ramp-up before or simultaneously with VDDC For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before DPx_VDD18 For power-down, DPx_VDD18 should ramp-down before DPx_VDD10 The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and VDD_CT have ramped up 5.VDDC and VDD_CT should not ramp-up simultaneously (e.g., VDDC should reach 90% before VDD_CT starts to ramp-up (or vice versa).) VDDR3(3.3VSG) Note: Do not drive any IOs before VDDR3 is ramped up PCIE_VDDC(1.0V) C W ͺ'W/KϬ͗>ŽǁͲхZĞƐĞƚĚ'Wh͖,ŝŐŚͲхEŽƌŵĂůŽƉĞƌĂƚŝŽŶ W ͺ'W/Kϭ͗>ŽǁͲхĚ'WhWŽǁĞƌK&&͖,ŝŐŚͲхĚ'WhWŽǁĞƌKE All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred D tŝƚŚŽƵƚKŽƉƚŝŽŶ͗ VDDR1(1.5VSG) Ě'WhWŽǁĞƌWŝŶƐ sŽůƚĂŐĞ Wyϯ͘Ϭ KDŽĚĞ DĂdžĐƵƌƌĞŶƚ W/ ͺWs͕W/ ͺsZ͕d^s͕sZϰ͕sͺd͕ W ͺWs͕W&͗ ͺsϭϴ͕W͗ͺWs͕ W͗ͺsϭϴ͕s͕sϭ/͕ϮsY͕sϮ/͕ W>>ͺWs͕DWsϭϴ͕ĂŶĚ^Wsϭϴ ϭ͘ϴs K&& KE ϭϲϳϵŵ W&͗ ͺsϭϬ͕W͗ͺsϭϬ͕W>>ͺs͕ĂŶĚ ^WsϭϬ ϭ͘Ϭs K&& KE ϱϳϱŵ W/ ͺs ϭ͘Ϭs K&& KE Ϯ sZϯ͕ĂŶĚϮs ϯ͘ϯs K&& KE ϭϵϬŵ /&ͺs;ĐƵƌƌĞŶƚĐŽŶƐƵŵƉƚŝŽŶсϱϱŵΛϭ͘Ϭs͕ŝŶ KŵŽĚĞͿ ^ĂŵĞĂƐ s K&& KE ^ĂŵĞĂƐ W/ ͺs ϳϬŵ sZϭ ϭ͘ϱs K&& K&& Ϯ͘ϴ sͬs/ ϭ͘ϭϮs K&& K&& ϭϮ͘ϵ D C VDDC/VDDCI(1.12V) VDD_CT(1.8V) ŝ'Wh PE_GPIO0 PE_EN Ě'Wh PERSTb K^ǁŝƚĐŚ BIF_VDDC PE_GPIO1 REFCLK PX_mode нϯ͘ϯs>t B Straps Reset нϭ͘Ϭs Straps Valid MOS Regulator ϭ Ϯ нϯ͘ϯs^' нϭ͘Ϭs^' B нϭ͘ϱs SI4800 ϯ Regulator ϰ нϭ͘ϱs^' Global ASIC Reset нϭ͘ϴs SI4800 T4+16clock ϱ н нϭ͘ϴs^' нs'ͺKZ PWRGOOD A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/06/30 Deciphered Date 2012/06/30 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC P04-dGPU Block Diagram Size B Date: Document Number Rev 1.0 LA-7322P Thursday, February 17, 2011 Sheet of 47 +1.8VS A10 B10 10 APU_TXOUT2+ 10 APU_TXOUT2- B5 A5 10 APU_TXOUT1+ 10 APU_TXOUT1- D6 C6 C237 @ 0.01U_0402_25V7K APU_RST# C238 @ 0.01U_0402_25V7K APU_PWRGD +3VS R410 APU_PROCHOT# 1K_0402_5% 12 12 R411 1K_0402_5% APU_ALERT#_R R143 1K_0402_5% APU_SIC R414 1K_0402_5% APU_SID 10 APU_TXOUT0+ 10 APU_TXOUT0- A6 B6 10 APU_TXCLK+ 10 APU_TXCLK- D8 C8 APU_CLKP APU_CLKN 12 APU_DISP_CLKP 12 APU_DISP_CLKN 43 43 APU_SIC APU_SID R169 R168 30 EC_THERM# 12 FCH_PROCHOT# @ APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ# T93PAD T94PAD Close to APU 43 APU_VDDNB_RUN_FB_H 43 APU_VDD0_RUN_FB_H T77PAD P3 P4 SVC SVD SIC SID RESET_L PWROK PROCHOT_L THERMTRIP_L ALERT_L F4 G1 F3 VDDCR_NB_SENSE VDDCR_CPU_SENSE VDDIO_MEM_S_SENSE +3VS DAC_RED DAC_REDB DAC_GREEN DAC_GREENB DAC_BLUE DAC_BLUEB R398 APU_ENBKL 10 APU_ENVDD 10 APU_BLPWM 10 APU_HDMI_CLK APU_HDMI_DATA A3 B3 D3 C12 D13 A12 B12 A13 B13 DAC_HSYNC DAC_VSYNC DAC_SCL DAC_SDA F2 D4 DAC_ZVSS D12 TEST4 TEST5 TEST6 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19 TEST25_H TEST25_L TEST28_H TEST28_L TEST31 TEST33_H TEST33_L TEST34_H TEST34_L TEST35 TEST36 TEST37 R1 R2 R6 T5 E4 K4 L1 L2 M2 K1 K2 L5 M5 M21 J18 J19 U15 T15 H4 N5 R5 APU_HDMI_HPD 11 APU_LCD_CLK APU_LCD_DATA APU_LCD_CLK 10 APU_LCD_DATA 10 R406 100K_0402_5% 150_0402_1% R408 150_0402_1% R409 150_0402_1% APU_CRT_DDC_SCL 10 APU_CRT_DDC_SDA 10 R144 499_0402_1% PAD T66 PAD T67 PAD T68 TEST15 @ R416 R417 R418 1K_0402_5% C 1K_0402_5% 1K_0402_5% 510_0402_1% TEST31 PAD T73 TEST33_H C516 R420 0.1U_0402_16V4Z TEST33_L C517 R421 0.1U_0402_16V4Z Delete Test point for layout limitation 20100917 TEST35 R422 @ 1K_0402_5% TEST36 TEST37 R958 1K_0402_5% PAD T76 +1.8VS K3 T1 51_0402_1% 51_0402_1% Close to U22 0.1U_0402_16V4Z @ ALLOW_STOP# 12 R423 1K_0402_5% +1.8VS B ZACATE ZM161032B2238 1.6G BGA 413P AMD Debug Q79 U22 1G@ C H_THERMTRIP# 13 +1.8VS +1.8VS 0_0402_5% JHDT1 @ C236 BSH111, the Vgs is: = 0.4V Typ = 1.0V Max = 1.3V 0.1U_0402_10V7K @ R160 R842 CPU TSI interface level shift 1K_0402_5% ONTARIO CMC50AFPB22GT 1G If FCH internal pull-up disabled, level-shifter could be deleted Need BIOS to disable internal pull-up!! APU_TRST# FDV301N, the Vgs is: = 0.65V Typ = 0.85V Max = 1.5V R847 2 APU_TRST#_R 0_0402_5% 10K_0402_5% 11 R176 10K_0402_5% 13 R177 10K_0402_5% 15 R846 30K_0402_1% G APU_SID EC_SMB_DA D S @ Q22 BSH111 1N_SOT23-3 If use level shift, EC_SMB need pull up (pop R747 & R748) FCH_SID @ R429 R430 0_0402_5% EC_SMB_DA2 0_0402_5% @ R432 R433 FCH_SIC 0_0402_5% EC_SMB_CK2 0_0402_5% 19 10 11 12 13 14 15 16 17 18 19 20 APU_TCK R843 1K_0402_5% APU_TMS R840 1K_0402_5% APU_TDI R798 1K_0402_5% APU_TDO 10 APU_PWRGD 12 APU_RST# 14 APU_DBRDY 16 APU_DBREQ# R178 300_0402_5% 18 J108_PLLTST0 R799 0_0402_5% TEST19 20 J108_PLLTST1 R863 0_0402_5% TEST18 +1.8VS Please be noted about TEST_18 and TEST_19 FCH_SID 13 EC_SMB_DA2 18,30 T0 FCH A SAMTE_ASP-136446-07-B CONN@ TO EC 0_0402_5% G R431 17 1.607V for Gate A R415 TEST18 TEST19 TEST25_H TEST_25_L U22 16G@ MMBT3904_NL_SOT23-3 R427 31.6K_0402_1% APU_CRT_B 10 APU_CRT_HSYNC 10 APU_CRT_VSYNC 10 E APU_CRT_G 10 ONTARIO-2M161000-1.6G_BGA413 15G@ B APU_THERMTRIP# @ R428 APU_CRT_R 10 R425 1K_0402_5% +3VS +5VS R407 C639 TEST38 DMAACTIVE_L RSVD_1 RSVD_2 RSVD_3 D APU_HDMI_CLK 11 APU_HDMI_DATA 11 C1 E1 E2 VSS_SENSE 150_0402_1% R424 10K_0402_5% @ B LTDP0_HPD TDI TDO TCK TMS TRST_L DBRDY DBREQ_L B4 W11 V5 TDP1_AUXP TDP1_AUXN B2 C2 LTDP0_AUXP LTDP0_AUXN N2 N1 P1 P2 M4 M3 M1 F1 43 APU_VDD0_RUN_FB_L LTDP0_TXP3 LTDP0_TXN3 DISP_CLKIN_H DISP_CLKIN_L APU_PROCHOT# U1 APU_THERMTRIP# U2 APU_ALERT#_R T2 0_0402_5% 0_0402_5% LTDP0_TXP2 LTDP0_TXN2 CLKIN_H CLKIN_L T3 T4 12 APU_RST# 12 APU_PWRGD C LTDP0_TXP1 LTDP0_TXN1 D2 D1 G2 H2 H1 TDP1_HPD LTDP0_TXP0 LTDP0_TXN0 V2 V1 J1 J2 APU_SVC APU_SVD TDP1_TXP3 TDP1_TXN3 DP MISC 11 APU_HDMI_CLKP 11 APU_HDMI_CLKN TDP1_TXP2 TDP1_TXN2 VGA DAC D10 C10 H3 TEST 11 APU_HDMI_TX0P 11 APU_HDMI_TX0N TDP1_TXP1 TDP1_TXN1 DISPLAYPORT B9 A9 CLK 11 APU_HDMI_TX1P 11 APU_HDMI_TX1N DP_ZVSS DP_BLON DP_DIGON DP_VARY_BL SER 2 1 2 TDP1_TXP0 TDP1_TXN0 CTRL 1 2 1 APU_SVC APU_SVD APU_RST# APU_PWRGD TEST_25_L TEST36 1K_0402_5% 1K_0402_5% 300_0402_5% 300_0402_5% 510_0402_1% 1K_0402_5% JTAG R399 R400 R142 R401 R402 R141 DISPLAYPORT U22B A8 B8 11 APU_HDMI_TX2P 11 APU_HDMI_TX2N D APU_SIC D S EC_SMB_CK @ Q23 BSH111 1N_SOT23-3 R434 FCH_SIC 13 EC_SMB_CK2 18,30 TO EC Compal Secret Data Security Classification 2010/06/30 Issued Date 2012/06/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 0_0402_5% T0 FCH Title Compal Electronics, Inc P05-FT1 CTRL/DP/CRT Size Document Number Custom Rev 1.0 LA-7322P Date: Thursday, February 17, 2011 Sheet of 47 A B C D E U22E 8,9 DDR_A_DQS0 8,9 DDR_A_DQS#0 8,9 DDR_A_DQS1 8,9 DDR_A_DQS#1 8,9 DDR_A_DQS2 8,9 DDR_A_DQS#2 8,9 DDR_A_DQS3 8,9 DDR_A_DQS#3 8,9 DDR_A_DQS4 8,9 DDR_A_DQS#4 8,9 DDR_A_DQS5 8,9 DDR_A_DQS#5 8,9 DDR_A_DQS6 8,9 DDR_A_DQS#6 8,9 DDR_A_DQS7 8,9 DDR_A_DQS#7 9 9 8 8 DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 DDR_B_CLK2 DDR_B_CLK#2 DDR_B_CLK3 DDR_B_CLK#3 9 8 9 8 D15 B19 D21 H22 P23 V23 AB20 AA16 DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7 A16 B16 B20 A20 E23 E22 J22 J23 R22 P22 W22 V22 AC20 AC21 AB16 AC16 DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 DDR_B_CLK2 DDR_B_CLK#2 DDR_B_CLK3 DDR_B_CLK#3 M17 M16 M19 M18 N18 N19 L18 L17 DDR_RST# DDR_EVENT# 8,9 DDR_RST# 8,9 DDR_EVENT# 8,9 8,9 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 DDR_CKE0 DDR_CKE1 DDR_CKE0 DDR_CKE1 DDR_A_ODT0 DDR_A_ODT1 DDR_B_ODT0 DDR_B_ODT1 DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMB# DDR_CS1_DIMMB# F15 E15 DDR_A_ODT0 DDR_A_ODT1 DDR_B_ODT0 DDR_B_ODT1 W19 V15 U19 W15 DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMB# DDR_CS1_DIMMB# T17 W16 U17 V16 DDR_A_RAS# DDR_A_CAS# DDR_A_WE# 8,9 DDR_A_RAS# 8,9 DDR_A_CAS# 8,9 DDR_A_WE# L23 N17 U18 V19 V17 M_DATA0 M_DATA1 M_DATA2 M_DATA3 M_DATA4 M_DATA5 M_DATA6 M_DATA7 M_DATA8 M_DATA9 M_DATA10 M_DATA11 M_DATA12 M_DATA13 M_DATA14 M_DATA15 DDR SYSTEM MEMORY R18 T18 F16 8,9 DDR_A_BS0 8,9 DDR_A_BS1 8,9 DDR_A_BS2 M_ADD0 M_ADD1 M_ADD2 M_ADD3 M_ADD4 M_ADD5 M_ADD6 M_ADD7 M_ADD8 M_ADD9 M_ADD10 M_ADD11 M_ADD12 M_ADD13 M_ADD14 M_ADD15 M_BANK0 M_BANK1 M_BANK2 M_DM0 M_DM1 M_DM2 M_DM3 M_DM4 M_DM5 M_DM6 M_DM7 M_DQS_H0 M_DQS_L0 M_DQS_H1 M_DQS_L1 M_DQS_H2 M_DQS_L2 M_DQS_H3 M_DQS_L3 M_DQS_H4 M_DQS_L4 M_DQS_H5 M_DQS_L5 M_DQS_H6 M_DQS_L6 M_DQS_H7 M_DQS_L7 M_DATA16 M_DATA17 M_DATA18 M_DATA19 M_DATA20 M_DATA21 M_DATA22 M_DATA23 M_DATA24 M_DATA25 M_DATA26 M_DATA27 M_DATA28 M_DATA29 M_DATA30 M_DATA31 M_DATA32 M_DATA33 M_DATA34 M_DATA35 M_DATA36 M_DATA37 M_DATA38 M_DATA39 M_DATA40 M_DATA41 M_DATA42 M_DATA43 M_DATA44 M_DATA45 M_DATA46 M_DATA47 M_CLK_H0 M_CLK_L0 M_CLK_H1 M_CLK_L1 M_CLK_H2 M_CLK_L2 M_CLK_H3 M_CLK_L3 M_DATA48 M_DATA49 M_DATA50 M_DATA51 M_DATA52 M_DATA53 M_DATA54 M_DATA55 M_RESET_L M_EVENT_L M_CKE0 M_CKE1 M_DATA56 M_DATA57 M_DATA58 M_DATA59 M_DATA60 M_DATA61 M_DATA62 M_DATA63 M0_ODT0 M0_ODT1 M1_ODT0 M1_ODT1 M0_CS_L0 M0_CS_L1 M1_CS_L0 M1_CS_L1 B14 A15 A17 D18 A14 C14 C16 D16 DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 C18 A19 B21 D20 A18 B18 A21 C20 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 C23 D23 F23 F22 C22 D22 F20 F21 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 H21 H23 K22 K21 G23 H20 K20 K23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 N23 P21 T20 T23 M20 P20 R23 T22 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 V20 V21 Y23 Y22 T21 U23 W23 Y21 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 Y20 AB22 AC19 AA18 AA23 AA20 AB19 Y18 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 AC17 Y16 AB14 AC14 AC18 AB18 AB15 AC15 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 M23 +MEM_VREF M22 R437 DDR_A_D[0 63] DDR_A_MA[0 15] DDR_A_DM[0 7] DDR_A_D[0 63] 8,9 DDR_A_MA[0 15] DDR_A_DM[0 7] 8,9 8,9 U22A 17 PCIE_GTX_C_FRX_P0 17 PCIE_GTX_C_FRX_N0 PCIE_GTX_C_FRX_P0 PCIE_GTX_C_FRX_N0 AA6 Y6 17 PCIE_GTX_C_FRX_P1 17 PCIE_GTX_C_FRX_N1 PCIE_GTX_C_FRX_P1 PCIE_GTX_C_FRX_N1 AB4 AC4 17 PCIE_GTX_C_FRX_P2 17 PCIE_GTX_C_FRX_N2 PCIE_GTX_C_FRX_P2 PCIE_GTX_C_FRX_N2 AA1 AA2 17 PCIE_GTX_C_FRX_P3 17 PCIE_GTX_C_FRX_N3 PCIE_GTX_C_FRX_P3 PCIE_GTX_C_FRX_N3 Y4 Y3 +1.05VS R435 2K_0402_1% P_ZVDD_10 Y14 P_GPP_RXP0 P_GPP_RXN0 P_GPP_RXP1 P_GPP_RXN1 P_GPP_RXP2 P_GPP_RXN2 P_GPP_RXP3 P_GPP_RXN3 P_GPP_TXP0 P_GPP_TXN0 PCIE I/F R17 H19 J17 H18 H17 G17 H15 G18 F19 E19 T19 F17 E18 W17 E16 G15 P_GPP_TXP1 P_GPP_TXN1 P_GPP_TXP2 P_GPP_TXN2 P_GPP_TXP3 P_GPP_TXN3 P_ZVDD_10 P_ZVSS AB6 PCIE_FTX_GRX_P0 AC6 PCIE_FTX_GRX_N0 C518 1VGA@2 0.1U_0402_16V7K C519 1VGA@2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P0 17 PCIE_FTX_C_GRX_N0 17 AB3 PCIE_FTX_GRX_P1 AC3 PCIE_FTX_GRX_N1 C520 1VGA@2 0.1U_0402_16V7K C521 1VGA@2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P1 17 PCIE_FTX_C_GRX_N1 17 Y1 Y2 PCIE_FTX_GRX_P2 PCIE_FTX_GRX_N2 C522 1VGA@2 0.1U_0402_16V7K C523 1VGA@2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P2 17 PCIE_FTX_C_GRX_N2 17 V3 V4 PCIE_FTX_GRX_P3 PCIE_FTX_GRX_N3 C524 1VGA@2 0.1U_0402_16V7K C525 1VGA@2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P3 17 PCIE_FTX_C_GRX_N3 17 AA14 P_ZVSS R436 1.27K_0402_1% Less than 1" Less than 1" 12 UMI_RX0P 12 UMI_RX0N AA12 Y12 12 UMI_RX1P 12 UMI_RX1N AA10 Y10 12 UMI_RX2P 12 UMI_RX2N AB10 AC10 12 UMI_RX3P 12 UMI_RX3N AC7 AB7 P_UMI_RXP0 P_UMI_RXN0 P_UMI_RXP1 P_UMI_RXN1 P_UMI_RXP2 P_UMI_RXN2 P_UMI_RXP3 P_UMI_RXN3 P_UMI_TXP0 P_UMI_TXN0 UMI I/F DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 P_UMI_TXP1 P_UMI_TXN1 P_UMI_TXP2 P_UMI_TXN2 P_UMI_TXP3 P_UMI_TXN3 AB12 AC12 UMI_TX0P_C UMI_TX0N_C C526 C527 2 0.1U_0402_16V7K 0.1U_0402_16V7K AC11 AB11 UMI_TX1P_C UMI_TX1N_C C528 C529 2 0.1U_0402_16V7K 0.1U_0402_16V7K AA8 Y8 UMI_TX2P_C UMI_TX2N_C C530 C531 2 0.1U_0402_16V7K 0.1U_0402_16V7K AB8 AC8 UMI_TX3P_C UMI_TX3N_C C532 C533 2 0.1U_0402_16V7K 0.1U_0402_16V7K UMI_TX0P 12 UMI_TX0N 12 UMI_TX1P 12 UMI_TX1N 12 UMI_TX2P 12 UMI_TX2N 12 UMI_TX3P 12 UMI_TX3N 12 ONTARIO-2M161000-1.6G_BGA413 15G@ M_VREF M_RAS_L M_CAS_L M_WE_L M_ZVDDIO_MEM_S ONTARIO-2M161000-1.6G_BGA413 15G@ 15 mils +1.5V 39.2_0402_1% DDR_CKE0 DDR_CKE1 DDR_EVENT# 2 1K_0402_5% R1706 68_0402_5% +MEM_VREF R149 R438 1K_0402_1% R1705 68_0402_5% +1.5V 1 +1.5V R439 1K_0402_1% 1 C534 C535 1000P_0402_50V7K 0.1U_0402_16V4Z Place within 1000 mils to APU 20100526 For AMD recommend to fix S3 issue Compal Secret Data Security Classification Issued Date 2010/06/30 2012/06/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Compal Electronics, Inc P06-FT1 DDRIII/UMI/PCIE Size Document Number Custom Rev 1.0 LA-7322P Date: Thursday, February 17, 2011 Sheet E of 47 +APU_CORE +1.8VS 10U_0603_6.3V6M C577 10U_0603_6.3V6M C578 10U_0603_6.3V6M C579 10U_0603_6.3V6M 2 10U_0603_6.3V6M 1U_0402_6.3V6K C583 C584 1U_0402_6.3V6K C585 1U_0402_6.3V6K C586 1U_0402_6.3V6K C587 1U_0402_6.3V6K 180P_0402_50V8J C588 10U_0603_6.3V6M 1U_0402_6.3V6K C549 1U_0402_6.3V6K C548 1U_0402_6.3V6K C547 1U_0402_6.3V6K C538 0.1U_0402_16V7K C546 180P_0402_50V8J C537 C545 POWER Change from SM010014520 to SD002000080 20100816 2 2 @ FBMA-L11-201209-221LMA30T_0805 Change from SM010014520 to SD002000080 20100816 +1.05VS 0.2A VDDPL_10 L31 +VDDL_10 U11 2 VDDIO_MEM_S_1 VDDIO_MEM_S_2 VDDIO_MEM_S_3 VDDIO_MEM_S_4 VDDIO_MEM_S_5 VDDIO_MEM_S_6 VDDIO_MEM_S_7 VDDIO_MEM_S_8 VDDIO_MEM_S_9 VDDIO_MEM_S_10 VDDIO_MEM_S_11 10U_0603_6.3V6M W9 10U_0603_6.3V6M C684 VDD_18_DAC 10U_0603_6.3V6M C604 VDDCR_NB_1 VDDCR_NB_2 VDDCR_NB_3 VDDCR_NB_4 VDDCR_NB_5 VDDCR_NB_6 VDDCR_NB_7 VDDCR_NB_8 VDDCR_NB_9 VDDCR_NB_10 VDDCR_NB_11 VDDCR_NB_12 VDDCR_NB_13 VDDCR_NB_14 VDDCR_NB_15 VDDCR_NB_16 VDDCR_NB_17 VDDCR_NB_18 VDDCR_NB_19 VDDCR_NB_20 VDDCR_NB_21 VDDCR_NB_22 5.5A VDD_10_1 VDD_10_2 VDD_10_3 VDD_10_4 U13 W13 V12 T12 2 FBMA-L11-201209-221LMA30T_0805 L32 2 0.5A VDD_33 +VDD_10 2 2 FBMA-L11-201209-221LMA30T_0805 Change from SM010014520 to SD002000080 20100816 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSSBG_DAC N13 N20 N22 P10 P14 R4 R7 R20 T6 T9 T11 T13 U4 U5 U7 U12 U20 U22 V8 V9 V11 V13 W1 W2 W4 W5 W7 W12 W20 Y5 Y7 Y9 Y11 Y13 Y15 Y17 Y19 AA4 AA22 AB2 AB5 AB9 AB13 AB17 AB21 AC5 AC9 AC13 A11 D C +3VS ONTARIO-2M161000-1.6G_BGA413 15G@ A4 ONTARIO-2M161000-1.6G_BGA413 15G@ C582 U22D A7 B7 B11 B17 B22 C4 D5 D7 D9 D11 D14 B15 D17 D19 E7 E9 E12 E20 F8 F11 F13 G4 G5 G7 G9 G12 G20 G22 H6 H11 H13 J4 J5 J7 J20 K10 K14 L4 L6 L8 L11 L13 L20 L22 M7 N4 N6 N8 N11 +1.8VS DP Phy/IO G16 G19 E17 J16 L16 L19 N16 R16 R19 W18 U16 10U_0603_6.3V6M C576 1 L30 +VDD_18_DAC DDR3 C575 2A 0.15A PCIE/IO/DDR3 Phy +1.5V C 10U_0603_6.3V6M C574 +APU_CORE_NB 1U_0402_6.3V6K C573 0.1U_0402_16V7K 2 10U_0603_6.3V6M 0.1U_0402_16V7K E8 E11 E13 F9 F12 G11 G13 H9 H12 K11 K13 L10 L12 L14 M11 M12 M13 N10 N12 N14 P11 P13 1U_0402_6.3V6K C572 C563 10A 1U_0402_6.3V6K C567 0.1U_0402_16V7K +APU_CORE_NB 0.1U_0402_16V7K C571 C562 1U_0402_6.3V6K C558 C555 180P_0402_50V8J 2 0.1U_0402_16V7K C566 C554 180P_0402_50V8J 0.1U_0402_16V7K C570 U8 W8 U6 U9 W6 T7 V7 1 180P_0402_50V8J 2 1U_0402_6.3V6K C553 1U_0402_6.3V6K VDD_18_1 VDD_18_2 VDD_18_3 VDD_18_4 VDD_18_5 VDD_18_6 VDD_18_7 C556 10U_0603_6.3V6M VDDCR_CPU_1 VDDCR_CPU_2 VDDCR_CPU_3 VDDCR_CPU_4 VDDCR_CPU_5 VDDCR_CPU_6 VDDCR_CPU_7 VDDCR_CPU_8 VDDCR_CPU_9 VDDCR_CPU_10 VDDCR_CPU_11 VDDCR_CPU_12 VDDCR_CPU_13 VDDCR_CPU_14 VDDCR_CPU_15 DIS PLL 0.1U_0402_16V7K 10U_0603_6.3V6M 2 10U_0603_6.3V6M 10U_0603_6.3V6M E5 E6 F5 F7 G6 G8 H5 H7 J6 J8 L7 M6 M8 N7 R8 L29 FBMA-L11-201209-221LMA30T_0805 GND C561 C540 GPU AND NB CORE 1 C544 DAC C560 180P_0402_50V8J C557 C552 1U_0402_6.3V6K 2 1U_0402_6.3V6K C559 0.1U_0402_16V7K C543 C564 C551 1U_0402_6.3V6K 10U_0603_6.3V6M 180P_0402_50V8J C565 C550 C542 CPU CORE 10U_0603_6.3V6M 2 10U_0603_6.3V6M C568 C541 180P_0402_50V8J C569 C580 C536 +VDD_18 0.1U_0402_16V7K C581 C539 2A TSense/PLL/DP/PCIE/IO D U22C 11A +APU_CORE Power Cap Summary APU S POLY C 330U 2.5V M D2E TPE LESR9M H1.8 ->+APU_CORE(Qty : 3) Unpop:2 +APU_CORE S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU ->+APU_CORE(Qty : 2) +1.5V S POLY C 330U 2.5V Y D2 LESR9M EEFS H1.9 ->+APU_CORE_NB(Qty : 1) +APU_CORE_NB S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU ->+APU_CORE_NB(Qty : 1) C589 C591 0.1U_0402_16V7K C592 C593 0.1U_0402_16V7K C594 0.1U_0402_16V7K 1 C590 10U_0603_6.3V6M 0.1U_0402_16V7K C595 B 1 C596 1U_0402_6.3V6K POWER 10U_0603_6.3V6M C597 1U_0402_6.3V6K C598 1U_0402_6.3V6K S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU ->+1.5V(Qty : 1) +1.5V S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU ->1.05VS(Qty : 1) +1.05VS S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU ->+1.8VS(Qty : 1) +1.8VS DDR3 Socket 1U_0402_6.3V6K B S POLY C 330U 2V M X LESR6M SX H1.9 ->1.5V(Qty : 1) +1.5V +1.05VS FCH S POLY C 330U 2.5V Y D2 LESR9M EEFS H1.9 ->1.1VS(Qty : 1) UMA unpop +1.1VS 0.1U_0402_16V7K C601 0.1U_0402_16V7K C602 0.1U_0402_16V7K C603 180P_0402_50V8J GPU 180P_0402_50V8J S POLY C 330U 2V M X LESR6M SX H1.9 ->VGA_CORE(Qty : 2) Unpop:1 +GPU_CORE S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU ->+VGA_CORE(Qty : 1) S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU ->+1.5VSG(Qty : 1) +1.5V S_A-P_CAP 220U 6.3V M C45 R17M SVPE H4.4 ->+USB_VCCA(Qty : 1) 330U_D2E_2.5VM_R9M C606 1 1 390U_2.5V_10M 390U_2.5V_10M +@ C607 + C1104+ C1105+ 1 C103 180P_0402_50V8J By case (Along split plane) 1 C623 C685 C624 + C622 + C617 + C618 + 390U_2.5V_10M 390U_2.5V_10M C619 390U_2.5V_10M 10U_0603_6.3V6M 2 10U_0603_6.3V6M 390U_2.5V_10M @ C625 @ 10U_0603_6.3V6M 2 @ @ 2 @ @ @ @ A 10U_0603_6.3V6M @ Near CPU Socket Near CPU Socket Compal Secret Data Security Classification Near CPU Socket Issued Date 2010/06/30 Deciphered Date 2012/06/30 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC (390uF_2.5V_6.3x5.7_ESR10m)*1=(SF000002O00) Title Compal Electronics, Inc P07-FT1 PWR/VSS Size C Date: @ C613 C612 180P_0402_50V8J C608 A C611 POWER 0.1U_0402_16V7K +1.8VS C610 POWER +1.5V Near CPU Socket FOR EMI PURPOSE +1.5V +APU_CORE_NB +USB_VCCA C104 180P_0402_50V8J 0.1U_0402_16V7K C102 0.1U_0402_16V7K C609 2 0.1U_0402_16V7K 10U_0603_6.3V6M C616 @ 390U_2.5V_10M 2 C101 0.1U_0402_16V7K 0.1U_0402_16V7K C605 + @ 330U_D2E_2.5VM_R9M +1.5VSG USB POWER +APU_CORE 180PF Qt'y follow the distance between CPU socket and DIMM0 C615 C600 180P_0402_50V8J C614 C599 180P_0402_50V8J C621 + @ 390U_2.5V_10M 180P_0402_50V8J C620 @ 10U_0603_6.3V6M Document Number Rev 1.0 LA-7322P Thursday, February 17, 2011 Sheet of 47 +1.5V +1.5V JDIMM1 +VREF_DQ C680 DDR_A_D0 DDR_A_D1 C681 0.1U_0402_16V4Z D DDR_A_DM0 1000P_0402_50V7K DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D9 6,9 DDR_A_DQS#1 6,9 DDR_A_DQS1 DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17 6,9 DDR_A_DQS#2 6,9 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_DM3 DDR_A_D26 DDR_A_D27 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 DDR_A_D4 DDR_A_D5 DDR_A_DQS#0 6,9 DDR_A_DQS0 6,9 DDR_A_D[0 63] 6,9 DDR_CKE0 6,9 DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 6 DDR_B_CLK2 DDR_B_CLK#2 DDR_A_MA10 6,9 DDR_A_BS0 6,9 DDR_A_WE# 6,9 DDR_A_CAS# DDR_A_MA13 DDR_CS1_DIMMB# DDR_A_D32 DDR_A_D33 6,9 DDR_A_DQS#4 6,9 DDR_A_DQS4 B DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41 DDR_A_DM5 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 6,9 DDR_A_DQS#6 6,9 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 DDR_A_DM7 DDR_A_D58 DDR_A_D59 R155 10K_0402_5% DDR_A_DM[0 7] @ R150 10K_0402_5% R152 10K_0402_5% @ R151 10K_0402_5% 205 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 G2 206 G1 D DDR_A_DM[0 7] 6,9 DDR_A_DM1 DDR_RST# 6,9 DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A_DM2 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 6,9 DDR_A_DQS3 6,9 +1.5V DDR_A_D30 DDR_A_D31 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_CKE1 6,9 C45 0.1U_0402_16V4Z 2 C652 C653 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 C654 C655 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 C682 1 0.1U_0402_16V4Z C683 C47 0.1U_0402_16V4Z C48 0.1U_0402_16V4Z C49 0.1U_0402_16V4Z C DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 CRB 0.1u X1 4,7uX1 DDR_A_MA2 DDR_A_MA0 +0.75VS DDR_B_CLK3 DDR_B_CLK#3 C50 @ 0.1U_0402_16V4Z DDR_A_BS1 6,9 DDR_A_RAS# 6,9 DDR_CS0_DIMMB# DDR_B_ODT0 C51 C664 0.1U_0402_16V4Z 4.7U_0603_6.3V6K DDR_B_ODT1 +VREF_CA DDR_A_D36 DDR_A_D37 C665 Place near JDIMM2 C666 DDR_A_DM4 DDR_A_D38 DDR_A_D39 0.1U_0402_16V4Z 1000P_0402_50V7K B DDR_A_D44 DDR_A_D45 DDR_A_DQS#5 6,9 DDR_A_DQS5 6,9 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 6,9 DDR_A_DQS7 6,9 DDR_A_D62 DDR_A_D63 DDR_EVENT# 6,9 FCH_SMDAT0 9,13,28 FCH_SMCLK0 9,13,28 A +0.75VS TYCO_2-2013289-1 DDR3 SO-DIMM A H:5.2mm Standard Typ Compal Secret Data Security Classification 2010/06/30 Issued Date 2012/06/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC C46 0.1U_0402_16V4Z 2 DDR_A_MA15 DDR_A_MA14 2 C668 +3VS 0.1U_0402_16V4Z C667 2.2U_0603_6.3V4Z A +3VS 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 6,9 DDR_A_MA[0 15] 6,9 DDR_A_D12 DDR_A_D13 C44 C DDR_A_D[0 63] DDR_A_MA[0 15] DDR_A_D6 DDR_A_D7 Title Compal Electronics, Inc P08-DDR3 SODIMM-I Socket Size Document Number Custom Rev 1.0 LA-7322P Date: Thursday, February 17, 2011 Sheet of 47 +1.5V +1.5V JDIMM2 D DDR_A_D8 DDR_A_D9 6,8 DDR_A_DQS#1 6,8 DDR_A_DQS1 DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17 6,8 DDR_A_DQS#2 6,8 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_DM3 DDR_A_D26 DDR_A_D27 205 G1 DDR_A_MA[0 15] DDR_A_DQS#0 6,8 DDR_A_DQS0 6,8 +1.5V 6,8 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 DDR_A_D[0 63] 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 DDR_A_D[0 63] DDR_A_MA[0 15] 6,8 DDR_A_DM[0 7] R145 1K_0402_1% DDR_A_DM[0 7] 6,8 DDR_A_D6 DDR_A_D7 R146 1K_0402_1% 15mil 15mil DDR_A_D2 DDR_A_D3 +1.5V DDR_A_D4 DDR_A_D5 +VREF_DQ DDR_A_D12 DDR_A_D13 +VREF_CA D 1000P_0402_50V7K VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 DDR_A_DM1 R147 1K_0402_1% DDR_RST# 6,8 DDR_A_D14 DDR_A_D15 R148 1K_0402_1% DDR_A_DM0 0.1U_0402_16V4Z VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 DDR_A_D0 DDR_A_D1 C627 C626 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 +VREF_DQ 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 DDR_A_D20 DDR_A_D21 DDR_A_DM2 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 6,8 DDR_A_DQS3 6,8 DDR_A_D30 DDR_A_D31 +1.5V 6,8 C DDR_CKE0 6,8 DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 6 DDR_A_CLK0 DDR_A_CLK#0 DDR_A_MA10 6,8 DDR_A_BS0 6,8 DDR_A_WE# 6,8 DDR_A_CAS# DDR_A_MA13 DDR_CS1_DIMMA# DDR_A_D32 DDR_A_D33 B 6,8 DDR_A_DQS#4 6,8 DDR_A_DQS4 DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41 DDR_A_DM5 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 6,8 DDR_A_DQS#6 6,8 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 DDR_A_DM7 For DRAM strap pin reservation 20100817 DDR_A_D58 DDR_A_D59 R961 R153 @ 10K_0402_5% 10K_0402_5% +3VS 1 C646 C647 G2 206 TYCO_2-2013310-1 CRB only one 4.7k DDR_CKE1 6,8 DDR_A_MA15 DDR_A_MA14 0.1U_0402_16V4Z C628 DDR_A_MA11 DDR_A_MA7 0.1U_0402_16V4Z C629 0.1U_0402_16V4Z C630 C631 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 C632 0.1U_0402_16V4Z C633 0.1U_0402_16V4Z 2 C634 0.1U_0402_16V4Z C635 0.1U_0402_16V4Z 2 C636 C637 0.1U_0402_16V4Z C 0.1U_0402_16V4Z C638 0.1U_0402_16V4Z C110 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_CLK1 DDR_A_CLK#1 DDR_A_BS1 6,8 DDR_A_RAS# 6,8 CRB 0.1u X1 DDR_CS0_DIMMA# DDR_A_ODT0 DDR_A_ODT1 4.7u X1 CRB DDR_A_D36 DDR_A_D37 C645 X2 +1.5V 2 C640 C641 @ 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 C644 DDR_A_DM4 DDR_A_D38 DDR_A_D39 100U +0.75VS +VREF_CA 1000P_0402_50V7K 0.1U_0402_16V4Z 2 C642 + 4.7U_0603_6.3V6K C1102 330U_D2E_2.5VM_R9M B DDR_A_D44 DDR_A_D45 DDR_A_DQS#5 6,8 DDR_A_DQS5 6,8 Place near JDIMM1 330U ESR:9m H:2 P/N:SGA20331E10 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 +1.5V 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 DDR_A_DQS#7 6,8 DDR_A_DQS7 6,8 DDR_A_D62 DDR_A_D63 C643 C675 C676 C678 A DDR_EVENT# 6,8 FCH_SMDAT0 8,13,28 FCH_SMCLK0 8,13,28 +0.75VS Compal Secret Data Security Classification DDR3 SO-DIMM B H:9.2mm Standard Type 2.2U_0603_6.3V4Z @ R154 10K_0402_5% R962 0.1U_0402_16V4Z 10K_0402_5% 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 A CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 Issued Date 2010/06/30 2012/06/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC For DRAM strap pin reservation 20100817 Title Compal Electronics, Inc P09-DDR3 SODIMM-II Socket Size Document Number Custom Rev 1.0 LA-7322P Date: Sheet Thursday, February 17, 2011 of 47 D1 HSYNC_L 1 VSYNC_L YSDA0502C 3P C/A SOT-23 @ VGA_DDC_DATA_C W=40mils +CRT_VCC CRT_G_R 0_0402_5% CRT_B_R C1573 C1574 C1576 For EMI C1577 2 +CRT_VCC JCRT1 +3VS +CRT_VCC DDC_MD2 C1580 R1650 0_0603_5% U88 74AHCT1G125GW_SOT353-5 C1583 Close to APU APU_CRT_DDC_SCL R1649 C1584 2 CRT_CLK 0_0402_5% Q101B CRT_DATA R4 @ CRT_CLK R31 @ DMN66D0LDW-7_SOT363-6 W=60mils +LCDVDD S G R1656 C1589 C9 @ R1657 10K_0402_5% Q99B 2N7002DW-7-F_SOT363-6 26 26 DMIC_CLK DMIC_DATA APU_TXOUT25 APU_TXOUT2+ APU_TXCLK5 APU_TXCLK+ 13 13 +3VS Camera USB20_N2 USB20_P2 USB20_N2 USB20_P2 W=60mils +LCDVDD +3VS R1670 10K_0402_5% @ D29 AZC199-02SPR7G_SOT23-3 AZC199-02SPR7G_SOT23-3 @ @ D30 INVTPWM DISPOFF# 2 APU_LCD_CLK APU_LCD_DATA 1 +3VS @ C1590 R1664 100K_0402_1% R1662 2 0_0402_5% APU_ENBKL APU_ENBKL R1663 2.2K_0402_5% R1661 100K_0402_5% 2.2K_0402_5% R1660 30 1 ENBKL INVTPWM 0_0402_5% 0_0402_5% 0_0402_5% @ 0.1U_0402_16V4Z 2N7002DW-7-F_SOT363-6 Q99A 0.047U_0402_16V7K R1655 INVT_PWM R1659 220K_0402_1% R1654 30 2 APU_BLPWM 0.1U_0402_16V4Z APU_TXOUT15 APU_TXOUT1+ 22P_0402_50V8J C1586 For EMI, close to JLVDS1 APU_TXOUT05 APU_TXOUT0+ APU_ENVDD 1 C1588 2 W=60mils 4.7U_0805_10V4Z C1585 4.7U_0805_10V4Z 1 0.1U_0402_16V4Z C1587 B D R1653 47K_0402_5% R1652 100_0805_5% L119 B+_L FBMA-L11-201209-221LMA30T_0805 B+ +3VS Q93 SI2301BDS-T1-E3_SOT23-3 1 +LCDVDD R1672 30 For AMD check list LCD POWER CIRCUIT +5VALW VGA_DDC_CLK_C C1582 @ VGA_DDC_DATA_C 0_0402_5% VGA_DDC_CLK_C 0_0402_5% 680P_0402_50V7K @ +LCDVDD VGA_DDC_CLK_C C CONN@ VGA_DDC_DATA_C C1581 @ 15P_0402_50V8J 0_0402_5% Y VSYNC_L 15P_0402_50V8J A CRT_VSYNC_D 16 17 SUYIN_070546FR015S263ZR VGA_DDC_DATA_C Q101A DMN66D0LDW-7_SOT363-6 G APU_CRT_VSYNC_R P OE# APU_CRT_VSYNC 2.2K_0402_5% 1K_0402_5% G G 100P_0402_50V8J R1648 1 100P_0402_50V8J C1579 0.1U_0402_16V4Z CRT_DATA 0_0402_5% 100P_0402_50V8J APU_CRT_DDC_SDA +CRT_VCC R1646 R1645 R1647 R1642 2.2K_0402_5% U87 74AHCT1G125GW_SOT353-5 R1644 HSYNC_L 0_0603_5% C R1651 VSYNC_L 1 R1643 CRT_HSYNC_D 2.2K_0402_5% 0_0402_5% Y A 2 HSYNC_L BLUE 1K_0402_5% 2.2K_0402_5% P OE# APU_CRT_HSYNC_R G 11 12 13 14 10 15 T69 PAD RED R1641 2 GREEN +CRT_VCC C1578 R1640 1 0.1U_0402_16V4Z APU_CRT_HSYNC C1571 @ BLUE D SMD1812P075TF 75A 13.2V RB491D_SOT23-3 C1570 GREEN C1575 6.8P_0402_50V8J 6.8P_0402_50V8J C1572 6.8P_0402_50V8J 150_0402_1% R1639 150_0402_1% R1638 2 150_0402_1% 0_0402_5% R1637 0.1U_0402_16V4Z R1636 W=40mils RED 6.8P_0402_50V8J APU_CRT_B 0_0402_5% 6.8P_0402_50V8J APU_CRT_G L116 NBQ160808T-800Y-N 0603 L117 NBQ160808T-800Y-N 0603 L118 NBQ160808T-800Y-N 0603 CRT_R_R L115 1+5VS_CRTVCC ESD D R1635 D4 YSDA0502C 3P C/A SOT-23 @ YSDA0502C 3P C/A SOT-23 @ R1634 VOUT AP2230_SOT23-3 VGA_DDC_CLK_C VIN @ +CRT_VCC APU_CRT_R Q92 YSDA0502C 3P C/A SOT-23 D6 D2 RED +5VS @ 0.1U_0402_16V4Z GND BLUE GREEN CRT D3 6.8P_0402_50V8J BKOFF# BKOFF# JLVDS1 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 B G1 G2 G3 G4 G5 41 42 43 44 45 HONDA_LVD-A40SFYG+ CONN@ 0_0402_5% DISPOFF# ESD RB751V40_SC76-2 @ D5 For EMI, close to JLVDS1 C122 A A R1677 10K_0402_5% Compal Secret Data Security Classification Issued Date 2010/06/30 Deciphered Date 2012/06/30 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title P10-LVDS/CRT CONN Size C Date: Compal Electronics, Inc Document Number Rev 1.0 LA-7322P Thursday, February 17, 2011 Sheet 10 of 47 A B C D +5VALW TO +5VS +1.1VALW TO +1.1VS +1.1VALW 5VS_GATE C1447 R1111 100K_0402_5% 10U_0603_6.3V6M C1449 2 1U_0402_6.3V4Z 10U_0603_6.3V6M VLDT_EN# 30 SUSP S +VSB R1105 47K_0402_5% 1.1VS_GATE S SSM3K7002FU_SC70-3 Q56 G D S D S SSM3K7002FU_SC70-3 R1107 10K_0402_5% C1451 VLDT_EN# 0.1U_0603_25V7K C1450 D Q51 G VLDT_EN SSM3K7002FU_SC70-3 Q55 G SUSP Q53 G 47K_0402_5% 1 R1103 R1104 C1448 1K_0402_5% 10U_0603_6.3V6M C1444 2 1U_0402_6.3V4Z D +VSB +5VALW R1101 150_0603_5% 1 10U_0603_6.3V6M 2 10U_0603_6.3V6M C1446 C1445 1 1 C1443 +1.1VS U39 AO4478L 1N SO8 +5VS U38 AO4478L 1N SO8 Change P/N SB00000HZ00 +5VALW E 0.1U_0603_25V7K SSM3K7002FU_SC70-3 +3VALW TO +3VS Change P/N SB00000HZ00 +3VS +3VALW 2 U41 AO4478L 1N SO8 +5VALW S 0.1U_0603_25V7K R1109 100K_0402_5% S 28,30,38,42 SUSP# Q59 G 1 D D Q52 G C1456 SYSON SSM3K7002FU_SC70-3 30,39 1 SUSP SUSP S R1115 10K_0402_5% D 11,41 SYSON# SSM3K7002FU_SC70-3 SUSP S SSM3K7002FU_SC70-3 Q61 G R1116 100K_0402_5% R1108 100K_0402_5% Q60 G SSM3K7002FU_SC70-3 D 10U_0603_6.3V6M C1455 2 1U_0402_6.3V4Z R1110 300_0603_5% 3VS_GATE 200K_0402_5% SUSP R1112 +VSB 1 10U_0603_6.3V6M 2 10U_0603_6.3V6M +5VALW C1452 1 C1454 1 C1453 3 +1.5VS C1463 0.1U_0603_25V7K SUSP 2 1 S G SUSP S SSM3K7002FU_SC70-3 S D Q80 SSM3K7002FU_SC70-3 Q74 G D SYSON# Q78 G D VLDT_EN# S S SSM3K7002FU_SC70-3 Q28 G 1.5_VDDC_PWREN# 1.5_VDDC_PWREN# 24 VGA@ SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 S SSM3K7002FU_SC70-3 2010/06/30 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/06/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A R1126 470_0603_5% VGA@ D Q67 G R1128 470_0603_5% 1 200K_0402_5% G +VGA_CORE SUSP# Q65 D D R1122 R1137 470_0603_5% 1 R1135 470_0603_5% R1120 470_0603_5% C1461 10U_0603_6.3V6M +1.1VS G 100K_0402_5% +0.75VS 2 R1121 +1.5V +1.5VS D S 3 Q63 SI2301CDS-T1-GE3_SOT23-3 +1.5V B C D Title P34-DC Interface Size Document Number Custom Rev 1.0 LA-7322P Date: Thursday, February 17, 2011 Sheet E 34 of 47 B C PL1 HCB2012KF-121T50_0805 2 X7R type PC5 0.1U_0603_16V7K PR1 22K_0402_1% 1 PC4 100P_0402_50V8J PU1 VCC TMSNS1 GND RHYST1 OT1 TMSNS2 OT2 RHYST2 OTP_N_001 OTP_N_002 PR2 22.1K_0402_1% 2 VL PC3 1000P_0402_50V7K @ACES_88323-0471 PC2 100P_0402_50V8J 4 PC1 1000P_0402_50V7K 2 1 PH1 under CPU botten side : CPU thermal protection at 92 +-3 degree C Recovery at 80 +-3 degree C VIN PL2 HCB2012KF-121T50_0805 ADPIN PJPDC1 D A OTP_N_003 VMB PJP2 @SUYIN_200275MR009G186ZL VS_ON 37 0_0402_5% BATT+ PC6 1000P_0402_50V7K 2 PD1 2 PC7 0.01U_0402_25V7K PR27 1K_0402_1% 1 GND GND B/I EC_SMCA EC_SMDA TS_A PH1 100K_0402_1%_NCP15W F104F03RC PR4 PL4 HCB2012KF-121T50_0805 2 @PJSOT24CW_SOT323-3 10 11 G718TM1U_SOT23-8 PL3 HCB2012KF-121T50_0805 2 PD2 PR31 100_0402_1% EC_SMB_DA1 30 VL PR13 100K_0402_1% BATT_TEMP 30 1K_0402_1% 37,40 SPOK PR16 0_0402_5% 2VSB_N_002 G S VSB_N_001 VIN D PQ1 TP0610K-T1-GE3_SOT23-3 PQ2 SSM3K7002FU_SC70-3 PC10 0.1U_0402_16V7K 1 1VSB_N_003 +3VALW 2 100K_0402_5% PR30 PR12 22K_0402_1% PR29 EC_SMB_CK1 30 @PJSOT24CW _SOT323-3 PC8 0.22U_0603_25V7K PR10 100K_0402_1% PR28 100_0402_1% +VSBP PC9 0.1U_0603_25V7K B+ 2 PD3 RLS4148_LL34-2 VS_N_001 1 +VSB (120mA,40mils ,Via NO.= 1) PR18 68_1206_5% VS PC12 0.1U_0603_25V7K 2 PC11 0.22U_0603_25V7K 2 PR21 100K_0402_1% 1 JUMP_43X39 PQ3 PR17 TP0610K-T1-GE3_SOT23-368_1206_5% N1 1 PD4 RLS4148_LL34-2 2 BATT+ PJ2 +VSBP 4 33 PR22 22K_0402_1% 51_ON# VS_N_002 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2009/01/23 Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title DCIN / BATT CONN / OTP Size Document Number Rev 0.1 NCL61 LA-6321P M/B Date: Friday, February 18, 2011 Sheet D 35 of 44 B C 1CHG_N_0081 CSON 22 CELLS CSOP 21 ICOMP CSIN 20 VCOMP CSIP 19 ICM PHASE 18 LX_CHG VREF UGATE 17 DH_CHG DCIN EN PQ106 DTC115EUA_SC70-3 CHLIM BOOT 16 6251aclim 10 ACLIM VDDP 15 11 VADJ LGATE 14 GND PGND 13 PD106 RB751V-40TE17_SOD323-2 6251VDDP 12 DL_CHG 26251VDD 1 1CHG_SNUB2 PR128 20K_0402_1% PQ110 2 BATT+ PC101 10U_0805_25V6K ACPRN G PQ109 @SSM3K7002FU_SC70-3 PL101 PR102 10UH_MSCDRI-104A-100M-E_4.6A_20% 0.02_1206_1% CHG PC121 0.1U_0603_25V7K BST_CHGA 2 Rtop 30 CHGVADJ CHG_CHLIM S PQ108 AON7408L_DFN8-5 PR122 2.2_0603_1% PR126 0_0603_5% BST_CHG CHG_N_006 PC114 @2200P_0402_25V7K PR125 @4.7_1206_5% CSOP CHG_N_001 D CSON PR118 20_0603_5% CHG_CSON PC113 0.047U_0603_16V7K CHG_CSOP PR119 20_0603_5% CHG_CSIN PC118 PR120 0.1U_0603_25V7K 20_0603_5% CHG_CSIP AON7406L_DFN8-5 PR127 226K_0402_1% 6251VREF ACPRN 6251VREF PC106 2200P_0402_25V7K PC105 0.1U_0402_25V6 PR111 14.3K_0402_1% PC125 @10U_0805_25V6K PC110 1000P_0402_50V7K 2 23 PR129 4.7_0603_5% PC123 4.7U_0805_6.3V6K ACSET ACPRN PR115 100K_0402_1% ISL6251AHAZ-T QSOP 24P PR105 10K_0402_1% PR104 140K_0402_1% PQ111 DTC115EUA_SC70-3 2 PC120 0.1U_0402_16V7K ACOFF ACOFF 24 100_0402_1% CHG_ICM PR103 150K_0402_1% PC122 0.01U_0402_25V7K 2 IREF 30 ADP_I DCIN PC120 must close EC pin CHG_VCOMP VDD 30 30 PR123 0.01U_0402_25V7K PACIN PR124 22K_0402_5% 10K_0402_1% PC112 1U_0603_25V6K 6800P_0402_25V7K CHG_ICOMP PR121 1 VIN PC124 @680P_0402_50V7K PC117 10_1206_5% PR110 47K_0402_1% PR112 10K_0402_1% PC116 SSM6N7002FU_US6 CHG_N_009 6251_EN PR130 0_0402_5% PU101 CHG_N_005 2 PQ107B 2S: Float 3S: GND CHG_VADJ 3CHG_N_002 SSM6N7002FU_US6 PR113 1 PQ107A CHG_VIN PC109 2.2U_0603_6.3V6K 1 PR117 PR116 150K_0402_1% ACSETIN PD101 PC104 10U_0805_25V6K 1 2 FSTCHG 100K_0402_1% CHG_N_001 30 RB751V-40TE17_SOD323-2 ACSETIN PR114 10K_0402_1% 2 PQ105 DTC115EUA_SC70-3 PR108 191K_0402_1% 6251VDD CHG_N_003 CSIN CSIP PR107 200K_0402_1% PC108 0.1U_0603_25V7K 2 PR109 47K_0402_1% 1CHG_N_010 PQ104 DTA144EUA_SC70-3 PQ103 AO4407AL 1P SO8 VIN B+ CHG_B+ PL102 @HCB2012KF-121T50_0805 PC103 4.7U_0805_25V6K 1 PR101 0.02_1206_1% PC107 5600P_0402_25V7K VIN P3 PQ102 AO4409L_SO8 P2 PQ101 AO4435L_SO8 PC102 10U_0805_25V6K B+ 1.2UH_1127AS-1R2N_2.4A_30% (B+ 6A,240mils ,Via NO.= 12) D PL103 10U_0805_25V6K PC129 4.7U_0805_25V6K PC128 A PR106 22K_0402_1% 3 PR131 47K_0402_1% ACIN PR132 10K_0402_1% 30 PACIN C ACPRN PQ112 B 1 Iada=0~4.737A(90W);CP=4.03A;where Racdet=0.020ohm,where Rtop=12.4K 90W for Dis:Rtop:SD00000AJ80 Iada=0~3.421A(65W);CP=2.91A;where Racdet=0.020ohm,where Rtop=226K 65W for UMA:Rtop:SD034226380 Astro2010_01_15 need confirm P/N CP= 85%*Iada; PR133 10K_0402_1% 1 6251VDD PR136 20K_0402_1% Add E MMBT3904W H NPN SOT323-3 CP mode Vaclim=VREF*(Rbot//Rinternal/(Rtop//Rinternal+Rbot//Rinternal)) when 90W Vaclim=2.39*(20K//152K/(20K//152K+12.4K//152K))=1.44966V when 65W Vaclim=2.39*(20K//152K/(20K//152K+226K//152K))=0.38914V Iinput=(1/Racdet)*((0.05*Vaclim/VREF+0.05)) when 90W,Iinput=(1/0.02)*(0.05*1.44966/2.39+0.05)=4.02A when 65W,Iinput=(1/0.02)*(0.05*0.38914/2.39+0.05)=2.92A CHGVADJ=(Vcell-4)/0.10627 CC=0.25A~3A IREF=1.016*Icharge Vcell IREF=0.254V~3.048V 4V VCHLIM need over 95mV 4.2V CHGVADJ Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 0V 1.882V 2009/01/23 Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title CHARGER Size Document Number Rev 0.1 NCL61 LA-6321P M/B Date: Friday, February 18, 2011 D Sheet 36 of 44 A B C D E 2VREF_6182 VO1 24 PGOOD 23 VO2 PC306 10U_0805_25V6K PR307 162K_0402_1% PC312 2200P_0402_50V7K ENTRIP1 B++ FB1 REF PR306 20K_0402_1% PQ305 AON7408L_DFN8-5 2 PR305 30.9K_0402_1% ENTRIP1 P PAD TONSEL 25 ENTRIP2 PU301 PC313 10U_0805_6.3V6M PQ303 AON7408L_DFN8-5 PC304 4.7U_0805_25V6K PC310 2200P_0402_50V7K PR303 140K_0402_1% FB_5V ENTRIP2 +3VLP PC309 0.1U_0402_25V6 LGATE1 19 LG_5V PQ306 NC 18 17 16 SPOK 35,40 SNUB_5V VREG5 VIN PR314 499K_0402_1% LGATE2 PL305 4.7UH_FMJ-0630T-4R7 HF_5.5A_20% S IC RT8205LZQW(2) WQFN 24P PWM EN0 AON7406L_DFN8-5 + PC305 220U_6.3VM_R15 1 PC318 4.7U_0805_10V6K 2 PC320 1U_0603_10V6K +5VALWP AO4406AL_SO8 VL PR315 95.3K_0402_1% PR313 4.7_1206_5% LX_5V PC317 680P_0402_50V7K 20 PHASE1 UG_5V PHASE2 EN 22 21 13 B++ BOOT1 UGATE1 GND 12 PR309 PC315 2.2_0402_5% 0.1U_0402_10V7K BST_5V BST1_5V UGATE2 BOOT2 15 LG_3V PQ304 PC316 680P_0402_50V7K SNUB_3V + 11 PC303 220U_6.3VM_R15 LX_3V +3VALWP PR312 4.7_1206_5% PL303 4.7UH_FMJ-0630T-4R7 HF_5.5A_20% VREG3 SKIPSEL PC314 PR308 0.1U_0402_10V7K BST1_3V 1 2 BST_3V 2.2_0402_5% UG_3V 10 14 PC322 @680P_0402_50V7K FB_3V FB2 PL301 HCB2012KF-121T50_0805 1 PR302 20K_0402_1% B++ B+ PC311 0.1U_0402_25V6 PR301 13.7K_0402_1% 1 PC308 1U_0603_16V6K B++ PC319 0.1U_0603_25V7K N_3_5V_001 G D PQ307A SSM6N7002FU_US6 D ENTRIP2 ENTRIP1 2VREF_6182 S PQ307B SSM6N7002FU_US6 G S +3VLP +5VALWP +CHGRTC PJP302 PJP305 2 +5VALW (11A,440mils ,Via NO.= 22) PAD-OPEN 2x2m PAD-OPEN 4x4m PJP306 1 VL VL PJP301 PAD-OPEN 4x4m PJP303 PQ308 DTC115EUA_SC70-3 +3VALWP +3VALW (4A,120mils ,Via NO.= 8) PAD-OPEN 4x4m EC:+3VL, reserve PR319, install PR318, PR320 100K EC:+3VALW, reserve PR318, install PR319, PR320 42.2K Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A PAD-OPEN 2x2m PC321 2.2U_0603_10V6K PR317 100K_0402_5% 2 PR319 100K_0402_1% 2 PR320 42.2K_0402_1% VS 35 VS_ON B C D Title Compal Electronics, Inc 3.3VALWP/5VALWP Size Document Number Custom Date: Rev 0.1 LAXXXX Friday, February 18, 2011 Sheet E 37 of 44 A B C D 1 PC402 22U_0805_6.3VAM 1 PR402 10K_0402_1% PC401 22U_0805_6.3VAM SY8033BDBC_DFN10_3X3 PR401 20K_0402_1% PC404 68P_0402_50V8J 1.8VSP_FB NC TP PR405 @47K_0402_5% 11 EN_1.8VSP 2 PR404 0_0402_5% FB VFB=0.6V Vo=VFB*(1+PR401/PR402)=0.6*(1+20K/10K)=1.8V +1.8VSP 2 EN LX PR403 4.7_1206_5% SVIN PC405 @0.1U_0402_10V7K 30,34,41,42 SUSP# PL401 1UH_PCMC063T-1R0MN_11A_20% 1.8VSP_LX PVIN PC406 680P_0402_50V7K SNUB_1.8VSP LX NC PVIN PC403 22U_0805_6.3VAM 10 1.8VSP_VIN PU401 HCB1608KF-121T30_0603 PG PL402 +5VALW PJP401 +1.8VSP +1.8VS (2.5A, 100mils, Via NO.= 5) PAD-OPEN 3x3m 3 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2009/01/23 Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title +1.8VSP Size Document Number Rev 0.1 NCL61 LA-6321P M/B Date: Sheet Friday, February 18, 2011 D 38 of 44 D D 1.5V_B+ PR503 30,34 SYSON 0_0402_5% B+ PL502 HCB1608KF-121T30_0603 EN_1.5V PR502 2.15K_0402_1% NC 10 LGATE TRIP_1.5V +5VALW LG_1.5V +5VALW PGOOD 11 1 2 PC502 @680P_0402_50V7K +1.5VP C 15.4K_0402_1% PQ502 PC510 4.7U_0805_10V6K CS VDDP PR508 1SNUB_1.5V FB PL501 2.2UH_PCMC063T-2R2MN_8A_20% + PC501 220U_6.3VM_R15 FDS6690AS-G_SO8 2 RT8209MGQW _W QFN14_3P5X3P5 PR509 @4.7_1206_5% 14 15 VDD PHASE LX_1.5V PC511 @680P_0402_50V7K 2.21K_0402_1% PC509 4.7U_0603_10V6K FB_1.5V UG_1.5V PQ501 AON7408L_DFN8-5 PR501 13 12 1 PGND +1.5VP V5FILT_1.5V PR507 100_0402_1% +5VALW +5VALW VOUT GND +1.5VP UGATE TON PC508 0.1U_0402_10V7K BOOT C EN/DEM PU501 PR506 255K_0402_1% 2TON_1.5V PC507 0.1U_0402_25V6 2200P_0402_50V7K PC506 PR504 2.2_0402_5% BST_1.5V 2BST1_1.5V PC504 @4.7U_0805_25V6-K PC503 10U_0805_25V6K PC505 @0.1U_0402_10V7K PJP502 B B @PAD-OPEN 4x4m PJP501 +1.5VP +1.5V (8A,320mils ,Via NO.= 16) @PAD-OPEN 4x4m A A Compal Secret Data Security Classification 2007/05/29 Issued Date Deciphered Date 2008/05/29 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc +1.5VP Size Document Number Rev 0.1 LAXXXX Date: Friday, February 18, 2011 Sheet 39 of 44 D D 1.1V_B+ PR703 SPOK 0_0402_5% PL702 HCB1608KF-121T30_0603 EN_1.1V B+ PC704 @0.1U_0402_10V7K PL701 1UH_PCMC063T-1R0MN_11A_20% TRIP_1.1V PR708 10 +5VALW LG_1.1V +5VALW PQ702 FDS6690AS-G_SO8 PC709 4.7U_0805_10V6K VDDP LGATE +1.1VALWP 15.4K_0402_1% 2 1SNUB_1.1V RT8209MGQW _W QFN14_3P5X3P5 11 + PR706 @100K_0402_5% CS PHASE LX_1.1V PR709 @4.7_1206_5% 14 15 NC BOOT UG_1.1V 12 PGOOD 13 FB UGATE PQ701 AON7408L_DFN8-5 PC701 220U_6.3VM_R15 C PC710 @680P_0402_50V7K PR702 10K_0402_1% FB_1.1V PC707 0.1U_0402_10V7K 2 VDD PGND PR701 4.64K_0402_1% VOUT +1.1VALW P PC708 4.7U_0603_6.3V6M 1 PR707 100_0603_1% C V5FILT_1.1V 2 +5VALW TON +1.1VALW P +5VALW EN/DEM PR705 255K_0402_1% 2TON_1.1V GND PU701 PC706 0.1U_0402_25V6 PC705 2200P_0402_50V7K 2 PC703 @4.7U_0805_25V6-K PR704 2.2_0402_5% BST_1.1V BST1_1.1V PC702 10U_0805_25V6K 1 35,37 PJP701 +1.1VALW P +1.1VALW (8A,320mils ,Via NO.=16) PAD-OPEN 4x4m B B A A Compal Secret Data Security Classification 2009/12/01 Issued Date Deciphered Date 2010/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc PWR+1.1VALWP Size Document Number Custom Rev 0.1 LAXXXX Date: Friday, February 18, 2011 Sheet 40 of 44 +1.5V +1.1VALW TO +1.05VSP PU601 VOUT NC TP PC603 1U_0603_10V6K APL5336KAI-TRL_SOP8P8 PC609 4.7U_0603_6.3V6K VREF_G2992 D VREF VCNTL GND PQ601 IRF8707GTRPBF_SO8 PC602 1U_0402_6.3V6K PR601 1K_0402_1% +1.05VSP_L +3VALW PC608 4.7U_0603_6.3V6K NC NC VIN 2 PC601 4.7U_0805_6.3V6K +1.1VALW 1 D PR603 47K_0402_5% +VSB PQ603 G D SUSP PC616 @0.1U_0402_10V7K 1 PR605 330K_0402_5% S 2 PC605 10U_0805_6.3V6M PC607 0.1U_0402_25V6 PR602 1K_0402_1% S G 0_0402_5% 10.75VS_N_002 2 D PC604 0.1U_0402_16V7K PR604 11,34 SUSP PQ602 SSM3K7002FU_SC70-3 +VSB1 +0.75VSP SSM3K7002FU_SC70-3 +3VALW 2 PC606 @0.1U_0402_10V7K PR606 @100K_0402_1% +1.05VSP_N001 D G S PQ604A @SSM6N7002FU_US6 D +1.05VSP_N002 G (2A,80mils ,Via NO.= 4) PQ604B S @SSM6N7002FU_US6 VGA_PWRGD 12,23,42,44C @0_0402_5% +0.75VS 1 +0.75VSP PR607 PJP601 C PAD-OPEN 3x3m PC610 @0.1U_0402_10V7K PJP602 +1.05VSP_L +1.05VS (5A,200mils ,Via NO.=10) PAD-OPEN 4x4m 1HHGWRFRQILUPZLWK+:SRZHUVHTXHQFH +5VALW PC613 0.1U_0402_25V6 PR611 7.32K_0402_1% 2 B +1.0VSP PR610 1.82K_0402_1% FB GND PC615 22U_0805_6.3V6M PD601 VOUT VOUT VGA_PWR_ON EN POK 30,34,38,42 PC614 180P_0402_50V8J PR609 100K_0402_1% APL5930KAI-TRG_SO8 VCNTL VIN VIN B PU602 1 PR608 @1K_0402_1% PC611 4.7U_0805_6.3V6K +3VS PC612 1U_0603_10V6K +1.5VP 1SS355_SOD323-2 PJP603 +1.0VSP +1.0VSG (2.5A,100mils ,Via NO.= 5) PAD-OPEN 3x3m A A Compal Secret Data Security Classification Issued Date 2006/11/23 Deciphered Date 2007/11/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc PWR 0.75VSP +1.05VSP Size Document Number Rev 0.1 LAXXXX Date: Sheet Friday, February 18, 2011 41 of 44 A B C D 1 PL802 PC802 @22U_0805_6.3VAM PC804 @68P_0402_50V8J 1 PR802 @10K_0402_1% PC801 @22U_0805_6.3VAM SNUB_1.05VSP @SY8035DBC_DFN10_3X3 PR801 @7.5K_0402_1% 1.05VSP_FB +1.05VSP 2 LX FB PC806 @680P_0402_50V7K 2 2 PR805 @47K_0402_5% LX 1.05VSP_LX PR803 @4.7_1206_5% PL801 @1UH_PCMC063T-1R0MN_11A_20% EN_1.05VSP PR804 @0_0402_5% 11 @0_0402_5% 1 SS EN PC805 @0.1U_0402_10V7K 30,34,38,41 SUSP# SVIN 2 TP PC803 @22U_0805_6.3VAM PVIN PR806 LX 12,23,41,44 VGA_PWRGD PU802 10 PVIN 1.05VSP_VIN PG @HCB1608KF-121T30_0603 +5VALW PJP801 +1.05VSP +1.05VS (5A,200mils ,Via NO.=10) PAD-OPEN 4x4m 3 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2009/01/23 Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title +1.05VSP Size Document Number Rev 0.1 NCL61 LA-6321P M/B Date: Sheet Friday, February 18, 2011 D 42 of 44 PC235 68P_0402_50V8J 2 PR226 100_0402_5% PC236 470P_0402_50V8J 2 APU_VDD0_RUN_FB_H 45 D PR234 0_0402_5% 1 PC238 @68P_0402_50V8J PC237 @68P_0402_50V8J PC239 @68P_0402_50V8J +APU_CORE 45 PR230 0_0402_5% COMP +5VS PR232 10K_0402_1% 2 PR231 47K_0402_1% D PR252 10K_0402_1% APU_VDD0_RUN_FB_L 45 PR236 100_0402_5% FB RGND CPU_B+ 25 VFIX/DRPSEL PGND0 OCSET_NB PHASE0 UGATE0 PHASE0 UGATE0 BOOT0 PC249 2200P_0402_50V7K PC247 PC243 2200P_0402_50V7K PC245 0.1U_0402_25V6 @68U_25V_M_R0.44 10U_0805_25V6K PC244 2 0_0402_5% 10uF_0603 * 1uF_0402 * 0.1uF_0402 * 180P_0402 * 390uF * Reserve 330uF * PC241 0.1U_0402_25V6 BOOT_NB PR206 2.2_0603_5% PR222 10K_0402_1% PR223 47K_0402_1% 2 PC211 2200P_0402_50V7K (10A, 400mils, via no = 20) PHASE_NB COMP_NB PC227 @68P_0402_50V8J PQ203 AO4468L_SO8 LGATE_NB FB_NB PC206 0.1U_0402_25V6 2 PC228 @68P_0402_50V8J RGND_NB PL202 1UH_MMD-06CZ-1R0M-V1_11A_20% +APU_CORE_NB + PR213 2K_0402_1% PR251 8.2K_0402_1% ISP_NB PR225 B PC216 0.22U_0603_10V7K 1 PR224 0_0402_5% PC229 @68P_0402_50V8J PC204 @4.7U_0805_25V6-K PC215 0.1U_0402_25V6 PR210 1SNUB_NB2 4.7_1206_5% PC220 680P_0603_50V7K APU_VDD0_RUN_FB_L PC226 68P_0402_50V8J PR220 0_0402_5% 2 45 APU_VDDNB_RUN_FB_H PC225 470P_0402_50V8J 2 45 +APU_CORE_NB PR219 100_0402_5% PQ202 AON7408L_DFN8-5 2 130K_0402_1% TON_NB PR205 PR207 1_0402_5% PC205 10U_0805_25V6K CPU_B+ PC231 2 ISN0 UGATE_NB 45 +CPU_CORE Imax=7.7A Ipeak=11A Iocp(minimum)=13.2A DCR=4.2mohm Rdson = 7mohm PR246 21 PC232 @0.01U_0402_25V7K @0.01U_0402_25V7K 2 PR240 22K_0402_1% PR242 2.43K_0402_1% PR244 2.43K_0402_1% PC242 0.1U_0402_25V6 PC203 1U_0603_10V6K PR202 2_0603_5% OCSET_NB PR239 5.1K_0402_1% (14A, 560mils, via no = 28) ISP0 BOOT_NB PHASE_NB 20 15 RGND_NB 19 14 ISN_NB BOOT_NB 13 ISP_NB UGATE_NB 12 TON_NB BOOT0 18 COMP_NB 11 COMP_NB FB_NB UGATE_NB VCC 24 22 PC218 220U_6.3VM_R15 PC222 10uF_0603 * 1uF_0402 * 0.1uF_0402 * 180P_0402 * 390uF * Reserve 390uF PR217 ISN_NB PC223 0.1U_0402_25V6 0_0402_5% 2 A Compal Secret Data Security Classification Issued Date 2009/12/01 Deciphered Date 2010/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title A Compal Electronics, Inc PWR-CPU_CORE Size C Date: +CPU_CORE_NB Imax=7A Ipeak=10A Iocp(minimum)=12A DCR=10mohm Rdson = 22mohm 0.1U_0402_25V6 100_0402_5% C +APU_CORE 4.7_1206_5% LGATE0 23 + +3VS VFIX/DRPSEL B LGATE0 1SNUB_CPU PVCC PC252 1U_0603_10V6K PR249 26 PR221 0_0402_5% PQ205 AO4726L_SO8 LGATE0 27 1 PVCC RT8870AZQW_WQFN40_5X5 PGOOD FB_NB B+ PL204 0.47UH_MMD-06CZ-R47M-V1_17.5A_20% 29 28 PHASE0 32 31 BOOT1 ISP1 ISN1 33 34 RGND 35 ISN0 37 38 36 ISP0 TON COMP UGATE0 680P_0603_50V7K PC251 PWORK 1 PR229 33K_0402_1% 39 40 LGATE1 10 +5VS FB 41 PGND1 SVD PHASE_NB 0_0402_5% 2 PR228 10K_0402_1% OCSET_NB VCC PR255 10K_0402_1% PGOOD VFIX/DRPSEL SVC LGATE_NB PR235 45,52 VGATE +5VS 30 17 H_PWRGD_L PHASE1 PGND_NB FCH_PWROK 45 PR227 0_0402_5% PR238 0_0402_5% PR233 @0_0402_5% EN 16 45 LGATE_NB 45 APU_SVD ENABLE RGND_NB 45 APU_SVC BOOT0 PR250 2_0603_5% UGATE1 PQ206 AON7408L_DFN8-5 PC250 PR248 0.1U_0402_25V6 2.2_0603_5% 2 PC240 0.22U_0603_10V7K +5VS RBIAS ISN_NB +1.5V ISP_NB PR237 @51_0402_1% PR241 @51_0402_1% RBIAS TON_NB PR208 100K_0402_1% C OCSET PC234 @0.01U_0402_25V7K 45 VR_ON GND PU201 PR245 110K_0402_1% TON 2 ISN0 ISP0 TON OCSET PC230 0.1U_0402_25V6 PR254 @10K_0402_1% PC246 @4.7U_0805_25V6-K PR247 1_0402_5% ISN1 ISP1 +3VS PL205 HCB2012KF-121T50_0805 PR256 10K_0402_1% PC253 @0.01U_0402_25V7K PR253 7.15K_0402_1% 2 +5VS Document Number Rev 0.1 LAXXXX Friday, February 18, 2011 Sheet 43 of 44 A EN_VGA VDDP 10 LGATE PR923 0_0402_5% +5VALW PR905 11K_0402_1% 2 1 + PR912 @4.7_1206_5% PC911 4.7U_0805_10V6K 1SNUB_VGA LG_VGA PQ906 TPCA8059-H_PPAK56-8-5 VGA_PW RGD 12,23,41,42 +VGA_CORE 1 TRIP_VGA PC913 @680P_0402_50V7K 11 BOOT NC CS PL901 0.56UH +-20% PCMC104T-R56MN 25A RT8209BGQW _W QFN14_3P5X3P5 PR911 100K_0402_1% PC912 0.1U_0402_10V7K LX_VGA (14A, 560mils, via no = 28) PR902 10K_0402_1% PR914 pin2 trace need to close VGA chipset MLCC.(remote sense) PC912 pin1 trace need to close PC901 (local sense.) +3VS PR917 15K_0402_1% PQ903A SSM6N7002FU_US6 N_VGA_003 GPU_VID1 PC914 0.022U_0402_16V7K PQ903B SSM6N7002FU_US6 PR903 10.5K_0402_1% N_VGA_004 1 18 GPU_VID1 PR918 10K_0402_5% +VGA_CORE 1 0.9V 1.05V 0 1.1V PR919 N_VGA_005 PQ904B SSM6N7002FU_US6 1 PR904 30.1K_0402_1% N_VGA_006 PC915 0.022U_0402_16V7K PQ904A SSM6N7002FU_US6 1 2 10K_0402_5% N_VGA_002 PR920 15K_0402_1% 2 18 GPU_VID0 GPU_VID0 N_VGA_001 PR916 10K_0402_5% 2 GCORE_SEN +VGA_CORE 20 GCORE_SEN 2 PR914 100_0402_5% 2 1 +3VS 12 PGOOD PHASE FB UG_VGA 14 15 EN/DEM VDD 13 NTMS4816NR2G_SO8 UGATE PC902 4.7U_0805_6.3V6K VOUT PC901 390U_2.5V_M PC910 1U_0603_10V6K FB_VGA PR901 2K_0402_1% +VGA_COREP1 PGND V5FILT_VGA TON B+ PR907 PC909 2.2_0402_1% 0.1U_0402_10V7K +VGA_CORE GND PR909 255K_0402_1% TON_VGA Need to close PC901 2 1 1+5VALW PU901 PC907 2200P_0402_50V7K PR908 316_0402_1% 2BST1_VGA PC904 4.7U_0805_25V6K PQ901 BST_VGA PC903 4.7U_0805_25V6K PC906 0.1U_0402_25V6 +5VALW VGA_B+ PC905 @0.1U_0402_10V7K PL902 HCB1608KF-121T30_0603 PC908 @680P_0402_50V7K 23,34 1.5_VDDC_PWREN D PR922 0_0402_5% C B PR921 10K_0402_5% 4 Compal Secret Data Security Classification Issued Date 2007/05/29 Deciphered Date 200810/11 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title Compal Electronics, Inc VGA_CORE Size Document Number Rev 0.1 LAXXXX Date: Sheet Friday, February 18, 2011 D 44 of 44 32:(56(48(1&( $&,1%$77,1 9$/:9$/:9$/: D (&B560567 D 7!PV 3%71B287 (&WR)&+ )&+WR(& 6/3B6 6/3B6 )&+WR(& 'HOD\6/3B6PV 6