acer aspire 5745p 5745pg 5820t quanta zr7 rev 3b sch

5 VER : 1A BOM P/N BOM MARK ZR7 SYSTEM BLOCK DIAGRAM Description D DDRIII-SODIMM2 DDRIII-SODIMM1 Dual Channel DDR III 800/1066 MHZ Clarksfield Arrandale Auburndale IMC rPGA 989 P14,15 P4, 5, 6, Channel A PCI-E x16 P21, 22 GFX EXT_CRT SLG8LV595 CLOCK GENERATOR FDI P23 SN74CBT3257 x3 LVDS/CRT SWITCH DMI(x4) P3 CRT Con TS3DV421 EXT_LVDS DMI FDI D EXT_LVDS P16, 17, 18, 19, 20, 21, 22, X'TAL 14.318MHz 64MB/128MB x Channel C N11M-GE1 N11P-GE1 Nvidia-GPU IV@ INT VGA EV@ DISCRETE SW@ SW VGA 11P@ N11P VGA 11M@ N11P VGA 11EP@ N11P + N11E VGA 3D@ N11E VGA +3D ES@ N11X+SW VGA CSP@ Option P/N (ARD&R D) VSP@ Option P/N (GPU/ VRAM) USB-8 INT_CRT DMI P23 INT_LVDS CLK LVDS/CCD/MIC Con P23 Int MIC Display SATA SATA - HDD C C P28 INT_HDMI SATA PS8101 LS P24 SATA SATA - ODD P28 USB Port x4 P33 USB-1/3/9/11 USB P24 PCIE-6 PCI-E x1 Ibex Peak-M MINI CARD WLAN USB-13 PCH Bluetooth Con HDMI Con EXT_LVDS USB-4 P27 P8, 9, 10, 11, 12, 13 P33 Cardreader P31 AU6437 Cardreader control Reference IV@ P31 RJ45 P25 P26 X'TAL 25MHz X'TAL 25MHz P8 B RTC BATTERY Description for UMA only SKU SW@ for Switchable Graphic only SKU SP@ special case component * AR8151 GIGA LAN USB-12 B BOM Option Table PCIE-1 X'TAL 32.768KHz Azalia ISL88731A SPI ROM (ME) SPI IHDA MAX8792ETD+T Batery Charger P37 P9 LPC not stuff +VGPU_CORE P43 RT8206B 3V/5V LPC P38 ISL62881HRZ-T Int MIC ALC271 AUDIO CODEC NPCE781 EC +VGFX_AXG P36 P29 UP6111AQDD HPA00835RTER P40 Speaker P30 MIC JACK HP/SPDIF P30 P30 A Power Board Con P33 P37 +1.8V P45 Touch Pad Board Con Function Board Con P33 CIR P46 X'TAL 32.768KHz A P35 P42 K/B Con W25X16VSS1G SPI FLASH P35 P37 EM-6781-T3 HALL SENSOR P24 Fan Driver (PWM Type) P35 Quanta Computer Inc PROJECT : ZR7 Size Document Number Rev 3B Block Diagram Date: Sheet Monday, February 22, 2010 1 of 49 GPU PWR CTRL Option (Default/ VDDR3 before VDDC) +3.3V VIN +3V_D VDDR3 dGPU_VRON PG_GPUIO_EN VDDC MOS (AO3413) P22 ISL6264 +1.5V PG_1V_EN VDDCI +1V (DP PLL PWR) P45 +VGPU_CORE (20A) +1.5V_SUS PG_1.5V_EN G9334ADJ & MOS ISL62872 P44 +3_D (0.5A) A VIN PG_1.5V_EN +1V (3A) +5V PG_1.5V_EN VDDR4 MOS (AO4710) P43 P47 +VGPU_IO (4.5A) VDDR1 +1.8V MOS (AO6402) P43 +1.5V_GPU (10A) dGPU_PWROK BJT dGPU_PWR_EN# MOS AO3413 P22 P22 +1.8V_GPU (3A) +5_GPU A GPU PWR CTRL Option (VDDR3 after VDDR1) VIN VIN PG_GPUIO_EN VDDC dGPU_VRON +1.5V PG_1V_EN VDDCI ISL6264 +VGPU_CORE (20A) +1V (DP PLL PWR) PG_1.5V_EN P45 +VGPU_IO (4.5A) +1V (3A) +1.8V +3V_D VDDR3 +1.5V_GPU (10A) +5V PG_1.5V_EN VDDR4 MOS (AO3413) P22 MOS (AO4710) P43 P47 MOS (AO6402) P43 dGPU_PWROK BJT dGPU_PWR_EN# AO3413 P22 +1.8V_GPU (3A) +3_D (0.5A) MOS P22 +5_GPU Thermal Follow Chart Power States B +3.3V +1.5V_GPU VDDR1 G9334ADJ & MOS ISL62872 P44 +1.5V_SUS POWER PLANE VOLTAGE DESCRIPTION CONTROL SIGNAL VIN +10V~+19V MAIN POWER ALWAYS ALWAYS +VCCRTC +3V~+3.3V RTC POWER ALWAYS ALWAYS +3VPCU +3.3V EC POWER ALWAYS ALWAYS +5VPCU +5V CHARGE POWER ALWAYS ALWAYS +15V +15V CHARGE PUMP POWER ALWAYS ALWAYS +3V_S5 +3.3V LAN/BT/CIR POWER S5_ON S0-S5 +5V_S5 +5V USB POWER S5_ON S0-S5 +5V +5V HDD/ODD/Codec/TP/CRT/HDMI POWER MAINON S0 +3V +3.3V PCH/GPU/Peripheral component POWER MAINON S0 +1.5VSUS +1.5V CPU/SODIMM CORE POWER SUSON S0-S3 +0.75V_DDR_VTT +0.75V SODIMM Termination POWER MAINON S0 ACTIVE IN +VGFX_AXG variation Internal GPU POWER GFX_ON S0 +1.8V +1.8V CPU/PCH/Braidwood POWER MAINON S0 +1.5V +1.5V MINI CARD/NEW CARD POWER MAINON S0 MAINON S0 B NTC Thermal Protection CPU CORE PWR H_ORICHOT# H/W Throttling PM_THRMTRIP# CPU 3V/5 V SYS PWR SYS_SHDN# WIRE-AND SML1ALERT# FAN Driver PCH FAN SM-Bus C C +1.1V_VTT +1.05V or +1.1V CPU VTT POWER +1.05V +1.05V PCH CORE POWER MAINON S0 +VCC_CORE variation CPU CORE POWER VRON S0 LCDVCC +3.3V LCD POWER LVDS_VDDEN S0 +5V_GPU +5V SWITCHABLE PWM IC POWER +GPU_CORE +0.9V~+1.1V GPU CORE POWER +GPU_IO +0.9V~+1.1V +1.5V_GPU +1.5V +1.8V_GPU +1V dGPU_PWR_EN# EC CPUFAN# Discrete enable +3V_D Discrete enable GPU I/O POWER PG_GPUIO_EN Discrete enable VRAM CORE POWER PG_1.5V_EN Discrete enable +1.8V GPU_CRE/LVDS/PLL POWER +1.5V_GPU Discrete enable +1V DP/PEG POWER PG_1V_EN Discrete enable D D Quanta Computer Inc PROJECT : ZR7 Size Document Number Date: Monday, February 22, 2010 Rev 3B PWR Status & GPU PWR CRL & THRM Sheet of 49 CLK GEN L40 595@PBY160808T-181Y-N/2A/180ohm_6 +VDDIO_CLK C697 C698 11/19 Change U39 PN .1u/16V_4 L41 BLM18AG601SN1D/200mA/600ohm_6 C494 C720 4.7u/10V_8 1u/16V_4 1u/16V_4 R598 10 CLK_ICH_14M VDD_DOT VDD_SRC VDD_CPU VDD_27 VDD_REF CLK_SDATA CLK_SCLK 31 32 SDA SCL C707 33_4 CPU_SEL 30 REF_0/CPU_SEL 33p/50V_4 XTAL_IN 28 XTAL_IN XTAL_OUT 27 12 21 26 33 C Y5 14.318MHz C701 33p/50V_4 IDT: AL003197001 (ICS9LVS3197AKLFT) Realtek: AL000890000 (RTM890N-632-GRT) Silego: AL000595000 (SLG8LV595VTR) CPU_CLK select B C702 C695 C700 1u/16V_4 1u/16V_4 10u/Y5V_8 10u/Y5V_8 D U39 17 24 29 20mil +3V_CLK C723 +1.05V C696 1u/16V_4 R617 *585@0_6 +3V 80mA(20mil) C719 D 1u/16V_4 L36 PBY160808T/2A/180ohm_6 150mA(30mil) +1.5V_CLK +1.5V VDD_SRC_I/O VDD_CPU_I/O DOT_96 DOT_96# 27M 27M_SS CLK_BUF_DREFCLK CLK_BUF_DREFCLK# CLK_VGA_27M_SS SRC_1/SATA SRC_1#/SATA# SRC_2 SRC_2# 10 11 13 14 XTAL_OUT *CPU_STOP# 16 VSS_DOT VSS_27 VSS_SATA VSS_SRC VSS_CPU VSS_REF GND CPU_1 CPU_1# CPU_0 CPU_0# 20 19 23 22 T46 T45 CKPWRGD/PD# 25 CK_PWRGD_R R595 C718 9/16 10 10 27M_CLK 18 CLK_27M_SS 18 *ES@33_4 *ES@10p/50V/COG_4 CLK_BUF_PCIE_3GPLL 10 CLK_BUF_PCIE_3GPLL# 10 CLK_BUF_DREFSSCLK 10 CLK_BUF_DREFSSCLK# 10 C R579 10K_4 +3V CLK_BUF_BCLK 10 CLK_BUF_BCLK# 10 ICS9LVS3197AKLFT/SLG8LV595V +3V SMBus Place each 0.1uF cap as close as possible to each VDD IO pin Place the 10uF caps on the VDD_IO plane 15 18 CLK Enable +3V B +1.05V R406 10 ICH_SMBDATA R603 C722 10K_4 *10p/50V/COG_4 CLK_SDATA CPU_SEL R578 1K/F_4 2.2K_4 CLK_SDATA CK_PWRGD_R 14,15,27 R599 *10K_4 Q27 2N7002D 39 VR_PWRGD_CK505# R577 100K/F_4 +3V Q48 2N7002D R407 A 10 ICH_SMBCLK CPU_SEL 2.2K_4 CPU0/1=133MHz (default) CLK_SCLK A CLK_SCLK Quanta Computer Inc 14,15,27 Q28 2N7002D CPU0/1=100MHz PROJECT : ZR7 Size Document Number Rev 3B Clock Generator Date: Monday, February 22, 2010 Sheet of 49 AR@ > ARD CPU ARRANDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) CF@ > CFD CPU ES@ > External VGA SKU ARRANDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG) AR@ > ARD CPU CF@ > CFD CPU Processor Compensation Signals 8 8 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 D24 G24 F23 H23 8 8 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 D25 F24 E23 G23 FDI_TX#[0] FDI_TX#[1] FDI_TX#[2] FDI_TX#[3] FDI_TX#[4] FDI_TX#[5] FDI_TX#[6] FDI_TX#[7] D22 C21 D20 C18 G22 E20 F20 G19 FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7 FDI_FSYNC0_R FDI_FSYNC1_R F17 E17 FDI_INT_R C17 FDI_LSYNC0_R FDI_LSYNC1_R F18 D17 FDI_TX[0] FDI_TX[1] FDI_TX[2] FDI_TX[3] FDI_TX[4] FDI_TX[5] FDI_TX[6] FDI_TX[7] FDI_FSYNC[0] FDI_FSYNC[1] FDI_INT FDI_LSYNC[0] FDI_LSYNC[1] PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] 750/F_4 PEG_RXN[0 15] 16 PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15 J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30 PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15 L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26 CPEG_TXN0 CPEG_TXN1 CPEG_TXN2 CPEG_TXN3 CPEG_TXN4 CPEG_TXN5 CPEG_TXN6 CPEG_TXN7 CPEG_TXN8 CPEG_TXN9 CPEG_TXN10 CPEG_TXN11 CPEG_TXN12 CPEG_TXN13 CPEG_TXN14 CPEG_TXN15 C245 C635 C248 C232 C235 C230 C236 C221 C627 C618 C620 C607 C622 C609 C624 C611 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15 L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25 CPEG_TXP0 CPEG_TXP1 CPEG_TXP2 CPEG_TXP3 CPEG_TXP4 CPEG_TXP5 CPEG_TXP6 CPEG_TXP7 CPEG_TXP8 CPEG_TXP9 CPEG_TXP10 CPEG_TXP11 CPEG_TXP12 CPEG_TXP13 CPEG_TXP14 CPEG_TXP15 C238 C634 C253 C227 C237 C224 C233 C220 C628 C619 C621 C608 C623 C610 C625 C612 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 ES@.1u/10V_4 PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15 20/F_4 H_COMP3 AT23 R522 20/F_4 H_COMP2 AT24 R123 49.9/F_4 H_COMP1 G16 R520 49.9/F_4 H_COMP0 AT26 AH24 T40 PCIE 16X Use reverse type (at GPU side) H_CATERR# 11 AK14 AT15 H_PECI H_PROCHOT# 39 H_PROCHOT# AN26 COMP3 COMP2 COMP1 COMP0 SKTOCC# CATERR# PECI PROCHOT# PEG_RXP[0 15] 16 AK15 11 PM_THRMTRIP# BCLK BCLK# THERMTRIP# BCLK_ITP BCLK_ITP# PEG_CLK PEG_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# SM_DRAMRST# SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] PM_EXT_TS#[0] PM_EXT_TS#[1] H_CPURST# ES@ > External VGA SKU AP26 AL15 PM_SYNC AN14 PEG_TXN[0 15] 16 AK13 8,35 PM_DRAM_PWRGD 10,11,16,25,27,31,36 PLTRST# 8 FDI_FSYNC0 FDI_FSYNC1 FDI_INT 8 FDI_LSYNC0 FDI_LSYNC1 Clarksfield/Auburndale R220 1.5K/F_4 H_VTTPWRGD AM15 T28 AM26 CPU_PLTRST# SI 2/5 Modified PEG_TXP[0 15] 16 B Thermaltrip protect AN27 11 H_PWRGOOD R278 R545 AR@0_4 AR@0_4 FDI_FSYNC0_R FDI_FSYNC1_R R543 AR@0_4 FDI_INT_R R546 R544 AR@0_4 AR@0_4 FDI_LSYNC0_R FDI_LSYNC1_R R277 R561 R556 R563 R559 EV@1K_4 EV@1K_4 EV@1K_4 EV@1K_4 EV@1K_4 VTT PWR_Good AL14 R211 750/F_4 RESET_OBS# PM_SYNC VCCPWRGOOD_1 VCCPWRGOOD_0 SM_DRAMPWROK VTTPWRGOOD TAPPWRGOOD A16 B16 AR30 AT30 CLK_CPU_BCLK 11 CLK_CPU_BCLK# 11 T30 T34 D E16 D16 A18 A17 CLK_PCIE_3GPLL 10 CLK_PCIE_3GPLL# 10 DPLL_REF_SSCLK_R DPLL_REF_SSCLK#_R R496 R500 R495 R499 F6 AL1 AM1 AN1 AR@0_4 AR@0_4 EV@0_4 EV@0_4 Layout Note: Place these resistors near Processor CPU_DDR3_DRAMRST# 35 SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 AN15 AP15 R182 R184 R195 100/F_4 24.9/F_4 130/F_4 R224 10K_4 R210 10K_4 PM_EXTTS#0 14 TCK TMS TRST# TDI TDO TDI_M TDO_M DBR# AT28 AP27 +1.1V_VTT XDP_PREQ# AN28 AP28 AT27 XDP_TCLK XDP_TMS XDP_TRST# AT29 AR27 AR29 AP29 XDP_TDI_R XDP_TDO_R XDP_TDI_M XDP_TDO_M AN25 H_DBR#_R AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23 XDP_OBS0 XDP_OBS1 XDP_OBS2 XDP_OBS3 XDP_OBS4 XDP_OBS5 XDP_OBS6 XDP_OBS7 T27 T102 T31 T37 T103 T106 T104 T105 T107 R229 *SHORT_4 XDP_DBRST# C 1/7 modify BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] T26 T29 T24 T32 T38 T33 T39 T41 RSTIN# Clarksfield/Auburndale AR@ > ARD CPU CF@ > CFD CPU B Processor pull-up VTT Rail Values are Arrandale VTT=1.05V Clarksfield VTT=1.1V +1.1V_VTT JTAG MAPPING 2/4 modify XDP_TDI_R +1.1V_VTT +3V DPLL_REF_SSCLK 10 DPLL_REF_SSCLK# 10 PM_EXTTS#1 15 PRDY# PREQ# PWR MANAGEMENT C 8 8 8 8 DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] E22 D21 D19 D18 G21 E19 F21 G18 FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7 PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] Intel(R) FDI 8 8 8 8 DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] R498 K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31 R523 CLOCKS B24 D23 B23 A22 49.9/F_4 JTAG & BPM DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 PCI EXPRESS GRAPHICS 8 8 DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] R497 THERMAL A24 C23 B22 A21 DMI DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 B26 A26 B27 A25 MISC D 8 8 U37B PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS DDR3 MISC U37A XDP_TDO H_CATERR# H_PROCHOT# H_CPURST# R529 R174 R521 R233 51/F_4 49.9/F_4 68_4 *68_4 XDP_TMS XDP_TDI_R XDP_PREQ# R232 R537 R527 *51_4 *51_4 *51_4 XDP_TCLK XDP_TRST# R213 R524 *51/F_4 51/F_4 XDP_TDI R538 *SHORT_4 R536 *0_4 XDP_TDO_M XDP_TDO R535 *SHORT_4 XDP_TDI_M 8,39 DELAY_VR_PWRGOOD Q22 FDV301N 36 MPWROK +1.5V_CPUVDDQ R223 STUFF -> R535, R538, R528 NO STUFF -> R536, R534 CPU Only STUFF -> R538, R536 NO STUFF -> R535, R534, R528 GMCH Only STUFF -> R534, R528 NO STUFF -> R535, R536, R538 2K/F_4 PM_THRMTRIP# *SHORT_4 Scan Chain (Default) H_VTTPWRGD 11 PM_THRMTRIP# *0_4 R528 1u/10V_4 R226 1K_4 A R534 XDP_TDO_R C383 Q21 MMBT3904 U20 R209 1K_4 TC7SH08FU R214 1.1K/F_4 A PM_DRAM_PWRGD SYS_SHDN# 38,46 pull-up 56ohm close to PCH R212 3K/F_4 Use a voltage divider with VDDQ (1.5 V) rail (ON in S3) and resistor combination of 1.1K/F (to VDDQ)/3K/F (to GND) to convert to processor VTT level Quanta Computer Inc Note: CRB uses a 3.3 V (always ON) rail with k and k combination PROJECT : ZR7 Size Document Number Date: Monday, February 22, 2010 Rev 3B ARRANDALE/CLARKSFIELD 1/4 Sheet of 49 ARRANDALE/CLARKSFIELD PROCESSOR (DDR3) U37D U37C 14 M_A_DQ[63:0] M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 C B 14 14 14 14 14 14 M_A_BS#0 M_A_BS#1 M_A_BS#2 M_A_CAS# M_A_RAS# M_A_WE# A10 C10 C7 A7 B10 D10 E10 A8 D8 F10 E6 F7 E9 B7 E7 C6 H10 G8 K7 J8 G7 G10 J7 J10 L7 M6 M8 L9 L6 K8 N8 P9 AH5 AF5 AK6 AK7 AF6 AG5 AJ7 AJ6 AJ10 AJ9 AL10 AK12 AK8 AL7 AK11 AL8 AN8 AM10 AR11 AL11 AM9 AN9 AT11 AP12 AM12 AN12 AM13 AT14 AT12 AL13 AR14 AP14 SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] AC3 AB2 U7 SA_BS[0] SA_BS[1] SA_BS[2] AE1 AB3 AE9 SA_CAS# SA_RAS# SA_WE# DDR SYSTEM MEMORY A D SA_CK[0] SA_CK#[0] SA_CKE[0] AA6 AA7 P7 M_A_CLK0 14 M_A_CLK0# 14 M_A_CKE0 14 SA_CK[1] SA_CK#[1] SA_CKE[1] Y6 Y5 P6 M_A_CLK1 14 M_A_CLK1# 14 M_A_CKE1 14 SA_CS#[0] SA_CS#[1] AE2 AE8 M_A_CS#0 14 M_A_CS#1 14 SA_ODT[0] SA_ODT[1] AD8 AF9 M_A_ODT0 14 M_A_ODT1 14 SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7] B9 D7 H7 M7 AG6 AM7 AN10 AN13 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] C9 F8 J9 N9 AH7 AK9 AP11 AT13 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] C8 F9 H9 M9 AH8 AK10 AN11 AR13 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 M_A_DM[7:0] 14 M_A_DQS#[7:0] 14 M_A_DQS[7:0] 14 M_A_A[15:0] 14 15 15 15 15 15 15 Clarksfield/Auburndale SB_CK[0] SB_CK#[0] SB_CKE[0] W8 W9 M3 M_B_CLK0 15 M_B_CLK0# 15 M_B_CKE0 15 SB_CK[1] SB_CK#[1] SB_CKE[1] V7 V6 M2 M_B_CLK1 15 M_B_CLK1# 15 M_B_CKE1 15 SB_CS#[0] SB_CS#[1] AB8 AD6 M_B_CS#0 15 M_B_CS#1 15 SB_ODT[0] SB_ODT[1] AC7 AD1 M_B_ODT0 15 M_B_ODT1 15 SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7] D4 E1 H3 K1 AH1 AL2 AR4 AT8 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] D5 F4 J4 L4 AH2 AL4 AR5 AR8 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] C5 E3 H4 M5 AG2 AL5 AP5 AR7 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 M_B_DQ[63:0] M_B_BS#0 M_B_BS#1 M_B_BS#2 M_B_CAS# M_B_RAS# M_B_WE# B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2 J6 J3 G1 G5 J2 J1 J5 K2 L3 M1 K5 K4 M4 N5 AF3 AG1 AJ3 AK1 AG4 AG3 AJ4 AH4 AK3 AK4 AM6 AN2 AK5 AK2 AM4 AM3 AP3 AN5 AT4 AN6 AN4 AN3 AT5 AT6 AN7 AP6 AP8 AT9 AT7 AP9 AR10 AT10 SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] AB1 W5 R7 SB_BS[0] SB_BS[1] SB_BS[2] AC5 Y7 AC6 SB_CAS# SB_RAS# SB_WE# DDR SYSTEM MEMORY - B 15 D M_B_DM[7:0] 15 C M_B_DQS#[7:0] 15 M_B_DQS[7:0] 15 M_B_A[15:0] 15 B Clarksfield/Auburndale A A Channel A DQ[11,15,19,32,35,42,46,48,54,60], DM[5] Requires minimum 12mils spacing with all other signals, including data signals Channel B DQ[11,16,18,19,36,42,51,55,56,57,60,61,62] Requires minimum 12mils spacing with all other signals, including data signals Quanta Computer Inc PROJECT : ZR7 Size Document Number Rev 3B ARRANDALE/CLARKSFIELD 2/4 Date: Monday, February 22, 2010 Sheet of 49 C667 AR@330u/2V_7343 C325 AR@22u/6.3V_8 C324 AR@22u/6.3V_8 + C251 + C666 AR@330u/2V_7343 330u/2V_7343 C326 AR@10u/6.3V_8 C327 AR@10u/6.3V_8 Add it for discrete only R215 EV@0_4 +1.1V_VTT C239 22U/6.3V_8 C240 22U/6.3V_8 +1.1V_VTT VTT Rail Values are Arrandale VTT=1.05V Clarksfield VTT=1.1V C242 22u/6.3V_8 1/7 modify R125 R129 *SHORT_4 *SHORT_4 J24 J23 H25 SENSE LINES + GRAPHICS VIDs 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 VAXG_SENSE VSSAXG_SENSE AR22 AT22 VCC_AXG_SENSE VSS_AXG_SENSE GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6] AM22 AP22 AN22 AP23 AM23 AP24 AN24 GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VID4 GFX_VID5 GFX_VID6 GFX_VR_EN GFX_DPRSLPVR GFX_IMON AR25 AT25 AM24 VTT1_45 VTT1_46 VTT1_47 (15mils) PSI# AN33 H_PSI# H_PSI# VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] PROC_DPRSLPVR AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34 H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 H_DPRSLPVR H_VID0 39 H_VID1 39 H_VID2 39 H_VID3 39 H_VID4 39 H_VID5 39 H_VID6 39 H_DPRSLPVR G15 H_VTTVID1 C649 22u/6.3V_8 C241 22u/6.3V_8 C297 22u/6.3V_8 39 ARD:3A CFD:6A 44 EV@1K_4 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1 +1.5V_CPUVDDQ VTT0_59 VTT0_60 VTT0_61 VTT0_62 P10 N10 L10 K10 VTT1_63 VTT1_64 VTT1_65 VTT1_66 VTT1_67 VTT1_68 J22 J20 J18 H21 H20 H19 VCCPLL1 VCCPLL2 VCCPLL3 L26 L27 M26 C337 C246 C252 C341 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 C340 C331 C271 1U/6.3V_4 22U/6.3V_8 22U/6.3V_8 C 1.1V VTT1_48 VTT1_49 VTT1_50 VTT1_51 VTT1_52 VTT1_53 VTT1_54 VTT1_55 VTT1_56 VTT1_57 VTT1_58 + C257 330u/2V_7343 +1.1V_VTT C641 C643 10U/6.3V_8 10U/6.3V_8 VTT Rail Values are Arrandale VTT=1.05V Clarksfield VTT=1.1V C211 1u/10V_4 C309 22u/6.3V_8 D CF@ > CFD CPU C646 22u/6.3V_8 K26 J27 J26 J25 H27 G28 G27 G26 F26 E26 E25 44 44 44 44 44 44 44 44 44 GFX_ON 44 GFX_DPRSLPVR GFX_IMON 44 R236 - 1.5V RAILS 1.1V RAIL POWER VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44 AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 +VTT_43 J15 +VTT_44 C655 C652 C638 C328 C660 C640 C639 C662 C616 C288 VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 PEG & DMI A AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 FDI B VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8 VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32 AT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16 AL21 AL19 AL18 AL16 AK21 AK19 AK18 AK16 AJ21 AJ19 AJ18 AJ16 AH21 AH19 AH18 AH16 1.8V C VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 CPU CORE SUPPLY AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 POWER + 330u/2V_7343 22A CPU VIDS + 330u/2V_7343 C304 U37G 18A DDR3 +1.1V_VTT C636 C637 22U/6.3V_8 22U/6.3V_8 C243 C244 C204 C210 C209 22U/6.3V_8 4.7U/6.3V_6 2.2U/6.3V_6 1U/6.3V_4 1U/6.3V_4 0.6A +1.8V B 39 Clarksfield/Auburndale VTT_SELECT T12 H_VTTVID1=Low, 1.1V H_VTTVID1=High, 1.05V ISENSE AN35 I_MON R178 SENSE LINES C272 AR@ > ARD CPU CF@ > CFD CPU GRAPHICS 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 1u/10V_4 1u/10V_4 +VGFX_AXG +VCC_CORE ARD:48A CFD:52A C310 C661 C314 C249 C648 C653 C650 C358 C318 C644 C268 C332 C296 C300 C283 C651 C642 C659 C654 C362 C645 C322 C323 C281 C647 C284 C273 C658 C308 C258 ARRANDALE/CLARKSFIELD PROCESSOR (GRAPHICS POWER) VTT Rail Values are Arrandale VTT=1.05V Clarksfield VTT=1.1V U37F CPU Core Power D ARRANDALE/CLARKSFIELD PROCESSOR (POWER) POWER AR@ > ARD CPU CF@ > CFD CPU VCC_SENSE VSS_SENSE VTT_SENSE VSS_SENSE_VTT 100/F_4 AJ34 AJ35 B15 A15 R181 100/F_4 VTT_SENSE VSS_SENSE_VTT 39 +VCC_CORE VCCSENSE 39 VSSSENSE 39 T98 T100 H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 H_DPRSLPVR H_PSI# R539 R540 R541 R542 R240 R239 R532 R533 R235 R234 R526 R519 R530 R531 R244 R243 R525 R518 1K_4 *1K/F_4 1K_4 *1K/F_4 1K_4 *1K/F_4 *1K/F_4 1K_4 *1K/F_4 1K_4 1K_4 *1K/F_4 *1K/F_4 1K_4 1K_4 *1K/F_4 *1K/F_4 1K_4 Note: For Validating IMVP VR R6451 should be STUFF and R2N1 NO_STUFF +1.1V_VTT VTT Rail Values are Arrandale VTT=1.05V Clarksfield VTT=1.1V A HFM_VID : Max 1.4V LFM_VID : Min 0.65V Quanta Computer Inc PROJECT : ZR7 Clarksfield/Auburndale Size Document Number Date: Monday, February 22, 2010 Rev 3B ARRANDALE/CLARKSFIELD 3/4 (PWR) Sheet of 49 ARRANDALE/CLARKSFIELD PROCESSOR (GND) D C B U37I VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30 K27 K9 K6 K3 J32 J30 J21 J19 H35 H32 H28 H26 H24 H22 H18 H15 H13 H11 H8 H5 H2 G34 G31 G20 G9 G6 G3 F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11 E8 E5 E2 D33 D30 D26 D9 D6 D3 C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11 B8 B6 B4 A29 A27 A23 A9 U37E RSVD32 RSVD33 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 AP25 AL25 AL24 AL22 AJ33 AG9 M27 L28 J17 H17 G25 G17 E31 E30 14,35 VREF_DQ_DIMM0 15,35 VREF_DQ_DIMM1 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 SA_DIMM_VREF SB_DIMM_VREF RSVD11 RSVD12 RSVD13 RSVD14 CFG0 CFG3 CFG4 CFG7 VSS AT35 AT1 AR34 B34 B2 B1 A35 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 AM30 AM28 AP31 AL32 AL30 AM31 AN29 AM32 AK32 AK31 AK28 AJ28 AN30 AN32 AJ32 AJ29 AJ30 AK30 H16 B19 A19 T22 T13 T14 T99 T97 A20 B20 U9 T9 AC9 AB9 C1 A3 J29 J28 A34 A33 C35 B35 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD_TP_86 AJ13 AJ12 RSVD34 RSVD35 AH25 AK26 RSVD36 RSVD_NCTF_37 AL26 AR2 RSVD38 RSVD39 AJ26 AJ27 RSVD_NCTF_40 RSVD_NCTF_41 RSVD_NCTF_42 RSVD_NCTF_43 NCTF U37H AT20 AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12 AR9 AR6 AR3 AP20 AP17 AP13 AP10 AP7 AP4 AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11 AM8 AM5 AM2 AL34 AL31 AL23 AL20 AL17 AL12 AL9 AL6 AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11 AJ8 AJ5 AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13 AH9 AH6 AH3 AG10 AF8 AF4 AF2 AE35 ARRANDALE/CLARKSFIELD PROCESSOR( RESERVED, CFG) RESERVED D AP1 AT2 AT3 AR1 RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53 RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57 RSVD58 AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32 RSVD_TP_59 RSVD_TP_60 KEY RSVD62 RSVD63 RSVD64 RSVD65 E15 F15 A2 D15 C15 AJ15 AH15 C T25 T35 RSVD15 RSVD16 RSVD17 RSVD18 RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75 RSVD19 RSVD20 RSVD21 RSVD22 RSVD_NCTF_23 RSVD_NCTF_24 RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85 RSVD26 RSVD27 RSVD_NCTF_28 RSVD_NCTF_29 RSVD_NCTF_30 RSVD_NCTF_31 VSS AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3 M_A_CLK2 14 M_A_CLK2# 14 M_A_CKE2 14 M_A_CS#2 14 M_A_ODT2 14 M_A_CLK3 14 M_A_CLK3# 14 M_A_CKE3 14 M_A_CS#3 14 M_A_ODT3 14 V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9 M_B_CLK2 15 M_B_CLK2# 15 M_B_CKE2 15 M_B_CS#2 15 M_B_ODT2 15 M_B_CLK3 15 M_B_CLK3# 15 M_B_CKE3 15 M_B_CS#3 15 M_B_ODT3 15 AP34 B T21 AP34 can be NC on CRB; EDS/DG suggestion to GND Clarksfield/Auburndale Clarksfield/Auburndale Clarksfield/Auburndale VTT Rail Values are Arrandale VTT=1.05V Clarksfield VTT=1.1V Processor Strapping A CFG0 (PCI-Epress Configuration Select) CFG3 (PCI-Epress Static Lane Reversal) CFG4 (Embended Display Port Presence) Single PEG Normal Operation Bifurcation enabled Lane Numbers Reversed DEFAULT Use reverse type +1.1V_VTT R185 3.01K/F_4 CFG4 R183 *3.01K R227 3.01K/F_4 CFG0 R219 *3.01K_NC R198 *3.01K/F_4 CFG3 R192 3.01K/F_4 CFG7 R203 *3.01K/F_4 A Enabled; An external Display port Disabled; No Physical Display Port device is connected to the Embedded attached to Embedded Diplay Port Display port The Clarkfield processor's PCI Express interface may not meet PCI Express 2.0 jitter specifications Intel recommends placing a 3.01K +/- 5% pull down resistor to VSS on CFG[7] pin for both rPGA and BGA components This pull down resistor should be removed when this issue is fixed Quanta Computer Inc PROJECT : ZR7 Size Date: Document Number Rev 3B ARRANDALE/CLARKSFIELD 4/4 Monday, February 22, 2010 Sheet of 49 AR@ > ARD CPU CF@ > CFD CPU IV@ > iGPU only AR@ > ARD CPU IBEX PEAK-M (DMI,FDI,GPIO) CF@ > CFD CPU AR@ > ARD CPU IBEX PEAK-M (LVDS,DDI) Arrandale only U40C BD22 BH21 BC20 BD18 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 R566 +1.05V DMI0TXN DMI1TXN DMI2TXN DMI3TXN 49.9/F_4 DMI0TXP DMI1TXP DMI2TXP DMI3TXP BH25 DMI_ZCOMP BF25 DMI_IRCOMP AR@0_4 AR@0_4 AR@0_4 AR@0_4 AR@0_4 AR@0_4 AR@0_4 AR@0_4 FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12 FDI_TXP0_R FDI_TXP1_R FDI_TXP2_R FDI_TXP3_R FDI_TXP4_R FDI_TXP5_R FDI_TXP6_R FDI_TXP7_R R568 R555 R553 R564 R549 R573 R570 R551 AR@0_4 AR@0_4 AR@0_4 AR@0_4 AR@0_4 AR@0_4 AR@0_4 AR@0_4 FDI_INT BJ14 FDI_FSYNC0 BF13 FDI_FSYNC1 BH13 FDI_LSYNC0 BJ12 FDI_LSYNC1 BG14 R557 *CF@1K_4 R276 *CF@1K_4 R560 *CF@1K_4 R562 *CF@1K_4 R558 *CF@1K_4 FDI_INT FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7 4 4 4 4 FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7 4 4 4 4 U40D 23 INT_LVDS_BRIGHT FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1 AR@2.37K/F_4 LVD_IBG AP39 AP41 LVD_IBG LVD_VBG R300 R305 AR@0_4 AR@0_4 LVD_VREFH LVD_VREFL AT43 AT42 LVD_VREFH LVD_VREFL SYS_PWROK M6 SYS_RESET# SYS_PWROK B17 RSV_ICH_LAN_RST# PWROK K5 MEPWROK A10 LAN_RST# D9 4,35 PM_DRAM_PWRGD DRAMPWROK C16 36 ICH_RSMRST# SUS_PWR_ACK_R RSMRST# M1 DNBSWON# 36 PCH_ACIN P5 R345 *0_4 ACIN_R PM_BATLOW# PM_RI# CLKRUN# / GPIO32 PWRBTN# P7 ACPRESENT / GPIO31 A6 BATLOW# / GPIO72 F14 RI# J12 PCIE_WAKE# Y1 23 INT_TXLOUT0+ 23 INT_TXLOUT1+ 23 INT_TXLOUT2+ SUS_STAT# T49 SLP_S5#_R T59 P8 SUSCLK / GPIO62 F3 SLP_S5# / GPIO63 E4 SLP_S4# H7 SUSC# 36 SLP_S3# P12 SUSB# SLP_M# TP23 PMSYNCH SLP_LAN# / GPIO29 K8 ICH_SUSCLK INT_TXLOUT0+ INT_TXLOUT1+ INT_TXLOUT2+ BB48 BA50 AY49 AV48 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 INT_CRT_BLU INT_CRT_GRN INT_CRT_RED N2 LVDSB_CLK# LVDSB_CLK AY53 AT49 AU52 AT53 LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 AY51 AT48 AU50 AT51 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3 AA52 AB53 AD53 CRT_BLUE CRT_GREEN CRT_RED Y53 Y51 *0_4 DAC_IREF T55 R317 1K/F_4 PM_SYNC PM_SLP_LAN# AP48 AP47 V51 V53 SDVO_STALLN SDVO_STALLP BJ48 BG48 SDVO_INTN SDVO_INTP BF45 BH45 AD48 AB51 D CRT_HSYNC CRT_VSYNC DAC_IREF CRT_IRTN SDVO_CTRLCLK SDVO_CTRLDAT BG44 BJ44 AU38 T109 T108 DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38 INT_HDMITX2N_R INT_HDMITX2P_R INT_HDMITX1N_R INT_HDMITX1P_R INT_HDMITX0N_R INT_HDMITX0P_R INT_HDMICLK-_R INT_HDMICLK+_R SDVO_CTRLCLK 24 SDVO_CTRLDAT 24 INT_HDMI_HPD C408 C409 C411 C410 C453 C452 C426 C425 IV@.1u/10V_4 IV@.1u/10V_4 IV@.1u/10V_4 IV@.1u/10V_4 IV@.1u/10V_4 IV@.1u/10V_4 IV@.1u/10V_4 IV@.1u/10V_4 INT_HDMITX2N INT_HDMITX2P INT_HDMITX1N INT_HDMITX1P INT_HDMITX0N INT_HDMITX0P INT_HDMICLKINT_HDMICLK+ 24 24 24 24 24 24 24 24 24 C DDPC_CTRLCLK DDPC_CTRLDATA Y49 AB49 DDPC_AUXN DDPC_AUXP DDPC_HPD BE44 BD44 AV40 DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36 DDPD_CTRLCLK DDPD_CTRLDATA CRT_DDC_CLK CRT_DDC_DATA T51 T53 DDPB_AUXN DDPB_AUXP DDPB_HPD IV@ > iGPU only AR@ > ARD CPU U50 U52 DDPD_AUXN DDPD_AUXP DDPD_HPD BC46 BD46 AT38 DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36 36 23 INT_HSYNC 23 INT_VSYNC BJ10 F6 LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 23 INT_CRT_DDCCLK 23 INT_CRT_DDCDAT SLP_M# R354 LVDSA_CLK# LVDSA_CLK 36 23 INT_CRT_BLU 23 INT_CRT_GRN 23 INT_CRT_RED BJ46 BG46 SDVO_CTRLCLK SDVO_CTRLDATA BB47 BA52 AY48 AV47 25,27 SDVO_TVCLKINN SDVO_TVCLKINP L_CTRL_CLK L_CTRL_DATA INT_TXLOUT0INT_TXLOUT1INT_TXLOUT2- CLKRUN# 36 SUS_STAT# / GPIO61 SUS_PWR_DN_ACK / GPIO30 B 36 WAKE# System Power Management T6 INT_TXLCLKOUT- AV53 INT_TXLCLKOUT+ AV51 23 INT_TXLOUT023 INT_TXLOUT123 INT_TXLOUT2- 10/20 Modify Unstuff XDP_DBRST# L_DDC_CLK L_DDC_DATA R307 C XDP_DBRST# L_BKLTCTL L_CTRL_CLK AB46 L_CTRL_DATA V48 23 INT_TXLCLKOUT23 INT_TXLCLKOUT+ L_BKLTEN L_VDD_EN Y48 AR@10K_4 AR@10K_4 R329 R333 +3V T48 T47 AB48 Y45 23 INT_LVDS_EDIDCLK 23 INT_LVDS_EDIDDATA FDI_FSYNC0 INT_LVDS_BLON INT_LVDS_DIGON 23 INT_LVDS_BLON 23 INT_LVDS_DIGON Digital Display Interface DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 BE22 BF21 BD20 BE18 DMI0RXP DMI1RXP DMI2RXP DMI3RXP FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 R567 R554 R552 R565 R548 R572 R569 R550 LVDS 4 4 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 BD24 BG22 BA20 BG20 DMI0RXN DMI1RXN DMI2RXN DMI3RXN FDI_TXN0_R FDI_TXN1_R FDI_TXN2_R FDI_TXN3_R FDI_TXN4_R FDI_TXN5_R FDI_TXN6_R FDI_TXN7_R CRT 4 4 BC24 BJ22 AW20 BJ20 FDI 4 4 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI 4 4 D BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12 R place close to PCH R596 AR@150_4 INT_CRT_BLU R587 AR@150_4 INT_CRT_GRN R584 AR@150_4 INT_CRT_RED B IbexPeak-M_R1P0 T58 IbexPeak-M_R1P0 System PWR_OK AR@ > ARD CPU A R132 AR@100K_4 INT_LVDS_BLON R119 AR@100K_4 INT_LVDS_DIGON CLKRUN# R586 8.2K_4 PM_RI# R372 10K_4 XDP_DBRST# R352 1K_4 PM_BATLOW# R632 8.2K_4 PCIE_WAKE# R365 1K_4 PM_SLP_LAN# R369 *10K_4 SUS_PWR_ACK_R R619 10K_4 ACIN_R R346 10K_4 ICH_RSMRST# +3V R160 AR@4.7K_4 SDVO_CTRLCLK R161 AR@4.7K_4 SDVO_CTRLDAT +3V_S5 R650 +3V_S5 C778 10K_4 RSV_ICH_LAN_RST# R662 10K_4 SYS_PWROK R670 10K_4 DELAY_VR_PWRGOOD need PU 2K to +3V PU at power side *.1u/10V_4 A +3V SYS_PWROK DELAY_VR_PWRGOOD U45 PCH Pull-high/low R695 4,39 Quanta Computer Inc PWROK_EC 36 100K_4 TC7SH08FU PROJECT : ZR7 Size Document Number Date: Monday, February 22, 2010 Rev 3B IBEX PEAK-M 1/6 Sheet of 49 RTC Circuitry C758 15p/50V_4 +VCCRTC +3VPCU CR1 Y6 RTC_X1 RTC_X2 15p/50V_4 D R677 1K_4 C14 R663 +VCCRTC C753 1u/10V_4 1M_4 SRTC_RST# D17 SM_INTRUDER# A16 J2 *SHORT_PAD PCH_INVRMEN A14 FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3 D33 B33 C32 A32 FWH4 / LFRAME# C34 LDRQ0# LDRQ1# / GPIO23 A34 F34 RTCX1 RTCX2 RTCRST# SRTCRST# INTRUDER# INTVRMEN SERIRQ LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 27,36 27,36 27,36 27,36 LPC_LFRAME# 27,36 D R327 10K_4 +3V AB9 IRQ_SERIRQ 36 C784 1u/10V_4 RTC_RST# SRTC_RST# 20K/F_4 R405 B13 D13 LPC J1 *SHORT_PAD U40A 32.768KHZ RTC C757 C768 1u/10V_4 BAT54C R647 10M_4 RTC_RST# 20K/F_4 R676 VCCRTC_1 RTC_N01 R674 *22K/F_6 Q55 R673 *MMBT3904 A30 ACZ_SYNC D29 29 SPKR SPKR P1 ACZ_RST# HDA_BCLK HDA_SYNC SPKR C30 HDA_RST# G30 HDA_SDIN0 F30 HDA_SDIN1 *68.1K/F_4 29 PCH_AZ_CODEC_SDIN0 RTC_N03 BT1 +5V_S5 ACZ_BIT_CLK Internal weak pull-down VCCVRM=>+1.8V (default) external pull-up VCCVRM=>+1.5V R678 E32 *150K/F_6 F32 RTC_CONN IHDA VCCRTC_2 HDA_SYNC (PCH strap pin) HDA_SDIN2 HDA_SDIN3 ACZ_SDOUT B29 HDA_SDO PCH_GPIO33 H32 HDA_DOCK_EN# / GPIO33 PCH_GPIO13 J30 HDA_DOCK_RST# / GPIO13 *10K_4 M3 29 PCH_AZ_CODEC_SYNC R653 33_4 ACZ_SYNC JTAG_TMS K1 JTAG_TDI R659 33_4 ACZ_RST# R658 33_4 ACZ_SDOUT J2 J4 29 PCH_AZ_CODEC_RST# 29 PCH_AZ_CODEC_SDOUT R654 29 PCH_AZ_CODEC_BITCLK 33_4 +3VPCU ACZ_BIT_CLK R575 *10K_4 C759 *27p/50V_4 10/29 Modify P/N to 2M 12/7 Modify P/N to 4M B +3V JTAG_TDO TRST# SPI_CLK_R BA2 SPI_CLK SPI_CS0# SPI_CS0#_R AV3 SPI_CS1# AY3 SPI_SI_R AY1 SPI_SO_R AV1 AK7 AK6 AK11 AK9 SATA_TXN0_C SATA_TXP0_C C483 C484 01u/25V_4 01u/25V_4 SATA_RXN0 SATA_RXP0 SATA_TXN0 SATA_TXP0 28 28 28 28 SATA1RXN SATA1RXP SATA1TXN SATA1TXP AH6 AH5 AH9 AH8 SATA_TXN1_C SATA_TXP1_C C495 C487 01u/25V_4 01u/25V_4 SATA_RXN1 SATA_RXP1 SATA_TXN1 SATA_TXP1 28 28 28 28 SATA2RXN SATA2RXP SATA2TXN SATA2TXP AF11 AF9 AF7 AF6 SATA3RXN SATA3RXP SATA3TXN SATA3TXP AH3 AH1 AF3 AF1 SATA4RXN SATA4RXP SATA4TXN SATA4TXP AD9 AD8 AD6 AD5 SATA5RXN SATA5RXP SATA5TXN SATA5TXP AD3 AD1 AB3 AB1 SATAICOMPO SATAICOMPI SPI_CS1# SATALED# SPI_MOSI SATA0GP / GPIO21 SPI_MISO SATA1GP / GPIO19 10/20 Modify Note: SATA port2/3 may not be available on all PCH sku (HM55 support port only) C AF16 SATAICOMP AF15 +3V R608 3.3K/F_4 CE# SCK SI SO VDD HOLD# WP# VSS W25X32QVSSIG SPI_CLK_R C463 37.4/F_4 T3 +1.05V SATA_ACT# 32 PCH_ODD_EN 28 Y9 R338 10K_4 +3V V1 R594 10K_4 +3V INTVRMEN Integrated 1.05V VRM Enable / Disable = Integrated VRM is enabled = Integrated VRM is disabled SPI_MOSI TPM Functionality Disable = Enabled = Disable SPKR Reboot option at power-up = Default Mode (Internal weak Pull-down) = No Reboot Mode with TCO Disabled HDA_DOCK_EN Flash Descriptor Security Override #/GPIO33 = Flash Descriptor Security will be overridden = Security measure defined in the Flash Descriptor will be enabled GNT0#, GNT1# (0,0) = LPC (1,0) = PCI R685 330K_6 PCH_INVRMEN +3V R618 *1K_4 SPI_SI_R +3V R611 +VCCRTC 11/5 R338 and R594 Modify to 10K ohm *1K/F_4SPKR R370 *1K/F_4 R382 *10K_4 B 12/1 Add by SPI ROM PCH_GPIO33 +3V U41 SPI_CS0#_R SPI_CLK_R SPI_SI_R SPI_SO_R R319 IbexPeak-M_R1P0 PCH Strap Pin Configuration Table-1 PCH SPI JTAG_TCK K3 C JTAG R652 SPI +3V_S5 HDA Bus SATA 1/7 Change P/N by ME SATA0RXN SATA0RXP SATA0TXN SATA0TXP +3V R613 3.3K/F_4 Boot BIOS Strap 10 PCI_GNT0# R360 *1K_4 PCI_GNT0# R708 1K_4 10 PCI_GNT1# R363 *1K_4 PCI_GNT1# R709 1K_4 10,23 PWM_SELECT# R364 *1K/F_4 (0,1) = Reserved NAND (1,1) = SPI C717 1u/10V_4 GNT2#/ GPIO53 *22p_4 ESI compatible mode is for server platforms only GNT3#/ GPIO55 Top-Block Swap Override = Top Block Swap Mode = Default Mode (Internal pull-up) NV_ALE IntelR Anti-Theft Technology HDD Data Protection (Intel AT-d) Enable = Enabled = Disabled (Default) 10 DMI Termination Voltage DMI termination voltage Weak internal pull-up Do not pull low 10 11 NV_CLE GPIO8 GPIO15 A ESI Strap (Server Only) GPIO27 Reserved Reserved On-Die PLL Voltage Regulator This signal has a weak internal pull up NOTE: This signal should not be pulled low = Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality = Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality = Disables the VccVRM = Enables the internal VccVRM to have a clean supply for analog rails 10 PCI_GNT3# R628 NV_ALE *1K/F_4 +1.8V NV_CLE R295 *1K/F_4 +1.8V RSV_GPIO8 R380 R371 11 *10K/F_4 R296 CR_WAKE# 11 PCH_GPIO27 10K_4 +3V_S5 *1K_4 R341 1K_4 R324 A +3V_S5 *10K_4 Quanta Computer Inc PROJECT : ZR7 Size Document Number Date: Monday, February 22, 2010 Rev 3B IBEX PEAK-M 2/6 Sheet of 49 IV@ > iGPU only EV@ > dGPU only SW@ > iGPU & dGPU Switch U40B U40E F48 K45 F36 H53 PCI_GNT0# PCI_GNT1# 9,23 PWM_SELECT# PCI_GNT3# 27 PCI_SERR# PCI_PERR# E44 E50 PCI_IRDY# PCI_PAR PCI_DEVSEL# PCI_FRAME# A42 H44 F46 C46 PCI_PLOCK# D49 K6 T54 R612 22_4 R358 CLK_PCI_FB R606 22_4 22_4 27 CLK_LPC_DEBUG T56 36 B41 K53 A36 A48 PCI_RST# T63 B PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH# CLK_PCI_775 PCI_STOP# PCI_TRDY# D41 C48 ICH_PME# M7 PCI_PLTRST# D5 CLK_LPC_DEBUG_C CLK_PCI_PCCARD CLK_PCI_775_C CLK_PCI_FB_C N52 P53 P46 P51 P48 NV_WR#0_RE# NV_WR#1_RE# NV_WE#_CK0 NV_WE#_CK1 PIRQA# PIRQB# PIRQC# PIRQD# USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P REQ0# REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 GNT0# GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5 PCIRST# SERR# PERR# IRDY# PAR DEVSEL# FRAME# PLOCK# USBRBIAS# STOP# TRDY# USBRBIAS CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 BA32 BB32 BD32 BE32 BF33 BH33 BG32 BJ32 BD3 AY6 NV_ALE NV_CLE NV_RCOMP R574 27 27 27 27 WLAN *32.4/F_4 PCIE_RX6PCIE_RX6+ PCIE_TX6PCIE_TX6+ C451 C450 PCIE_TXN6_C PCIE_TXP6_C 1u/10V_4 1u/10V_4 OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 BA34 AW34 BC34 BD34 AT34 AU34 AU36 AV36 AV7 AY8 AY5 BG34 BJ34 BG36 BJ36 AV11 BF5 H18 J18 A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22 A22 C22 G24 H24 L24 M24 A24 C24 B25 SML0ALERT# / GPIO60 SML0CLK PERN3 PERP3 PETN3 PETP3 USBP1USBP1+ 33 33 USBP3USBP3+ USBP4USBP4+ USBP5USBP5+ 33 33 33 33 27 27 AK48 AK47 MB USB CLK_PCIE_REQ0# T50 T48 USB/B-USB1-3 BLUETOOTH AM43 AM45 EHCI1 CLK_PCIE_REQ1#_R USB_BIAS R651 23 23 33 33 27 27 33 33 31 31 27 27 U4 Reserve Touch Screen USB port6/7 may not be available on all PCH sku (HM55 support 12port only) USBP8USBP8+ USBP9USBP9+ USBP10USBP10+ USBP11USBP11+ USBP12USBP12+ USBP13USBP13+ P9 AM47 AM48 27 CLK_PCH_SRC2# 27 CLK_PCH_SRC2 R616 27 PCIE_CLK_REQ2# Camera *SHORT_4 CLK_PCIE_REQ2#_R USB/B-USB1-2 Touch Screen USB/B-USB1-1 N4 AH42 AH41 CLK_PCIE_REQ3# EHCI2 A8 Card Reader AM51 AM53 Mini Card (WLAN) CLK_PCIE_REQ4# M9 USB_OC6# USB_OC7# SML1ALERT# / GPIO74 SML1CLK / GPIO58 SML1DATA / GPIO75 PERN5 PERP5 PETN5 PETP5 PERN6 PERP6 PETN6 PETP6 CL_CLK1 CL_DATA1 CL_RST1# PEG_A_CLKRQ# / GPIO47 PERN7 PERP7 PETN7 PETP7 CLKOUT_PEG_A_N CLKOUT_PEG_A_P PERN8 PERP8 PETN8 PETP8 CLKOUT_PCIE0N CLKOUT_PCIE0P PCIECLKRQ0# / GPIO73 CLKOUT_PCIE1N CLKOUT_PCIE1P PCIECLKRQ1# / GPIO18 CLKOUT_PCIE2N CLKOUT_PCIE2P B9 RSV_SMBALERT# H14 ICH_SMBCLK C8 ICH_SMBDATA J14 RSV_SML0ALERT# C6 SMB_CLK_ME0 G8 SMB_DATA_ME0 ICH_SMBCLK ICH_SMBDATA D SMB_CLK_ME0 25 SMB_DATA_ME0 25 M14 RSV_SML1ALERT# E10 SMB_CLK_ME1 G12 SMB_DATA_ME1 T13 CL_CLK1 T11 CL_DATA1 T9 CL_RST1# H1 PEG_CLKREQ#_R R336 *0_4 SML1ALERT# 11,34,36 CL_CLK1 27 SW@ > iGPU & dGPU Switch CL_DATA1 27 CL_RST1# 27 R620 AD43 AD45 SW@0_4 PEG_CLKREQ# AN4 AN2 CLK_PCIE_3GPLL# CLK_PCIE_3GPLL AT1 CLKOUT_DP_N / CLKOUT_BCLK1_N AT3 CLKOUT_DP_P / CLKOUT_BCLK1_P DPLL_REF_SSCLK# DPLL_REF_SSCLK CLKOUT_DMI_N CLKOUT_DMI_P CLKIN_DMI_N CLKIN_DMI_P CLKIN_BCLK_N CLKIN_BCLK_P CLKIN_DOT_96N CLKIN_DOT_96P CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P PCIECLKRQ2# / GPIO20 CLKOUT_PCIE3N CLKOUT_PCIE3P REFCLK14IN USB_OC0# 33 USB_OC1# 33 T51 T53 H6 AK53 AK51 25 CLK_PCIE_LOM# 25 CLK_PCIE_LOM USB_OC4_5# 16 CLK_PCIE_VGA# 16 CLK_PCIE_VGA 16 AW24 BA24 CLK_BUF_PCIE_3GPLL# CLK_BUF_PCIE_3GPLL AP3 AP1 CLK_BUF_BCLK# CLK_BUF_BCLK F18 E18 CLK_BUF_DREFCLK# CLK_BUF_DREFCLK AH13 AH12 CLK_BUF_DREFSSCLK# CLK_BUF_DREFSSCLK P41 CLK_ICH_14M C 11/27 Modify C699,C703 to 27pF R699 EV@0_4 AR@27p/50V_4 PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK J42 CLK_PCI_FB AH51 AH53 XTAL25_IN XTAL25_OUT AF38 XCLK_RCOMP R312 T45 BOARD_ID1 P43 BOARD_ID2 T42 BOARD_ID3 C699 CLKOUT_PCIE4N CLKOUT_PCIE4P XTAL25_IN XTAL25_OUT PCIECLKRQ4# / GPIO26 XCLK_RCOMP R581 33 R591 25 CLK_PCIE_LAN_REQ# *SHORT_4 T62 T61 PCIE_CLK_REQB# P13 CLKOUT_PCIE5N CLKOUT_PCIE5P CLKOUTFLEX0 / GPIO64 PCIECLKRQ5# / GPIO44 CLKOUT_PEG_B_N CLKOUT_PEG_B_P CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67 IbexPeak-M_R1P0 Y4 AR@25MHz AR@1M_4 90.9/F_4 22.6/F_4 AJ50 AJ52 USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4_5# SML0DATA PERN4 PERP4 PETN4 PETP4 Port1 and port9 can be used on debug mode T57 T52 D25 N16 J16 F16 L16 E14 G16 F12 T15 SMBDATA PERN2 PERP2 PETN2 PETP2 SMBus AU30 AT30 AU32 AV32 SMBCLK Link 11/18 Delete R597, C444,C445 for cancel 3G function SMBALERT# / GPIO11 PCI-E* 3G AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6 AU2 AW30 BA30 BC30 BD30 CLK_PCIE_REQ5# PME# PLTRST# AV9 BG8 PERN1 PERP1 PETN1 PETP1 Controller NVRAM NV_RB# PCIE_TXN1_C PCIE_TXP1_C 1u/10V_4 1u/10V_4 F51 A46 B45 M53 NV_RCOMP C679 C680 BG30 BJ30 BF29 BH29 PEG PCI_REQ0# PCI_REQ1# dGPU_SELECT# PCI_REQ3# NV_ALE NV_CLE GLAN PCIE_RX1PCIE_RX1+ PCIE_TX1PCIE_TX1+ AR@27p/50V_4 C703 +1.05V 11/5 Add R699 connect XTAL25_IN to Gnd 11/18 Modify N50 dGPU_EDIDSEL# R349 23 dGPU_SELECT# G38 H51 B37 A44 NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15 25 25 25 25 From CLK BUFFER C PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# C/BE0# C/BE1# C/BE2# C/BE3# NV_DQS0 NV_DQS1 AY9 BD1 AP15 BD8 Clock Flex J50 G42 H47 G34 NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3 USB D AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PCI H40 N34 C44 A38 C36 J34 A40 D45 E36 H48 E40 C40 M48 M45 F53 M40 M43 J36 K48 F40 C42 K46 M51 J52 K51 L34 F42 J40 G46 F44 M47 H36 10K_4 B 23,24 +3V IbexPeak-M_R1P0 +3V_S5 +3V CLK_PCIE_REQ0# CLK_PCIE_REQ3# CLK_PCIE_REQ4# CLK_PCIE_REQ5# PCIE_CLK_REQB# *10K_4 BOARD_ID1 R355 10K_4 R373 *10K_4 BOARD_ID2 R359 10K_4 R347 *10K_4 BOARD_ID3 R342 10K_4 R387 +3V_S5 RP1 USB_OC7# USB_OC6# USB_OC4_5# +3V_S5 +3V_S5 10 USB_OC0# USB_OC1# USB_OC2# USB_OC3# R390 10K_4 dGPU_SELECT# R593 10K_4 CLK_PCIE_REQ1#_R R376 R348 R669 R665 8.2K_4 8.2K_4 8.2K_4 10K_4 PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCIE_CLK_REQ2# 1u/10V_4 RP4 PCI_PLTRST# +3V A PLTRST# 4,11,16,25,27,31,36 PCI_PIRQD# PCI_REQ1# PCI_FRAME# PCI_TRDY# U25 TC7SH08FU 10 R389 PCI_REQ3# PCI_PIRQB# PCI_REQ0# PCI_PIRQH# 8.2K_10P8R IV@ > iGPU only 2.2K_4 SMB_CLK_ME1 Q26 *2N7002D R700 +3V_S5 0_4 11/25 Modify R649 R385 R340 R404 R403 R627 R622 C524 +3V 36 2ND_MBCLK 11/18 Modify +3V 8.2K_10P8R +3V_S5 +3V Main Board ID R374 10K_4 10K_4 10K_4 10K_4 10K_4 10K_4 10K_4 10K_4 2.2K_4 2.2K_4 2.2K_4 2.2K_4 RSV_SMBALERT# RSV_SML0ALERT# RSV_SML1ALERT# ICH_SMBCLK ICH_SMBDATA SMB_CLK_ME0 SMB_DATA_ME0 +3V R381 36 2ND_MBDATA EV@ > dGPU only +3V_S5 2.2K_4 R353 R634 R357 R362 R600 Q29 *2N7002D A SMB_DATA_ME1 100K_4 +3V RP5 R388 PCI_PIRQC# PCI_PIRQA# PCI_STOP# PCI_IRDY# *0_4 +3V 10 R701 +3V_S5 PCI_PERR# PCI_PLOCK# PCI_DEVSEL# PCI_SERR# 0_4 11/25 Modify R624 IV@10K_4 PEG_CLKREQ#_R R625 EV@10K/F_4 Quanta Computer Inc 8.2K_10P8R PROJECT : ZR7 Size Document Number Rev 3B IBEX PEAK-M 3/6 Date: Monday, February 22, 2010 Sheet 10 of 49 11/12 PR90,PQ22 no stuff +0.75V_DDR_VTT +1.5V_CPUVDDQ PR90 *220_8 46 MAINON_DIS_G 46 MAINON_DIS_G PQ22 *DMN601K-7 PQ23 DMN601K-7 +1.5V_SUS A PR89 22_8 A C291 *.1u_4 C282 *.1u_4 C279 *.1u_4 C274 *.1u_4 +1.5V_CPUVDDQ B B +3V_S5 +3V_S5 +1.5V_SUS R138 R399 *10K/F_4 *1K_4 R637 DDR3_DRAMRST# 14,15 PM_DRAM_PWRGD 4,8 Q15 *1.5K/F_4 Q25 *2N7002D +1.5V_CPUVDDQ 3 R395 *10K/F_4 U26 *TC7SH08FU R638 *750/F_4 11 RST_GATE# 1 Q24 *PDTC143TT R137 0_4 *BSS138 CPU_DDR3_DRAMRST# PWRGD_1.5VCPU 42 C C +1.5V_SUS +1.5V_SUS +1.5V_SUS R140 *1K/F_4 R115 *1K/F_4 PQ16 +SMDDR_VREF_DQ0 14 10/29 Modify +SMDDR_VREF_DQ1 15 Q14 RST_GATE# Q13 R135 *1K/F_4 38,42,46 MAIND RST_GATE# *AO6402A R114 *1K/F_4 0_1206 +1.5V_CPUVDDQ 6A/maximum 7,14 VREF_DQ_DIMM0 R167 0_1206 *A03402 *A03402 R170 10/29 Modify 7,15 VREF_DQ_DIMM1 D D Quanta Computer Inc PROJECT : ZR7 Size Document Number Rev 3B S3 power saving Date: Monday, February 22, 2010 Sheet 35 of 49 EC(KBC) L18 AR@ > ARD CPU EV@ > dGPU Only SW@ > iGPU & dGPU Switch +A3VPCU PBY160808T-250Y-N/3A/25ohm_6 +3V 30mil +3VPCU C382 C381 1u/10V_4 10u/6.3V_6 I/O ADDRESS SETTING(KBC) E775AGND D8 0.03A(30mils) +3VPCU_EC 2.2_6 C357 4.7U/6.3V_6 1u/10V_4 *.1u/16V_4 1u/10V_4 *.1u/16V_4 1u/10V_4 U19 D C348 C347 4.7U/6.3V_6 1u/10V_4 C376 VDD C392 102 C391 AVCC C377 19 46 76 88 115 BAS316 C379 VCC1 VCC2 VCC3 VCC4 VCC5 R231 E775AGND 10u/6.3V_8 ICMNT C386 C388 SIO_RCIN# D7 11 SIO_EXT_SCI# C360 *10p/50V/COG_4 BAS316 EC_FPBACK# 23 EC_FPBACK# 33 PLTRST# USBON# IRQ_SERIRQ NOCIR# T23 4,10,11,16,25,27,31 29 124 PLTRST# USBON# 123 IRQ_SERIRQ 125 11 SIO_EXT_SMI# C 34 34 34 34 34 34 34 34 MX0 MX1 MX2 MX3 MX4 MX5 MX6 MX7 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 MY0 MY1 MY2 MY3 MY4 MY5 MY6 MY7 MY8 MY9 MY10 MY11 MY12 MY13 MY14 MY15 MY16 MY17 37 MBCLK 37 MBDATA 10 2ND_MBCLK 10 2ND_MBDATA 34 TPCLK 34 TPDATA PCH_ACIN 33 BT_POWERON# 40,41,42,45,46 MAINON 10/20 B T18 CR_PSAVE ICH_SUSCLK R263 R264 *20M_6 Y1 GPIO24/LDRQ GPIO10/LPCPD LREST GPIO67/PWUREQ SERIRQ GPIO65/SMI 53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33 MBCLK MBDATA 2ND_MBCLK 2ND_MBDATA 70 69 67 68 GPIO17/SCL1 GPIO22/SDA1 GPIO73/SCL2 GPIO74/SDA2 TPCLK TPDATA PCH_ACIN 72 71 10 11 12 13 GPIO37/PSCLK1 GPIO35/PSDAT1 GPIO26/PSCLK2 GPIO27PSDAT2 GPIO25/PSCLK3 GPIO12/PSDAT3 77 GPIO00/32KCLKIN 79 LPC ECSCI/GPIO54 MY0 MY1 MY2 MY3 MY4 MY5 MY6 MY7 MY8 MY9 MY10 MY11 MY12 MY13 MY14 MY15 MY16 MY17 E775_32KX2 GPIO KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7 KBSOUT0/JENK KBSOUT1/TCK KBSOUT2/TMS KBSOUT3/TDI KB KBSOUT4/JEN0 KBSOUT5/TDO KBSOUT6/RDY KBSOUT7 KBSOUT8 KBSOUT9/SDP_VIS KBSOUT10/P80_CLK KBSOUT11/P80_DAT KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62 KBSOUT15/GPIO61/XOR_OUT GPIO60/KBSOUT16 GPIO57/KBSOUT17 PS/2 GPIO02 NPCE781 *33K/F_4 *32.768KHz *15p/50V_4 C431 PBY160808T-250Y-N/3A/25ohm_6 *15p/50V_4 GPIO01/TB2 GPIO03 GPIO06/IOX_DOUT GPIO07 GPIO23/SCL3 GPIO30/CIRTX2 GPIO31/SDA3 GPIO32/D_PWM GPIO33/H_PWM GPIO36 GPIO40/F_PWM GPIO42/TCK GPIO43/TMS GPIO44/TDI GPIO45/E_PWM GPIO46/CIRRXM/TRST GPO47/SCL4 GPIO50/TDO GPIO51 GPIO52/CIRTX2/RDY GPIO53/SDA4 GPIO81 GPO82/TEST GPO84/TRIST GPIO41 SHBM=0: Enable shared memory with host BIOS GPIO15/A_PWM GPIO21/B_PWM GPIO13/C_PWM GPIO66/G_PWM 32 118 62 81 TEMP_MBAT 37 WL_SW T43 VGA_THERM# 19,20 10/28 84 83 82 ACIN 19,37 NBSWON# 32 LID591# 23,33 SUSB# MXM_SMCLK12 19,20 ACPRN 32 MXM_SMDATA12 19,20 BATLED0# 32 BATLED1# 32 VRON 39 SUSLED# 32 AC_OFF 2ND_MBCLK 2ND_MBDATA DGPU_IDLE# VGA_THERM# ODDLED SW@10K_4 SW@10K_4 2.2K_4 2.2K_4 ODD_EJ R265 *10K_4 R180 *10K_4 10/26 UnStuff A0 A1 A2 VCC GND SCL SDA WP C417 *ACER_ID_EEPROM *.1u/10V_4 CONTRAST 23 NUMLED# 32 PWRLED# 32 CAPSLED# 32 ODD_EJ 32 3G_EN RF_LED# 27,32 *SHORT_4 *SHORT_4 CIRR_X2 HWPG P_SAVE_LED# T16 F_SDI F_SDO F_CS0 F_SCK 86 87 90 92 SPI_SDI_uR SPI_SDO_uR_R SPI_CS0#_uR SPI_SCK_uR_R GPIO55/CLKOUT/IOX_DIN 30 ECDB_CLOCK 85 VCC_POR# R256 47K/F_4 104 VREF_uR R238 *SHORT_4 +A3VPCU 12/7 Change to 512K SPI FLASH(KBC) SPI_SDI_uR R266 +3VPCU R259 22_4 SPI_SDI_uR_R 10K_4 SO SPI_SDO_uR SI SPI_SCK_uR SCK SPI_CS0#_uR 22_4 SPI_SDO_uR 22_4 SPI_SCK_uR VDD HOLD C449 WP 1u/10V_4 CE VSS W25X40BVSSIG P_SAVE_LED# 32 R247 +3VPCU U21 11/09 ICH_RSMRST# SUSC# PWROK_EC RF_EN 27 R261 1/13 Comfirm by vendor mail : If the Southbridge enables 'Long Wait Abort' by default, the flash device should be 50MHz (or faster) R260 T19 100K_4 B SPI_SDI_uR +3V HWPG(KBC) +3VPCU 10/27 Modify R217 10K_4 SM BUS ARRANGEMENT TABLE SM Bus Battery SM Bus PCH 40,45 HWPG_VTT 45 HWPG_1.8V SM Bus 38 SYS_HWPG 44 HWPG_AXF SM Bus HDMI Controller, MMB1, MMB2 and VGA Thermal POWER-ON Switch(KBC) Add BAS316 D12 BAS316 HWPG D14 BAS316 D13 BAS316 D15 BAS316 D16 AR@BAS316 AR@ > ARD CPU D23 EV@BAS316 EV@ > dGPU Only *SHORT_4 42 HWPG_1.5V MMB3 and EEPROM D17 R222 41 HWPG_1.05V C374 E775AGND 11,18 dGPU_PWROK MPWROK INTERNAL KEYBOARD STRIP SET(KBC) A A 10/26 UnStuff SW1 *SWITCH_1.5 NBSWON# D1 *VPORT_6 MY0 R230 +3VPCU *10K_4 Quanta Computer Inc PROJECT : ZR7 Size Document Number Date: Monday, February 22, 2010 Rev 3B WPCE781 & FLASH C +3VPCU U22 MXM_SMCLK12 MXM_SMDATA12 SUSON 42 FANSIG 34 R253 +3V R208 R207 8/11 modify ACER ID(KBC) 1u/6.3V_4 E775AGND 11/25 Modify +3V R425 R428 T20 3G_EN 10K_4 10K_4 MXM_SMCLK12 MXM_SMDATA12 SW@ > iGPU & dGPU Switch 11/09 WLAN_LED# 32 PANEL_ENG 23 +3V *10K_4 *10K_4 ODD_POWER CPUFAN# 34 PANEL_COLOR 23 VIN_ON 37 D/C# 37 S5_ON 38,46 HDMI_HPD_EC# 24 ODD_POWER 28 DNBSWON# WLAN_LED PANEL_ENG R249 R250 R252 R251 11/25 Modify T17 R254 VREF 11/25 Modify unstuff AMP_MUTE# 29 PANEL_COLOR +3VPCU MBCLK MBDATA T15 3G_SW PWROK_EC_uR VCC_POR 10K_4 DGPU_IDLE# 19 RSMRST#_uR FIU R255 1/13 Comfirm by vendor mail : Disabled ('1') if using FWH device on LPC Enabled ('0') if using SPI flash for both system BIOS and EC firmware 10/20 POWER_SAVE 32 DGPU_IDLE# 3G_EN SHBM SML1ALERT# 10,11,34 ICMNT 37 VGA_THERM# 75 73 74 113 14 114 111 GPIO72/IRRX1/SIN2 GPIO70/IRRX2_IRSL0 GPIO71/IRTX/SOUT2 GPIO87/CIRRXM/SIN_CR GPIO34/CIRRXL GPIO16/CIRTX GPO83/SOUT_CR/XORTR D 01u/16V_4 SM BUS PU(KBC) 64 95 93 94 119 109 120 65 66 15 16 17 20 21 22 23 24 25 26 27 28 91 110 112 80 31 117 63 GPIO77/SPI_DI GPO76/SPI_DO/SHBM GPIO75/SPI_SCK SPI 101 105 106 107 GPIO56/TA1 GPIO20/TA2/IOX_DIN GPIO14/TB1 TIMER SMB IR L20 C400 GPIO94/DA0 GPI95/DA1 GPI96/DA2 GPI97 D/A KBRST/GPIO86 54 55 56 57 58 59 60 61 R279 GPIO85/GA20 MX0 MX1 MX2 MX3 MX4 MX5 MX6 MX7 E775_32KX1 *SHORT_4 GPIO11/CLKRUN VCORF 11 122 97 98 99 100 108 96 VCORF_uR 44 *22_4 AGND 121 GPIO90/AD0 GPIO91/AD1 GPIO92/AD2 GPIO93/AD3 GPIO05 GPIO04 A/D 103 CLKRUN# 11 SIO_A20GATE R197 CLK_PCI_775 LFRAME LAD0 LAD1 LAD2 LAD3 LCLK GND1 GND2 GND3 GND4 GND5 GND6 CLK_PCI_775 126 127 128 18 45 78 89 116 9,27 LPC_LFRAME# 9,27 LPC_LAD0 9,27 LPC_LAD1 9,27 LPC_LAD2 9,27 LPC_LAD3 10 CLK_PCI_775 Sheet 36 of 49 VA PL3 HI0805R800R-00_8 PJ2 VDC PQ32 FDD6685 VIN_SRC BAT-V PR129 220K/F_6 PD1 SW1010CPT PR125 220K/F_6 36 VIN_SRC VIN_SRC EC5 *10u/25V_1206 PR30 10/F_6 CH2 CH3 PR28 100K/F_6 +3VPCU VDDSMB 21 VDDP 26 11 33 32 31 30 28 MBDATA MBDATA VCC PD7 *RB500V-40 PR29 2.7_6 BOOT PC28 1u/50V_8 12/30 Modify 88731_DH 10 ACIN SDA UGATE PQ5 AO4468 SCL PHASE ACOK LGATE 0.01_3720 PR136 24 88731_LX 23 PL5 6.8uH BAT-V 19,36 C 25 MBCLK MBCLK PC116 1u/50V_6 PC117 2200p/50V_6 3 VP PC20 10u/25V_1206 PC23 1u/16V_6 CSIN CSSN CH4 +3VPCU NC GND GND GND GND CSSP PU2 CM1293A-04SO PC29 1u/50V_6 27 CSIP +3VPCU PR25 4.7_6 PC32 1u/50V_6 11/16 Modify PU3 footprint C PQ36 DMN601K-7 PC30 1u/16V_6 PR31 10/F_6 VN D/C# EC4 *10u/25V_1206 CSIP_1 CH1 D PR135 10K_6 PQ31 IMD2AT108 VDC PR134 33K_6 CSIP_1 2/5 Add by EMI PC11 2200p/50V_6 PC114 PC111 PC115 EC1 EC2 1u/50V_6 2200p/50V_6 *22u/25V_1210 1u/50V_6 *22u/25V_1210 EC3 *10u/25V_1206 PC13 1u/50V_6 VIN_SRC 9/1 modify PC108 1u/50V_6 PD6 SMAJ20A PC109 1u/50V_6 PC110 1u/50V_6 PL4 HI0805R800R-00_8 TEMP_MBAT POWER_CONN D PR133 0.01/F_7520 PQ30 FDD6685 VA1 1 PD5 SBR1045SP5-13 DCIN 22 DCIN PC105 1u/50V_6 PR33 22K/F_6 B HI0805R800R-00_8 PL2 BAT-V MBAT+ VREF ICOMP VBF VCOMP PC33 *1u/16V_6 36 MBDATA 36 16 BAT-V 1/11 Add PC3100 by EMI PR24 10/F_6 VIN_SRC CSOP_1 BAT-V GND NC 14 PC3100 29 PR12 100_4 PC112 1U/25V_6 PR19 150K_6 *10u/25V_1206 12 ICM BAT-V 15 36 1/11 Add by EMI PR20 39K_6 11/23 Modify VIN_SRC PC35 *0.01u/50V_6 PC34 0.01u/50V_6 36 VIN_ON PQ3 DMN601K-7 A A PC31 3300p/50V_4 PC3101 PC3103 PC3105 PC3107 *10u/25V_1206 *10u/25V_1206 *10u/25V_1206 *10u/25V_1206 PC3102 PC3104 PC3106 PC3108 *10u/25V_1206 *10u/25V_1206 *10u/25V_1206 *10u/25V_1206 PR18 *100K/F_6 PC12 0.01u/50V_6 Quanta Computer Inc PROJECT : ZR7 Size Document Number Date: Monday, February 22, 2010 Rev 3B CHARGER (ISL88731) B VIN PQ33 AOL1413 PR17 100K/F_6 PR11 100_4 MBCLK ICMNT PC36 0.01u/50V_6 +3VPCU PR10 100_4 PC107 10u/25V_1206 PR32 2.21K/F_6 TEMP_MBAT 36 PR13 *0_6 PC8 10u/25V_1206 PC6 47p/50V_6 PC106 2200p/50V_6 PC5 47p/50V_6 NC PD4 RB500V-40 Batt_Conn PC19 *680p/50V_6 PR27 *SHORT_4 GND 9/1 modify 17 CSON NC PL1 HI0805R800R-00_8 TEMP_MBAT PQ4 AO4710 CSOP_1 PC24 1u/50V_6 NC PJ1 18 CSOP ACIN CSON PC104 100p/50V_6 10 PR23 10/F_6 CSOP PC7 0.01u/50V_6 19 PU3 ISL88731A PR34 82.5K/F_6 PR22 *4.7_6 88731_DL PGND PR9 *SHORT_6 20 13 PC26 1u/50V_6 PR26 49.9/F_6 Sheet 37 of 49 MAIND MAIND 35,42,46 PR109 *SHORT_4 VL 2/11 Del PD3 and change PR105 and PR106 4,46 SYS_SHDN# VIN_SRC D PR213 39K/F_4 D VIN_SRC VL Add 100u cap PC192 10u/25V_1206 PR221 *SHORT_4 PC90 1u/16V_6 PC173 1u/50V_6 PR216 *0_4 PR236 *2.2_6 PC175 + 5V_DL PC89 1u/50V_6 330u/6.3V_6X5.7 +3VPCU PQ71 AO4468 PQ72 AO4710 PR225 1/F_6 PD12 SX34 *0_6 10 11 12 200K/F_6 DDPWRGD_R 13 5V_EN 14 15 16 37 36 BYP OUT1 FB1 ILIM1 PGOOD1 EN1 DH1 LX1 PAD PAD PU9 RT8206B PL13 2.2uH_14A REFIN2 ILIM2 OUT2 SKIP# PGOOD2 EN2 DH2 LX2 32 31 30 29 28 27 26 25 PR114 182K/F_6 REFIN2 3V_LX changed on 11/19 LDOREFIN LDO VIN NC ONLDO VCC TON REF +5VPCU PC177 1u/50V_6 PC199 *2200p/50V_6 PR112 *SHORT_4 6.21A change to 330u/6.3V_6x5.7 PR118 *2.2_6 SKIP DDPWRGD_R 3V_EN C + change to 330u/6.3V_6x5.7 PR115 5V_LX OCP : 8A PR214 *SHORT_6 PC99 *2200p/50V_6 PQ70 AO4710 PC178 1u/50V_6 PD9 SX34 PR224 1/F_6 PR215 PR218 *0_4 *SHORT_4 3V_DL PC166 1u/50V_6 PC91 10u/25V_1206 PR227 *0_6 PC182 1u/50V_6 PD10 CHN217UPT VL SKIP PR212 *SHORT_6 PC98 1u/50V_6 OCP:8A PC183 1u/50V_6 PR219 *SHORT_6 +3VPCU +15V_ALWP pad 2/12 09 PR108 100K/F_4 Iocp=8-(2.48/2)=6.67A Vth=6.67A*15mOhm=94.714mV R(Ilim)=(94.714mV*10)/5uA ~191K PR233 +15V REF L(ripple current) ohm change to shot =(19-3.3)*3.3/(2.2u*0.5M*19) ~2.48A PR226 *SHORT_6 PD11 CHN217UPT *0_6 PC180 1u/16V_6 B PR116 PR113 *0_6 B DDPWRGD_R SYS_HWPG 36 PR217 22_8 *SHORT_4 PC196 1u/50V_6 +15V +5V_S5 +5VPCU +3V_S5 +3VPCU +5VPCU VIN_SRC PC169 330u/6.3V_6X5.7 1 changed on 11/19 PC97 10u/25V_1206 PC94 2200p/50V_4 BST1 DL1 PVCC NC GND PGND DL2 BST2 PQ69 AO4468 PL14 2.2uH_14A C 5V_DH 17 18 19 20 21 22 23 24 Iocp=10-(4.18/2)=7.91A Vth=7.91A*14.2mOhm=112.322mV R(Ilim)=(112.322mV*10)/5uA ~220K PAD PAD PAD +5VPCU PC100 1u/50V_6 3V_DH PR107 PR105 150K_4 35 34 33 5.64A L(ripple current) =(19-5)*5/(2.2u*0.4M*19) ~4.18A OCP: 10A PR110 *0_4 PC92 1u/50V_6 REF PC172 01u/16V_4 PR106 390K_4 3V_EN 5V_EN 100u/25V_6.3X5.8 PR111 0_4 PR211 0_4 PR220 *SHORT_4 PC198 PC174 4.7u/10V_8 3V5V_EN PC187 PC93 2200p/50V_6 *10u/25V_1206 PC188 1u/50V_6 + +3VPCU MAIND PR188 1M_6 MAIND 4 1 PC160 PQ68 DMN601K-7 2200p/50V_4 PQ66 DMN601K-7 PQ24 AO3404 2.79A 2.83A +5V PQ26 +3V +3V_S5 AO4496 PQ67 DMN601K-7 PQ65 DTC144EU PR205 1M_6 2 PQ25 AO4496 3 S5_ON 36,46 A PQ27 AO4496 S5D S5D PR196 22_8 PR190 22_8 PR206 1M_6 0.23A Quanta Computer Inc +5V_S5 2.85A PROJECT : ZR7 Size Document Number Rev 3B SYSTEM 5V/3V (RT8206) Date: Monday, February 22, 2010 Sheet 38 of 49 A [PWM] PR71, PR72, PR73, PR74, PR75, PR76, and PR77 deleted VIN 4,8 DELAY_VR_PWRGOOD VR_PWRGD_CK505# PC65 10u/25V_1206 PC145 10u/25V_1206 + PC61 1u/50V_6 PC132 100u/25V_6X7.7 PC141 2200p/50V_6 PQ57 AOL1448 8/4 EMI request 62882_DH1 changed on 11/19 20A D D +VCC_CORE +3V PL10 PQ59 AOL1718 PQ58 AOL1718 62882_LX1 PR78 *SHORT_6 PR82 0.36uH VIN + PC71 5/12 Change pr144 from 10K to 1.91K UGATE1 BOOT1 147K/F_6 H_PROCHOT# RBIAS PHASE1 VR_TT# LGATE1a PR55 *4.02K/F_4 PC58 *.01u/16V/X7R_4 H_VID3 H_VID4 H_VID5 H_VID6 H_VID1 32 H_VID2 33 H_VID3 34 H_VID4 35 H_VID5 36 H_VID6 37 ISEN1 38 DPRSLPVR 39 VID1 VID2 PC135 0.22u/10V_4 VCCP ISL62882 PR185 25 0_4 PC153 10u/25V_1206 PC155 100u/25V_6X7.7 VID6 changed on 11/19 VR_ON DPRSLPVR UGATE2 FB2 VSSP2 ISEN2 PQ60 AOL1718 0.36uH PR88 62882_DL2 + PC72 *2.2/F_6 PC149 22u/25V_6 330u/2V_7343 28 PR162 PR167 26 PC73 *1000p/50V_6 27 *SHORT_4 *SHORT_4 B 62882_ISEN2 10 PC52 PL11 FB 62882_LX2 PQ61 AOL1718 29 30 20A +VCC_CORE PC70 1u/6.3V_4 LGATE2 8/4 EMI request +5V_S5 PC150 1u/6.3V_4 VID5 PC133 22p/50V_4 B PQ62 AOL1448 62882_DH2 VID4 PHASE2 PC74 10u/25V_1206 8/10 modify BOOT2 PR56 412K/F_4 PC75 1u/50V_6 VSUM- VID3 PR183 2.2_6 PR67 *10K/F_4 PC154 2200p/50V_6 62882_ISEN1 VID0 PR175 499/F_4 PR177 100K/F_4 + 22 11 31 H_DPRSLPVR 62882_DL1B 24 H_VID0 C VIN LGATE1b VRON VRON 10K/F_4 1/F_4 PR65 H_VID2 PR173 H_VID1 VSUM62882_DL1A 23 3.65K/F_4 PC148 22u/25V_6 21 H_VID0 10K/F_4 PR170 NTC VSSP1 PR61 VSUM+ PR181 2.2_6 Close to Phase Inductor 19 PSI# PR180 *470K_4_NTC *SHORT_4 PR66 10K/F_4 PR174 *SHORT_4 PR164 H_PSI# PR171 20 PR165 *499/F_4 40 PAD 7/16 modify 36 PC68 *1000p/50V_6 PGOOD CLK_EN# 17 16 PU8 VIN VDD 41 +1.1V_VTT 330u/2V_7343 *SHORT_8 PC63 1u/6.3V_4 C *2.2/F_6 PC66 22u/25V_6 PR77 10_6 PR163 1.91K/F_4 11/16 Modify PU8 footprint PR62 PR172 1.91K/F_4 +5V_S5 150p/50V_4 COMP PC134 0.22u/10V_4 VSUM8/10 modify PR54 8.06K/F_4 VW IMON 18 PR182 9.76K/F_4 ISUM+ ISUM- 10K/F_4 PR161 3.65K/F_4 VSUM- PR166 1/F_4 PR60 10K/F_4 VSSSENSE 5/12 Change pc92 rom 0.33u_4 to 0.22u_6 5/12 stuff pc26 0.068u_6 15 14 2.8K/F_4 RTN VSEN 12 PR57 13 5/12 Change pr24 rom 2.87K to 2.8K PR52 VSUM+ PC146 0.033u/16V_4 PC54 1000p/50V_4 PC144 0.22u/10V_6 PC55 390p/50V_4 PC143 0.068u/25V_6 VSUM+ PR58 562/F_4 I_MON PC136 10p/50V/COG_4 PR168 82.5/F_4 *27.4_4 PR59 2.61K/F_4 PR63 +VCC_CORE PC59 PC142 VSSSENSE PR64 *SHORT_4 PR71 *SHORT_4 330p/50V_4 PC137 330p/50V_4 Parallel PC138 01u/16V_4 PC60 PR70 *27.4_4 1000p/50V_4 2700p/50V_4 VCCSENSE 6 A PR178 11K/F_4 PR184 10K_6_NTC PR179 *SHORT_4 A Panasonic ERT-J1VR103J VSUM- 5/12 Change pr34 rom 1K to 1.24K PR176 1.24K/F_4 PC139 *1000p/50V_4 PR169 *100/F_4 PC140 1u/10V_4 Close to Phase Inductor Quanta Computer Inc Load Line setting to 2mV/A PROJECT : ZR7 Size 5/12 un-stuff PC76,PR140 Rev 3B CPU Core ( ISL62882) Date: Document Number Sheet Monday, February 22, 2010 39 of 49 [PWM] VIN SP@ > Operation P/N +5V_S5 PD8 RB500V-40 +3V PC45 *.1u/50V_6 PR45 V2@10K/F_6 15 EN/DEM BOOT 13 16 TON UGATE 12 VOUT PHASE 11 VDD OC 10 36,45 HWPG_VTT C PC40 1u/16V_6 LGATE GND PGND NC TPAD 17 PGOOD 14 stuff on 1/13 VDDP FB PC126 2200p/50V_4 PQ52 AOL1448 PC128 1u/50V_6 PC125 PC42 1u/50V_6 10u/25V_1206 PC41 *10u/25V_1206 changed on 11/19 PL8 2.2uH UGATE-VTT PHASE-VTT PR155 1.1VVTT_SRC 3.3K/F_6 MAINON OCP: 18A 1.1V/15A PR157 *SHORT_6 PU7 UP6111AQDD PC123 4.7u/6.3V_6 PC124 + 1u/16V_6 LGATE-VTT +1.1V_VTT PL7 2.2uH + PR151 *4.7_6 PQ49 AOL1718 36,41,42,45,46 PR158 1M/F_6 PR159 *SHORT_6 D PR152 2.2/F_6 PR156 10_6 D PC37 330u/2V_7343 C PC122 *680p/50V_6 NC PC43 330u/2V_7343 PC120 1u/50V_6 PC121 10u/10V_8 PC44 *1000p/50V_6 VOUT=(1+R1/R2)*0.75 R1 PR42 *SHORT_6 PR154 CSP@4.7K/F_6 PC127 *33p/50V_6 CSP@ > Operation P/N (ARD&CFD) VTT_FB SP@ BOM change notice B R2 AO1718 Rdson=3~4.3mOhm L(ripple current) =(19-1.05)*1.05/(1u*272k*19) ~3.64A TON=3.85p*RTON*Vout/(Vin-0.5) Frequency=Vout/(Vin*TON) PR153 10K/F_6 Arrandale (1.05V) Clarksfield(1.1V) B R1 = 4.02K (CS24023F928) R1 = 4.75K (CS24753F919) VIN 4.3m*18=RILIM*20uA RILIM=3.87K - 3.92K TON=3.85p*1M*1/(Vin-0.5) Frequency=1/(0.0036767)=272K A A C930 C931 C932 C933 C934 10u/25V_1206 *10u/25V_1206 10u/25V_1206 10u/25V_1206 *10u/25V_1206 Quanta Computer Inc 2/11 Add C930~C934 by monitor test PROJECT : ZR7 Size Document Number Rev 3B +VTT (UP6111A) Date: Monday, February 22, 2010 Sheet 40 of 49 VIN +5V_S5 PD13 RB500V-40 PU11 UP6111AQDD +3V PC194 *.1u/50V_6 PR240 *10K/F_6 EN/DEM BOOT 13 16 TON UGATE 12 VOUT PHASE 11 VDD OC 10 FB C PC102 1u/16V_6 36 HWPG_1.05V PGOOD VDDP LGATE GND PGND NC TPAD 17 14 NC PC197 1u/50V_6 PQ73 AO4468 15 PC101 2200p/50V_4 PC200 1u/50V_6 1.05V/8A OCP: 10A PC202 10u/25V_1206 PL16 2.2uH_8A UGATE-1.05V PHASE-1.05V PR121 +1.05V 5.76K/F_6 8/24 modify MAINON PC205 4.7u/6.3V_6 PC203 1u/16V_6 C LGATE-1.05V PR242 *4.7_6 Rds*OCP=RILIM*20uA PQ74 AO4710 + PC206 *680p/50V_6 PR119 *SHORT_6 36,40,42,45,46 PR235 *SHORT_6 PR241 2.2/F_6 PR234 1M_6 D PR120 10/F_6 D PC190 10u/10V_8 PC195 *1000p/50V_6 PC193 1u/50V_6 PC204 560u/2.5V_6X5.7 B R1 PR237 4.02K/F_6 1.05V_FB B PC201 *33p/50V_6 VOUT=(1+R1/R2)*0.75 R2 PR238 10K/F_6 PR239 *SHORT_6 TON=3.85p*RTON*Vout/(Vin-0.5) Frequency=Vout/(Vin*TON) A TON=3.85p*1M*1/(Vin-0.5) Frequency=1/(0.0036767)=272K AO4710 Rdson=11.7~14.2mOhm L(ripple current) =(19-1.05)*1.05/(1u*272k*19) ~3.646A A Quanta Computer Inc 14.2m*10=RILIM*20uA RILIM=7.1K - 7.15K PROJECT : ZR7 Size Rev 3B VCCP 1.05V(UP6111A) Date: Document Number Monday, February 22, 2010 Sheet 41 of 49 [PWM] PC49 10u/10V_8 PR50 PC48 *SHORT_6 1u/50V_6 +0.75V_DDR_VTT VIN 8207_DH PC51 10u/10V_8 2.25A PC50 10u/10V_8 D 8207_LX D 8207_DL VTTSNS GND 19 LL DRVL 21 22 20 DRVH +1.5V_SRC PGND 18 CS_GND 17 CS 16 V5IN 15 +5V_S5 100K/F_6 PC131 *680p/50V_6 PC53 1u/6.3V_4 PC152 560u/2.5V_6x5.7 PC151 560u/2.5V_6x5.7 +3VPCU C PC147 10u/10V_8 change to 560u/2.5V_6x5.7 HWPG_1.5V 36 S5_1.8V PR69 *0/F_6 + PQ14 AOL1718 PC56 1u/6.3V_4 NC S5 PR73 PR74 620K/F_4 S3_1.8V + PR160 *4.7_6 PQ56 AOL1718 +1.5V_SUS PGOOD 14 13 12 FOR DDR III S3 COMP PR53 5.1/F_6 V5FILT VTTREF 11 10 +5V_S5 NC PC57 0.033u/50V_6 VDDQSET 0.75A VDDQSNS +SMDDR_VREF C PR51 5.6K/F_6 MODE +1.5V_SUS RT8207A PU4 OCP 22A 18A PC129 10u/25V_1206 PL9 0.56uH VTTGND PC130 PC47 2200p/50V_6 10u/25V_1206 PQ55 AOL1448 VBST 23 VLDOIN VTT GND 24 25 PR75 PR80 VIN PR76 *SHORT_6 0/F_6 *0/F_6 (For RT8207A SUSON 400KHZ ) 36 MAINON 36,40,41,45,46 PWRGD_1.5VCPU 35 +5V_S5 Add it for S3 leakage circuit 7/23 modify PR68 *SHORT_6 PR72 10K/F_4 Vout = (PR150/PR149) X 0.75 + 0.75 AO1718 Rdson=3.8~4.3mOhm L(ripple current) =(9-1.5)*1.5/(0.56u*400k*9) ~5.58A Vtrip= (22-2.79)(*4.3mohm/2)=0.0413V RILIM=Vtrip/10uA~4.13K B PR79 10K/F_4 PC62 *0.033u/50V_6 +1.5V_SUS B PC64 *33p/50V_6 MAIND 35,38,46 MAIND S3 S5 VTT REF S0 1 ON ON ON S3 OFF ON ON S4/S5 0 OFF OFF OFF PQ20 AO3404 +1.5VSUS +1.5V 2.03A A A Quanta Computer Inc PROJECT : ZR7 Size Document Number Date: Monday, February 22, 2010 Rev 3B DDR III 1.5V(TPS51116) Sheet 42 of 49 11/16 Change VGPU_CORE to two phase solution V2@ > Two Phase dGPU only EV@ > External VGA SKU +5V_S5 PR3001 V2@10_6 SW@ > iGPU & dGPU Switch MAX17007_VCC 11M@ > N11M-GE1 Setitng VIN VCC VDD 18 PC3001 V2@@1u/10V_6 SW@ > iGPU & dGPU Switch 16 GND BST1 15 MAX17007_BST1 A PR3005 V2@0_6 PR3004 17007_EN V2@100K_4 11 25 PR124 ES@0_4 DH1 MAX17007_DH1 14 MAX17007_LX1 17 MAX17007_DL1 PL3003 V2@1uH V2@0_4 MAX17007_VCC +VGPU_CORE 1/13 Add PR3032 MAX17007_VCC B PR3009 *V2@0_4 DL1 PR3007 *V2@2.2_6 PC3011 *V2@2200p/50V_4 PC3013 V2@0.22U/25V_6 SKIP CSH1 CSL1 PR3032 V2@0_4 PQ3002 V2@AOL1718 PC3009 V2@0.1u/50V_6 PC3010 V2@330u/2V_7343 PR3011 V2@10K_6_NTC PC3012 *V2@1000p/50V_4 PR3010 V2@3.01K/F_4 B +VGPU_CORE PC3014 V2@1000p/50V_4 PGOOD1 TON1 PGOOD2 TON2 BST2 PR3014 V2@200K/F_4 PR3015 V2@200K/F_4 PR3016 V2@0_6 21 MAX17007_BST2 VIN + PC3030 *V2@330u/2V_7343 PQ3003 V2@AOL1448 PC3020 V2@0.22u/25V_6 REF DH2 23 MAX17007_DH2 LX2 22 MAX17007_LX2 DL2 19 MAX17007_DL2 PC3016 V2@2200p/50V_4 PU3001 V2@MAX17007AGTI+ C PGND REFIN1 PC3023 V2@330u/2V_7343 C PR3022 V2@10K_6_NTC PC3025 *V2@1000p/50V_4 PR3021 V2@3.01K/F_4 MAX17007_CSH2 26 27 PR3023 V2@36.5K/F_4 PR3024 V2@10_6 PC3027 V2@1000p/50V_4 PR3025 11M@100K_4 VID1 VID2 MAX17007_VCC AGND AGND AGND AGND 28 VIN_SRC +VGPU_CORE 29 33 32 30 31 AGND FB2 PC3028 V2@0.01u/16V_4 PC3022 V2@0.1u/50V_6 20 PQ3005 V2@DMN601K-7 reserved on 11/19 DCR=3m PR3019 V2@1.5K/F_4 PR3020 V2@196K/F_4 CSH2 CSL2 PC3019 V2@10u/25V_1206 V2@AOL1718 PC3026 V2@0.22u/25V_6 + PC3015 V2@330u/2V_7343 + PQ3004 PC3024 *V2@2200p/50V_4 PC3018 V2@10u/25V_1206 PR3017 *V2@2.2_6 PR3018 V2@34K/F_4 MAX17007_REFIN1 PC3017 V2@0.1u/50V_6 PL3002 V2@1uH PC3021 V2@2200p/50V_4 VIN MAX17007_REF 24 12 PR3008 V2@1.5K/F_4 MAX17007_CSH1 10 V2@100K_4 45,47 VGA_PG PR3028 V2@1M_6 PR3026 V2@82.5K/F_4 PR3029 V2@22_8 GPU_VID1 GPU_VID2 0 +VGPU_CORE 1.035V 0.95V 0.85V 1 0.8V N11E/N11P 3 + PR3012 V2@10_6 PR3013 11M@ > N11M-GE1 Setitng ripple current~=3.2A > current limit=60mV(Vcc) & Rdcr_eq=2.69mohm >OCP=(60mV/2.69m+3.2A/2)*2=48A DCR=3m +VGPU_CORE ILIM2 +3V 19,47 GPU_VID1 PC3006 V2@10u/25V_1206 TDC 36A/OCP 48A ILIM1 PC3008 V2@120p/50V_4 MAX17007_REF PC3005 V2@10u/25V_1206 PR3003 13 EN2 LX1 +3V_GFX EV@ > dGPU only EN1 PC3003 V2@2200p/50V_4 PC3004 V2@0.1u/50V_6 V2@0_6 PR3002 PQ3001 V2@AOL1448 PC3007 V2@0.22u/25V_6 PR3006 *SW@0_4 11,47 dGPU_VRON VIN PC3002 V2@2.2u/6.3V_6 A D PQ3006 V2@DMN601K-7 17007_EN 2 PR3027 V2@100K_4 PR3030 V2@1M_6 PQ7020 V2@DTC144EU PQ7019 V2@DMN601K-7 Quanta Computer Inc 19,47 GPU_VID2 D PC3029 V2@0.01u/16V_4 PROJECT : ZR7 Size Document Number Rev 3B GPU CORE(MAX17007) Date: Monday, February 22, 2010 Sheet 43 of 49 A Int_VGA B C D E F G H [PWM] AR@ > ARD CPU GFX_VID0 GFX_VID1 +1.1V_VTT +1.1V_VTT GFX_VID2 GFX_VID3 PR102 *AR@0_6 GFX_VID4 PR101 *AR@0_6 PR192 *AR@0_6 PR100 *AR@0_6 PR97 *AR@0_6 PR92 *AR@0_6 PR91 *AR@0_6 GFX_VID5 GFX_VID6 GFX_VID6 62881_GND GFX_ON GFX_DPRSLPVR AR@0_4 PR200 AR@0_4 GFX_VID2 GFX_VID1 GFX_VID0 GFX_VID6 GFX_VID5 GFX_VID4 GFX_VID3 GFX_VID2 26 25 24 23 22 62881VR_ON 27 PC76 62881_GND PC77 PC157 AR@10u/25V_1206AR@10u/25V_1206 PC158 AR@2200p/50V_4 VID2 VID3 VID4 VID5 VID1 21 +5V_S5 2 PGOOD GFX_VID0 CLK_EN# VID6 VR_ON GND AR@.1u/50V_6 GFX_VID1 DPRSLPVR 62881PGOOD AR@0_4 GND PR103 GND PR207 AR@1.91K/F_4 HWPG_AXF 29 30 11/16 Change PU6 footprint by SMT 31 +3V 36 GFX_VID3 VIN 62881_GND GFX_VID4 *AR@SHORT 62881DPRSLPVR PR193 PR195 28 GFX_VID5 PC168 *AR@.01u/25V_4 PR198 AR@47K/F_4 PR208 AR@8.06K/F_4 62881RBIAS RBIAS VID0 20 PC78 62881VW VW VCCP PU6 19 PC86 LGATE FB PHASE UGATE 17 16 62881PHASE 15 62881UGATE BOOT IMON PC85 13 12 14 PC79 PR99 AR@2.61K/F_4 PQ21 AR@AOL1718 AR@.22u/25V_6 GFX_IMON 62881_GND PR93 *AR@19.1K/F_4 PC162 AR@0.15u/10V_4 62881_GND AR@0_4 PR189 PC165 AR@47n/10V_4 +5V_S5 PC83 AR@.1u/10V_4 62881_GND 0616 change to 2.49k PR191 PC163 *AR@180p/50V_4 PR197 AR@2.49K/F_4 AR@10_6 PC164 PC80 AR@10u/6.3V_8 VIN PC161 AR@.22u/25V_6 62881_GND PC159 AR@560u/2.5V_6X5.7 AR@11K/F_4 PC81 *AR@0.022u/25V_4 VSS_AXG_SENSE PC167 AR@560u/2.5V_6X5.7 PR96 GFX_IMON AR@1000p/50V_4 DCR=1.6~1.8mOhm Load Line=7mV/A 1.6m*0.6168=0.986m 0.986m/.49K=396p 392p*2*8.87K=7.03m OCP 20u/2*2.49K=24.9m 24.9m/0.6168=40.3m 40.3m/1.6m=25.2A + PR187 AR@10K_6_NTC PC156 *AR@680p/50V_6 AR@1_6 62881RTN PR94 62881BOOT 62881VIN PC84 AR@330p/50V_4 62881VDD 11 PC88 AR@330p/50V_4 62881ISUM+ 10 AR@150p/25V_4 0616 change to 150pF 62881ISUM- AR@17.8K/F_4 PQ63 AR@AOL1718 + PR95 AR@3.65K/F_4 PR186 *AR@4.7_6 VIN VDD PC87 ISUM+ VSEN RTN PL12 AR@0.56uH VSSP 0616 change to 8.87k PR104 AR@8.87K/F_4 62881VSEN PC171 AR@100p/50V_4 22A +VGFX_AXG 18 62881LGATE COMP 0616 change to 22pF 62881FB PR209 AR@ISL62881HRZ-T ISUM- PC170 AR@22p/50V_4 62881COMP 5 AR@1000p/50V_4 PR210 AR@820K/F_4 0616 change to 0.56uH AR@4.7u/6.3V_6 62881_GND PR199 *AR@150K/F_4 62881_GND PQ64 AR@AOL1448 AR@1u/6.3V_4 PR194 *AR@100/F_4 62881_GND PR98 AR@82.5/F_4 Parallel PR201 PR202 PC82 0616 un-mount AR@.01u/25V_4 AR@10/F_4 AR@0_4 VSS_AXG_SENSE 4 PR204 PR203 AR@10/F_4 AR@0_4 VCC_AXG_SENSE Quanta Computer Inc PROJECT : ZR7 Size 1.Level Environment-related Substances Should NEVER be Used 2.Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners Date: A B C D E F G Document Number Rev 3B +VGFX_AXG (ISL62881) Monday, February 22, 2010 44 Sheet H of 49 ES@ > External VGA SKU SW@ > iGPU & GPU Switch 1A +3VPCU +1.8V PC96 0.1u/25V_4 11/16 Change PL15 footprint 16 PR117 *SHORT_4 D MAINON 15 54418-1.8_VFB PC176 1000p/50V_4 PH VIN PH VIN PH EN BOOT VSNS 10 DCR(max)=10mohm 11 PL15 1uH_7X7X3 12 D PR223 13 *SHORT_6 PC179 1u/50V_6 14 PWRGD PR232 51.1/F_4 COMP GND RT/CLK GND SS AGND PR230 182K/F_4 PC189 *100P/50V_4 MAINON HPA00835RTER VIN HWPG_1.8V 36 PR231 100K/F_4 +3V PC186 01u/25V_4 MAINON 36,40,41,42,46 R1 PR222 100K/F_4 22 21 20 19 18 17 PR228 15K/F_4 PU10 PAD PAD PAD PAD PAD PAD PC185 10u/10V_8 PC181 0.1u/25V_4 PC95 10u/10V_8 PC184 10u/10V_8 54418-1.8_VFB PC191 1200p/50V_4 PR229 78.7K/F_4 R2 V0=0.8*(R1+R2)/R2 +5V 5V_LCD 2A PC3111 V2@0.1u/25V_4 PC3110 V2@10u/10V_8 PU3002 16 PR3033 V2@0_4 HWPG_VTT 15 54418-1.8_VFB_1 PR3036 V2@30.1K/F_4 PR3037 V2@182K/F_4 PC3117 *V2@100P/50V_4 HWPG_VTT V2@HPA00835RTER 10 PH VIN VIN PH EN BOOT VSNS COMP RT/CLK SS DCR(max)=10mohm C PL3005 V2@1uH_4X4X2 11 PH 12 PWRGD 13 PR3034 14 HWPG_5V_LCD V2@0_6 PC3112V2@.1u/50V_6 PR3035 V2@51.1/F_4 GND GND AGND R1 PR3038 PR3039 *V2@100K/F_4 PC3114 V2@100K/F_4 +3V 22 21 20 19 18 17 PC3113 V2@1000p/50V_4 VIN PAD PAD PAD PAD PAD PAD C V2@0.1u/25V_4 PC3118 V2@.01u/25V_4 PC3115 PC3116 V2@10u/10V_8 V2@10u/10V_8 54418-1.8_VFB_1 5V_LCD HWPG_VTT 36,40 PC3119 V2@1000p/50V_4 VIN_SRC 11/19 Del 3G power circuit +1.5V_GFX +1.8V_GFX +1.8V +15V 23 PR3040 V2@26.7K/F_4 R2 1/13 Add 3D LCD power circuit 5V_LCD V0=0.8*(R1+R2)/R2 +1.5V_SUS B PR46 ES@22_8 PR36 ES@22_8 PR49 ES@1M/F_6 PQ8 ES@DMN601K-7 PQ13 ES@DMN601K-7 +1.05V_GFX PR48 ES@22_8 +1.05V PR43 ES@1M/F_6 1 A PQ6 ES@DMN601K-7 PQ10 ES@DMN601K-7 PC39 *ES@2200p/50V_4 +1.05V_GFX PQ9 ES@DMN601K-7 PQ7 ES@DTC144EU dGPU_D PR39 ES@1M/F_62 PR35 SW@100K_4 PQ54 ES@AO4468 PQ51 ES@AO3404 +3V_GFX SW@0_4 +3VPCU 3 3 dGPU_D EV@0_4 2.87A(Max 3.83A) 10/19 0.23A(Max0.3A) +15V PR37 ES@22_8 PR244 +1.5V_GFX PR38 ES@1M/F_6 11 dGPU_PWR_EN +1.8V_GFX +3V_GFX 11/12 PR243 PC46 *ES@2200p/50V_4 4.28A(Max5.72A) VIN_SRC MAINON PQ50 ES@AO4468 1 PQ11 ES@DTC144EU PC38 ES@1u/10V_4 PQ53 ES@AO3404 PQ12 ES@DMN601K-7 PR40 ES@1M/F_6 ES@0_4 VGA_PG A dGPU_D1 PR44 43,47 3 dGPU_D1 10/19 PR47 ES@1M/F_6 B Quanta Computer Inc 1.04A(Max1.38A) PROJECT : ZR7 SW@ > iGPU & GPU Switch Size Document Number Date: Monday, February 22, 2010 Rev 3B Discharge/1.8V) Sheet 45 of 49 VIN_SRC PU5B PD2 SW1010CPT A + - A LM393 For EC control thermal protection (output 3.3V) PR87 1M_6 PQ17 AO3409 36,38 3 S5_ON S5_ON Thermal protection VL PQ18 DTC144EU PR85 *SHORT_6 VL B B SYS_SHDN# PR83 1.2K/F_4 PR84 200K/F_4 4,38 PR81 200K_6 PC69 1u/50V_6 + 2.469V PQ15 DMN601K-7 PU5A LM393 PC67 1u/50V_6 PR41 10K_6_NTC PR86 200K/F_4 C C S5_ON PQ19 DMN601K-7 +3V VIN_SRC Add it for S3 leakage circuit PR143 22_8 PR146 1M/F_6 35 MAINON_DIS_G +5V +1.1V_VTT PR137 22_8 +1.5V PR140 22_8 +1.05V PR150 22_8 +15V PR149 22_8 PR145 1M/F_6 7/23 modify MAIND MAIND 35,38,42 3 2 PQ40 DMN601K-7 DMN601K-7 Quanta Computer Inc PQ45 DMN601K-7 PQ46 DMN601K-7 PC118 *2200p/50V_4 PROJECT : ZR7 DMN601K-7 PQ42 PQ39 1 PQ41 DMN601K-7 1 PQ47 DTC144EU D 2 PR148 *100K_4 PR142 1M/F_6 36,40,41,42,45 MAINON D 3 MAINON_DIS_G Size Document Number Rev 3B Thermal Protection Date: Monday, February 22, 2010 Sheet 46 of 49 V1@ > One Phase dGPU only +5V_S5 EV@ > External VGA SKU VIN VIN SW@ > iGPU & dGPU Switch PQ37 V1@AOL1448 PC2 V1@1u/10V_6 8792VCC 13 VDD 8792TON DH 8792DH BST 8792BST TON 14 VGA_PG 8792EN 11,43 dGPU_VRON V1@MAX8792ETD+TLX PC1 8792SKIP# 12 PR8 PR3031 ES@0_4 SKIP# DL *V1@0_4 8792REFIN 10 REFIN PR122 8792LX 8792DL FB ILIM PL3004 11M@0.36uH PR21 V1@1_8 10/19 8792REF 11 REF 8792_GND PR130 V1@34K/F_4 + + PC25 V1@330u/2V PC15 V1@1000p/50V_4 15 8792_GND B 8792ILIM + 11M@ N11M-GE1 Setitng REF-2V V1@100K_4 A +VGPU_CORE PC17 PC113 V1@2200p/50V_4 V1@10u/25V/X6S_1206 11P@ PL6 N11P-GE1 11P@0.68uH Setitng +VGPU_CORE EV@ > GPU only PU1 EN change net name V1@.1u/10V_4 +3V_GFX PGOOD PC10 V1@0.22u/X5R_6 SW@ > iGPU & GPU Switch PR123 *SW@0_4 PR15 V1@1_6 29A OCP=35A PC18 V1@10u/25V/X6S_1206 EP 43,45 VCC 8792_GND V1@1u/10V_6 PR4 V1@100K_4 PC4 PC16 V1@.1u/50V_6 11P@ > N11P-GE1 Setitng PQ7021 11P@AOL1448 PR16 V1@200K/F_4 PR128 *V1@0_4 +3V A 11M@ > N11M-GE1 Setitng PC3031 V1@10u/25V/X6S_1206 B PR131 V1@62K/F_4 PR1 V1@ES0_6 PC14 *V1@4700P/25V_4 8792_GND PQ35 V1@AOL1718 PQ34 V1@AOL1718 PC27 V1@.1u/50V_6 PC21 V1@330u/2V PC22 V1@330u/2V Place near GND pin15 PR127 V1@196K/F_4 PC9 V1@1000P/50V_4 PR14 V1@100K_4 VID1 PQ28 V1@2N7002D PC103 V1@.01u/16V_4 C 8792_GND 8792_GND changed to GND_VGA8792 PR5 V1@82.5K/F_4 VID2 GPU_VID1 GPU_VID2 0 +VGPU_CORE 1.035V 0.95V 0.85V 1 0.8V N11M N11E/N11P C VIN_SRC +VGPU_CORE PR7 V1@1M_6 10/20 Modify Power table 10/22 Power CKT updated PR3 V1@100K_4 Changed VID table VID2 PQ1 V1@2N7002D 19,43 GPU_VID2 VID1 300K PR2 V1@22_8 11M@ > N11M-GE1 Setitng Frequency(PR220=200K) 8792_GND 8792_GND PR132 V1@36.5K/F_4 changed value on 09/17 PR126 11M@100K_4 change net name 19,43 GPU_VID1 2 PQ29 V1@DTC144EU 8792_GND PR6 V1@1M_6 8792EN PC3 V1@.01u/16V_4 PQ2 V1@2N7002D D D Quanta Computer Inc PROJECT : ZR7 Size Document Number Date: Monday, February 22, 2010 Rev 3B GPU CORE(MAX8792) Sheet 47 of 49 300 mil ISL62882 1800 mil 1800 mil U3031 200 mil 200 mil D 520 mil AO6402A +5V PQ35 +5VPCU AO4496 +5V_TMA AO6402A U50 CN27 U6 U22 U33 CN1 CN2 CN34 CN36 CN30 CN15 20 mil 40 mil 40 mil 20 mil 20 mil 20 mil 30 mil 20 mil 80 mil 80 mil 80 mil 20 mil CN19 CN20 CN10 CN43 CN12 CN16 CN41 U2 20 mil 20 mil 20 mil 20 mil 20 mil 20 mil 20 mil 20 mil 280 mil 40 mil +5V_S5 PQ38 200 mil System Charger ISL6251A U3035 40 mil CN9 280 mil PQ82 ISL6237 PU4 40 mil AC U38 D 280 mil 400 mil CPU VCC_CORE PU7 +5VPCU U3035 PU7 PU8 PU9 PU10 PU6 PU11 20 mil 20 mil 20 mil 20 mil 20 mil 20 mil 20 mil R330 R3691 U45 ESD1 U23 CN15 CN14 20 mil 10 mil 20 mil 30 mil 20 mil 20 mil 20 mil CN39 CN6 U4 U19 U14 CN5 R428 20 mil 10 mil 70 mil 10 mil 70 mil 130 mil 20 mil VIN DC PU2 40 mil +3VPCU D30 MR1 CN14 U16 U8 R429 PU12 20 mil 15 mil 20 mil 30 mil 20 mil 20 mil 20 mil R164 15 mil R586 R437 L22 U9 PU2 20 mil 10 mil 10 mil 20 mil 10 mil C C +3VPCU 250 mil AO4496 250 mil +3V PQ25 150 mil AO6402A 150 mil 30 mil U15 R3343 R649 R462 L3035 R184 20 mil 10 mil 20 mil 20 mil 30 mil 15 mil 30 mil U5 Q6 U33 U27 U18 U44 R655 20 mil 65 mil 15 mil 20 mil 20 mil 20 mil 20 mil R327 CN12 CN18 U29 U13 CN5 R158 30 mil 20 mil 20 mil 100 mil 20 mil 20 mil 20 mil G973 +3V_S5 PQ7 L26 40 mil 120 mil U3031 R3301 R3268 30 mil 15 mil 15 mil R198 U21 U3017 U29 20 mil 15 mil 20 mil 30 mil +1.8V PU11 R654 Q22 20 mil 120 mil 30 mil CN17 R3587 15 mil R619 20 mil R36 20 mil L25 15 mil R17 20 mil R167 R192 R195 U3010 CN27 10 mil 30 mil 30 mil 10 mil 80 mil R710 L57 CN11 R496 R499 20 mil 20 mil 40 mil 120 mil 30 mil R11 R29 CN3 R3289 R3292 20 mil 20 mil 20 mil 40 mil 20 mil R711 L28 R3291 40 mil 25 mil 20 mil U3044 U11 R151 20 mil 15 mil 30 mil B B 20 mil G909 20 mil +1.5V_S5 PU12 200 mil UP6111A 400 mil UP6111A R448 R165 L3055 R3570 20 mil 80 mil 20 mil 15 mil 150 mil 15 mil L3047 R185 R3644 L3058 R195 15 mil 30 mil 60 mil 15 mil 30 mil +SMDDR_VTERM JDIM3001 JDIM3002 40 mil 40 mil 20 mil 600 mil A AO4496 L3046 L3048 R186 R454 R455 15 mil 15 mil 40 mil 50 mil 50 mil Q39 U3031 10 mil 600 mil 15 mil R3243 R195 15 mil 300 mil 400 mil +VAXG R3302 CN17 CN9 15 mil 30 mil 180 mil 20 mil U18 R676 R69 R668 U29 30 mil 30 mil 60 mil A +1.5V PQ23 400 mil PU8 R3304 15 mil 20 mil 300 mil +1.5VSUS ISL62881 15 mil R3326 +SMDDR_VREF PU6 200 mil R180 +VTT 80 mil TPS51116 15 mil 600 mil PU9 200 mil R3056 R34 15 mil +1.05V PU10 250 mil R3340 R3234 JDIM3001 JDIM3002 U3031 100 mil 100 mil 350 mil 30 mil U3031 Quanta Computer Inc 350 mil PROJECT : ZR7 Size Document Number Rev 3B POWER MANAGEMENT Date: Monday, February 22, 2010 Sheet 48 of 49 MODEL Model CHANGE LIST REV ZR7 FROM 11/2 Page33 Change CN10 P/N by PDC 11/5 Page9 change R338 and R594 to 10K ohm by checklist ZR7 MB 11/5 Page10 Add R699 connect XTAL25_IN to Gnd on EV sku and stuff Xtal components by checklist 11/5 Page12 un-stuff R318 and del C499 and add R698 contact VCCLAN to GND by checklist 11/9 Page32 change W/L LED signal to control by EC 11/9 Page36 Add EC pin82/112 for W/L LED control by EC 11/12 Page35 PR90,PQ22 no stuff 11/12 Page45 Add PR243,PR244 for option 11/16 Page23 CN5 Add LVDS signal to two channel and change CN3 to 8pin conn 11/16 Page44 Change PU6 footprint by SMT 11/16 Page45 Change PL15 footprint to CHOKE-PCMC063T-3R3MN-NB4 by SMT 11/16 Page39 Change PU8 footprint to qfn40-5x5-4-41p-0_75h-smt by SMT 11/16 Page37 Change PU3 footprint to QFN28-5X5-5-33P-SMT by SMT 11/18 Page10 Delete R597, C444,C445 for cancel 3G function 11/18 Page10 Change BOARD_ID0~2 to BOARD_ID1~3 11/18 Page11 Change GPIO7 to BOARD_ID0 and reserve R439 PD 11/18 Page36 Add D23 to connect to dGPU_PWROK on EV sku 11/18 Page9 Change P/N follow ZR7B that use right angle connector 11/18 Page27 Reserve C919, CN22 for NV IR signals on B-test 11/19 Page3 Change U39 PN to AL003197002 by vendor 11/19 Page31 Change CN9 footprint & P/N follow ZR7B 11/19 Page27 Add R697 for WI-FI 11/19 Page11 Add R442, R440 to dGPU_PWROK_R and stuff R321 on EV sku 11/19 Page23 Modify CN5 pin define 11/20 Page43 Add PR124 on EV sku 11/20 Page12~14 Change core logic cap 1uF CH41003ZB35 to CH4102K1B03 by SMT 11/20 Page45 del 3G power circuit 11/20 Page34 del HOLE10,Add HOLE5,HOLE6,HOLE7,HOLE8,HOLE11,HOLE12,HOLE14,HOLE15,HOLE17,HOLE18,HOLE20,HOLE24,HOLE25,HOLE26,HOLE30 P/N 11/25 Page10 Q26,Q29 change to unstuff , Add R700,R701 ohm for S3 leakage 11/25 Page34 Change HOLE8,HOLE12 footprint to H-C236D142P2 , Change HOLE5,HOLE7,HOLE11 footprint to H-TC197D122PT , Change HOLE14,HOLE15,HOLE17,HOLE18 footprint to H-TC236D142PT , Change HOLE20,HOLE24,HOLE26 footprint to H-TC236D162PT , Change HOLE9 footprint to O-ZR7-1-B 11/25 Page36 R425 change to DGPU_IDLE# signal and value to SW SKU , R428 change value to SW SKU , R249,R250 change to unstuff 11/25 Page28 Add C920,C921,C923,C924 0.1uF for EMI 11/25 Page33 L31 SWAP for Layout House 11/25 Page27 Modify LTRST#_7726 net name to PLTRST# 11/26 Page33 Change L19/L25 footprint , Stuff L25 common choke & unstuff R301,R302 by EMI 11/26 Page23 Change L2 footprint 11/26 Page23 Change R589,R590 to FLITER for EMI 11/26 Page28 Add C925,C926,C927 for EMI 11/26 Page11 Modify R422 Value to IV@ SKU 2A 2A 2A 1A 2A 1A 2A 1A 2A 1A 2A 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 2A 2A 1A 11/27 Page23 Add CN5 pin45 to GND 1A 2A 11/27 Page27 Add L46,L47,R702,R703,R704,R705 by EMI 1A 2A 11/27 Page10 Modify C699,C703 to 27pF 1A 2A 11/27 Page18 Modify C601,C600 to 27pF 1A 2A 12/1 Page27 Modify CN12 to pin connector 1A 2A 12/1 Page32 Modify LED3 & Add R706,R707 PD by EC ODD_EJ & POWER_SAVE 1A 2A 12/1 Page9 Add R708,R709 by SPI ROM 1A 2A 2A 3A 2A 3A 12/29 Page24 Change Q16, Q45 P/N & add F2 by HMDI submit and safety; del U15, U16, U18 12/29 Page30 Change CN19 color to black P/N: DFTJ08FR130 by ACER 1/5 Page33 Change CN17 footprint to USB-UB111GC-RABED-7F-4P-R-V-SMT by PDC 1/7 Page23 Change Q12 of dGPU_select# signal design by leakage issue 1/7 Page9 Change BT1 P/N to DFHD02MS784 by ME issue 1/8 Page27 Change CN12,CN22 6pin conn footprint for Touch Screen and IR 1/11 Page23 Add L48 & stuff L2 and un-stuff R28 and R29 by EMI 1/11 Page24 Add C928 by EMI 1/13 Page12,36 Change C711,C382 to 10U 6.3V 1/14 Page23 Change LVDS connector Pin4 define from NC to LCDVCC & add J3 by 3D PWR 2A 3A 2A 3A 2A 3A 2A 3A 2A 3A 2A 3A 3A 2A 3A 2A 3A 2A 3A 2A 3A 2A 3A 2A 3A 2A 1/14 Page28 Change C218,C678 to 10U/10V_8 and footprint 0805 3A 3A 3B 2/3 Page 30 Change R368,R393 to 75ohm 3A 3B Power modify: 1A 2A 11/19 Take out JP12, JP9, JP5, JP6, JP7, JP19, JP20, JP8, JP10, JP11,JP13, JP15, JP16, JP1, JP17, JP14, JP18 1A 2A 11/19 Page38 Change PC198 value; change PR114 from 191K to 182K, PR115 from 220K to 200K,PR106 from 100K to 1K,PR105 from 200K to 150K 11/19 Page40 Change PL7,PL8 from 1.0uH to 2.2uH 1A 2A 11/19 Page43 Reserve PC3030 11/23 Page37 PR19 change to 150K , PR20 change to 39K , PC112 change to 1U 25V 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 12/29 Page47 Change PL7,PL8,PL15,PL16 footprint to CHOKE-PCMC063T-3R3MN-SMT by SMT 2A 3A 12/29 Page37 Change PR136 footprint to RC3720-SMT by SMT 2A 3A 1/5 Page37~48 Change footprint from CHOKE-ETQP4LR36WFC to CHOKE-ETQP4LR36WFC-SMT by PDC 2A 3A 1/11 Page37 Add PC3100~PC3109 by EMI 2A 3A 2A 3A 1/11 Page47 Change value of PQ7021,PL6,PL3004 by BOM 1/13 Page43 Reserve PR3032 by PWR 2A 1/13 Page45 Reserve circuit of LCDVCC by PWR 2A 3A 2/10 Page37 Reserve EC1~EC5 by EMI 3A 3B 2/11 Page38 Del PD3 by power 3A 3B 2/11 Page40 Add C930~C934 by monitor test 3A 3B 3A 3B 3A Quanta Computer Inc PROJECT : ZR7 Size Rev 3B Change list2 Date: Monday, February 22, 2010 Sheet PROJECT MODEL : DOC NO Document Number 49 of ZR7 PART NUMBER: APPROVED BY: DATE: DRAWING BY: REVISON: 2009/11/06 1A 49 B 3A 2A 2/3 Page 16~22 Change U33 footprint to fcbga973-nvidia-n11p-es-a1 by NV 11/19 Page39 Change PL10,PL11 from DC+36T0M000 to CV+18V0MZ04 C 2A 2A B D 2A 1A 1A 12/29 Page23 Add F1 by safety 3B 2A 1A 11/27 Page16 C84,C109 change CC0603 package 12/29 Page27 Change CN21 footprint to MIPCI-800055FB052GX00pl-52P-smt by SMT A 2A 1A 11/27 Page20 C81,C105 change CC0603 package 12/18 Page47 Change PL6 footprint to choke-mpl136-2r2-smt by SMT 3A 2A 1A 1A 12/18 Page23 Add R712,R713 by 3D feature 2A 2A 1A 11/27 Page11 Del R440 12/18 Page32 Add R710,R711,Q57 by EC 3B 2A 1A 1A 11/25 Page20 C151 change to CC7343 package 3A 2A 1A 1A 11/18 Page30 R368,R393 modify from 47ohm to 56ohm by Realtek C 2A 1A 1A 11/16 Page27 Add CN12 8pin conn for Touch Screen by ME 2A 2A 1A 1A 11/16 Page43 GPU VCORE power change to two phase solution D To 1A A ... Reserve EC1~EC5 by EMI 3A 3B 2/11 Page38 Del PD3 by power 3A 3B 2/11 Page40 Add C930~C934 by monitor test 3A 3B 3A 3B 3A Quanta Computer Inc PROJECT : ZR7 Size Rev 3B Change list2 Date: Monday,... mil 30 mil U3031 Quanta Computer Inc 350 mil PROJECT : ZR7 Size Document Number Rev 3B POWER MANAGEMENT Date: Monday, February 22, 2010 Sheet 48 of 49 MODEL Model CHANGE LIST REV ZR7 FROM 11/2 Page33... +0.75V_DDR_VTT 205 206 4D@DDR3-DIMM1_H=8.0_Reverse A Quanta Computer Inc PROJECT : ZR7 4D@DDR3-DIMM1_H=8.0_Reverse Size Document Number Date: Monday, February 22, 2010 Rev 3B DDRIII SO-DIMM-B0/B1 Sheet 15