5 ZU1 SYSTEM BLOCK DIAGRAM DVI / 7307 Chrontel CLOCK GENERATOR CK505 (only for ezDock) D Merom 479 uFCPGA Page 21 Page CPU Thermal Sensor Page Page 3,4 PCI DEVICE IDSEL# REQ# / GNT# Interrupts CLOCK CB1410 AD17 REQ0# / GNT0# INTA# CK505/PCI1 MR510 AD18 REQ1# / GNT1# INTB# CK505/PCI0 TIAB23 AD25 REQ2# / GNT2# INTE# CK505/PCI2 D FSB 667/800 Mhz S-VIDEO CONN Page 20 SDVO TV LVDS VGA LCD CONN (12.1"WXGA) Page 20 Dual Channel DDR2 533/667 MHz NB Crestline (GM965) CRT Port DDRII SO-DIMM SO-DIMM RJ45 Page 18 Page 12,13 Transformer Page 5~11 Page 18 Page 19 X4 DMI interface C Page 26 SB PCI-Express ICH8M USB 2.0 Page 26 Azalia USB0~2 Page 18 PCIE-0 PCIE-1 PCI Bus Page 14~17 USB Port x C (BCM 5787) Page 27 PATA ODD (PATA) Giga Lan Mini Card / WLAN SATA HDD (SATA) Page 27 LPC Bluetooth USB4 Page 27 Finger Printer USB6 Super I/O NS PC87383 uR PC8763L Page 29 Page 28 B Page 30 PCMCIA Controller (CB 1410) Card Reader Controller (MR510) Page 22 1394 Controller (TI 43AB23) Page 23 Page 25 B CCD USB8 Page 20 SPI ROM Touch Pad Page 28 Page 29 K/B CONN Page 29 FIR Page 30 Card Reader PCMCIA Page 24 1394 CONN Page 24 Page 25 A1A (11/2):(1) Re-name HP HP AMP Page 32 Page 31 INT SPK SPK AMP Page 32 Audio Codec (ALC268) PCI-Express ezDockII/II+ Connector Page 32 PCIE , Lan ,1394 Line in & MIC Page 32 Page 31 USB Ser & Par Port 1394*2 PS2 , VGA, DVI TV out / CRT MediaBay Express Card Page 31 VCORE(ISL6262A) Page 38 C2A (12/28):Gerber out Discharge D3A (2/12):Gerber out Page 35 Page 38 VTT 1.05V (SC411) Charger (ISL6251) Page 36 Page 39 Audio Page 33 B1C (11/29):Gerber out E3A (4/2):Gerber out Switch Page 20 10/100/1G MDC 1.5 USB3 (2) Gerber out 1.25V 1.5V 2.5V Page 34 DVI SPDIF,SM BUS A PCIE-2 5V/3V (ISL6236) Switch Page 18 1.8V (TPS51116) A PROJECT : ZU1 Page 37 Size Quanta Computer Inc Document Number Date: Tuesday, April 10, 2007 Rev 3B Block Diagram Sheet 1 of 39 ClockL55 Generator +3V E3A:(3/16) Change C542 from 0805(CH6102K9A01) to 0603(CH6101M9905) base on ME request(HDD Mylar issue) Clock Gen I2C C288 1U_4 BKP1608HS181-T_6 C655 C542 C294 1U_4 0_6 C287 10U_8 C540 1U_4 U19 C292 1U_4 A1A:(9/28) Reverse RC0603 footprint for EMI C319 1U_4 0_6 R199 VDD_CK_VDD_PCI VDD_CK_VDD_48 VDD_CK_VDD_SRC VDD_CK_VDD_REF 16 61 VDD_CK_VDD_SRC VDD_CK_VDD_CPU 39 55 VDD_SRC VDD_CPU 12 20 26 45 36 49 VDD_96_IO VDD_PLL3_IO VDD_SRC_IO_1 VDD_SRC_IO_3 VDD_SRC_IO_2 VDD_CPU_IO +1.25V_VDD C318 1U_4 0_6 R444 VDD_PCI VDD_48 VDD_PLL3 VDD_REF 23 PCI_CLK_510 22 PCI_CLK_CB714 R429 +3V PCLK_1394 28 PCLK_591 +3V 27,30 PCI_CLK_SIO R188 22_4 PCI_CLK_510_R PCI0/CR#_A R434 33_4 PCI_CLK_CB714_R PCI1/CR#_B 10K_4 IO_VOUT SCLK SDA 64 63 SRC5/PCI_STOP# SRC5#/CPU_STOP# 38 37 CPU0 CPU0# 54 53 CLK_CPU_BCLK_R CLK_CPU_BCLK#_R RP36 0X2 CLK_CPU_BCLK CLK_CPU_BCLK# CPU1 CPU1# 51 50 CLK_MCH_BCLK_R CLK_MCH_BCLK#_R RP35 0X2 CLK_MCH_BCLK CLK_MCH_BCLK# SRC8/ITP SRC8#/ITP# 47 46 SRC10# SRC10 35 34 CLK_PCIE_3GPLL#_R CLK_PCIE_3GPLL_R RP34 0X2 CLK_PCIE_3GPLL# CLK_PCIE_3GPLL SRC11/CR#_H SRC11#/CR#_G 33 32 PCIE_CLK_RBS_R PCIE_CLK_RBS#_R SRC9 SRC9# 30 31 CLK_PCIE_EZ1_R CLK_PCIE_EZ1#_R RP29 0X2 SRC7/CR#_F SRC7#/CR#_E 44 43 SRC6 SRC6# 41 40 CLK_PCIE_ICH_R CLK_PCIE_ICH#_R RP37 0X2 CLK_PCIE_ICH 15 CLK_PCIE_ICH# 15 SRC4 SRC4# 27 28 CLK_PCIE_MINI1_R CLK_PCIE_MINI1#_R RP30 0X2 CLK_PCIE_MINI1 27 CLK_PCIE_MINI1# 27 SRC3/CR#_C SRC3#/CR#_D 24 25 CLK_PCIE_LAN_R CLK_PCIE_LAN#_R RP31 0X2 CLK_PCIE_LAN 18 CLK_PCIE_LAN# 18 SRC2/SATA SRC2#/SATA# 21 22 CLK_PCIE_SATA_R CLK_PCIE_SATA#_R RP32 0X2 CLK_PCIE_SATA 14 CLK_PCIE_SATA# 14 SRC1/SE1 SRC1#/SE2 17 18 DREFSSCLK_R DREFSSCLK#_R RP41 0X2 SRC0/DOT96 SRC0#/DOT96# 13 14 DREFCLK_R DREFCLK#_R RP33 0X2 CKPWRGD/PWRDWN# 56 CK505 R428 *10K_4 R427 10K_4 R433 33_4 PCLK_1394_R PCI2/TME R187 33_4 PCLK_591_R PCI3 R431 22_4 PCI_CLK_SIO_R PCI4/SRC5_EN R186 +3V 15 PCLK_ICH *10K_4 R182 10K_4 R430 16 CLKUSB_48 C 16 R181 CLK_BSEL0 CLK_BSEL1 R426 2.2K_4 CLK_BSEL2 R441 10K_4 R442 14M_ICH 22_4 PCLK_ICH_R CG_XIN 60 XTAL_IN CG_XOUT 59 XTAL_OUT 10 USB_48/FSA 57 FSB/TEST/MODE 62 REF0/FSC/TESTSEL 11 15 19 52 23 29 42 58 VSS_PCI VSS_48 VSS_IO VSS_PLL3 VSS_CPU VSS_SRC1 VSS_SRC2 VSS_SRC3 VSS_REF 33_4 FSA FSC 22_4 R443 22_4 30 SIO_14M A1A:(9/24) FAE : (14M_ICH and SIO_14M) signals trace should be equal length A1A:(9/24) ICS FAE suggest R change from 22 to 33 ohm A1A:(9/20) change R186 value from 33ohm to 22 ohm(Intel check list 1.301) A1A:(9/20) remove IO_VOUT 48 A1A:(9/20) remove SATACLKREQ function, change R188 value from 475ohm to 22 ohm 25 PCIF5/ITP_EN D +3V PM_STPPCI# 16 PM_STPCPU# 16 R194 R185 Q20 RHU002N06 CG_XIN 13,16,18,27,33 PCLK_SMB 475_4 475_4 Pin R195 Active 10K_4 CGCLK_SMB Control signal CLK_MCH_OE# PCIE_CLKREQ# 33 32 Low SRC9/9# PCIE_CLK1+ 33 PCIE_CLK1- 33 33 Low SRC10/10# A1A:(9/24) Base on above table, SWAP SRC3 and SRC9 +3V C R184 10K_4 PCIE_CLKREQ# A1A:(9/24) Add PCIE_CLKREQ# PU to +3V DREFSSCLK DREFSSCLK# DREFCLK DREFCLK# CK_PWRGD 16 (1)PCI2/TME: PU be used, the CK505 cannot over clock any of the clock for Trust Mode security purposes Y2 (2)PCI4/SRC5_EN: PU be used, the CK505 will be configured to use Pin37/38 to SRC5 clock If PD be detect at powe-on,the CK505 will setting Pin 37/38 to PCI_STOP/CUP_SOTP (Default is setting to PCI_STOP/CUP_SOTP) During initial power-up be used to sample FSB speed with FSA/B/C Clock Gen Differential IO power +1.25V_VDD CG_XOUT +1.25V L26 BKP1608HS181-T_6 (3)PCIF5/ITP_EN: PU be used, the CK505 will be configured to use Pin46/47 to CPU ITP clock If PD be detect at powe-on,the CK505 will setting Pin 46/47 to SRC8 (Default is setting to SRC8) XTAL length < 500mils B 10K_4 CGDAT_SMB C2A:(12/12)change from +1.05V to +1.25V Because VDD_IO will drop out when high loading 14.318MHZ C299 27P_4 CGCLK_SMB CGDAT_SMB C2A:(12/26) Base on vendor-FCE suggestion, change C310/C299 from CH03306JBD7 (33p) to CH02706JB06(27p) 27P_4 13,16,18,27,33 PDAT_SMB ICS9LPRS365AGLFT/ SLG8SP512T C310 R197 Q21 RHU002N06 ICS9LPRS365BGLFT SLG8SP512T: AL8SP512K05 A1A:(9/24) ICS FAE suggest to change C542,C287 from 4.7uF to 10uF 10U_6 D +3V R436 *4.7U_6 C320 C309 C300 C301 C316 C314 C317 C290 C315 C291 C293 *10U_8 *10U_8 *10U_8 10U_8 1U_4 1U_4 1U_4 1U_4 1U_4 1U_4 1U_4 B (4)SLG8SP512 Pin select Pin 17, 18 output is LCDCLK or 27 M, PD is LCDCLK, PU is 27 M , Pin 37, 38 will fixed be use CPU_Stop and PCI_Stop 0.1U close to each VDD_IO Power pin (5)SLG505YC64 CK505 Standar parts follow standar setting CPU Clock select CPU_BSEL0 +1.05V_CPU CPU_BSEL1 BSEL Frequency Select Table R180 0_4 R425 *56_4 R179 *1K_4 R440 0_4 R439 *0_4 R198 *1K_4 R448 0_4 R449 *0_4 A +1.05V_CPU CPU_BSEL2 R447 +1.05V_CPU CLK_BSEL0 CLK_BSEL1 MCH_BSEL0 MCH_BSEL1 A1A: (9/20) Remove 0ohm CLK_BSEL2 FSC FSB FSA Frequency 0 266Mhz 0 133Mhz 1 166Mhz 200Mhz 1 400Mhz 1 Reserved 1 100Mhz 0 333Mhz A MCH_BSEL2 PROJECT : ZU1 *1K_4 Date: Tuesday, April 10, 2007 Rev 3B CLK GEN./ CK505 C2A: (12/10) no stuff R179,R198,R447 for auto CPU frequence selection (follow ZD1,ZO1) Size Quanta Computer Inc Document Number Sheet of 39 H_A20M# H_FERR# H_IGNNE# A6 A5 C4 A20M# FERR# IGNNE# D5 C6 B4 A3 STPCLK# LINT0 LINT1 SMI# M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10] R173 0_4 T55 T50 T56 T53 T108 T48 T52 T5 T54 T49 TP_CPU_RSVD01 TP_CPU_RSVD02 TP_CPU_RSVD03 TP_CPU_RSVD04 TP_CPU_RSVD05 TP_CPU_RSVD06 TP_CPU_RSVD07 TP_CPU_RSVD08 TP_CPU_RSVD09 TP_CPU_RSVD10 H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[31:16] Layout note: Z=55 ohm H_GTLREF