1 ZE7 Block Diagram (Intel Cedar Trail-M Platform) HDMI CONN DC(3.5W) & DC(6.5W) (32nm) DDI1 1366x768 LVDS/eDP CONN P2 400 / 640MHz P17 A CLK Gen SLG8LV631V Cedarview-M DDI0 HDMI 1.3a 01 A DDR III,800/1066 MT/s Micro-FCBGA8 (22x22mm) Channel A UNBUFFERED DDRIII SODIMM RC-B/F CLK2/3, H=4 P4 LVDS 18bit,SC 1366x768 0ohm P18 DAC 1920x1200 VGA CONN P5~9 P18 x2 DMI Gen1 B RTL8105TA-VC-CG B PCIE Gen1 Tigerpoint (NM10) P22 1.5W Mini card2 vFBGA P25 (360 balls,17x17mm) P22 Mini card1 P25 RTS5209-GR CARDREADER MM-SIM CARD IN1 CARDREADER USB interface module SATA II I/F P19 Mobile 2.5" HDD SD3.0, MS, MS PRO, P26 xD, MMC C P24 USB PORT P21 Left P20 P25 P26 C MIC In Jack Analog MIC Speaker Header (2W) Audio CODEC Realtek 271X P20 HD AUDIO I/F RJ45 CONN USB 2.0 P10~15 USB PORT USB PORT Right Down Right Up P21 CCD P21 P18 EC Nuvoton NPCE791L P27 D BATTERY CHAGER P29 SYSTEM 5V/3V PCU CPU Core Gfx Core DDR 1.5VSUS P32 Discharge/+1.8V/ +3.3V_PRIME P34 Keyboard P19 Touch Pad SPI Flash P27 P19 Charger PWM FAN P29 D P6 Thermal Protection P30 +1.05V P35 P33 Quanta Computer Inc http://hobi-elektronika.net P31 PROJECT : ZE7 Size Document Number Date: Rev C3C Block Diagram Wednesday, August 31, 2011 Sheet of 42 CLK GEN (CLK) 02 +3V VDD_CLK_3.3V +1.5V VDD_CLK_1.5V R219 2.2/J_6 L27 PBY160808T-301Y-N/2A/300ohm_6 L32 PBY160808T-301Y-N/2A/300ohm_6 D C285 Place close to L32 C278 10U/10V_8 C254 1U/10V_4 C225 C277 C224 1U/10V_4 1U/10V_4 10U/10V_8 Add 2.2ohm resistor for noise suppress D C242 1U/10V_4 Place close to L27 1U/10V_4 0.1uF near every power pin U12 0.1uF near every power pin VDD_IO can be ranging from 1.05V to 3.3V +1.05V VDD_CLKIO_1.05V R221 L28 2A/300ohm_6 *0/short_6 Place close to L28 C228 C229 C249 C253 10U/10V_8 1U/10V_4 1U/10V_4 1U/10V_4 CG_XOUT CG_XIN VDD_CORE_1.5 23 VDD_PCI_3.3 VDD_CORE_1.5 45 14 VDD_48M_3.3 PCI_STOP# CPU_STOP# 36 42 PM_STPPCI# [13] PM_STPCPU# [13] From SB CPU_0 CPU_0# 53 52 CLK_MCH_BCLK [6] CLK_MCH_BCLK# [6] To CPU (Host CLK) 100 MHz CPU_1 CPU_1# 50 49 CLK_DDR3_REFCLK [8] CLK_DDR3_REFCLK# [8] To CPU (DDR3 IO CLK) 100 MHz SRC_1/CPU_ITP SRC_1/CPU_ITP# 44 43 CLK_PCIE_LANP CLK_PCIE_LANN To LAN (LAN) 100 MHz SRC_2 SRC_2# 41 40 CLK_PCIE_MNC_P CLK_PCIE_MNC_N SRC_3 SRC_3# 38 37 CLK_PCIE_MPC_P [25] CLK_PCIE_MPC_N [25] To Mini Card (WLAN) SRC_4 SRC_4# 34 33 CLK_PCIE_DMIP CLK_PCIE_DMIN To CPU (DMI CLK) 100 MHz SRC_5 SRC_5# 32 31 CLK_PCIE_MMC_P [26] CLK_PCIE_MMC_N [26] To Card Reader (MMC) 100 MHz SRC_6 SRC_6# 28 27 DOT96/SRC7 DOT96#/SRC7# 18 19 30 VDD_SRC_IO_1.05 35 VDD_SRC_IO_1.05 48 VDD_CPU_IO_1.05 0.1uF near every power pin CG_XIN VDD_REF_3.3 13 54 C C238 33P/50V_4 SMBDT1 SMBCK1 [4,13,25] SMBDT1 [4,13,25] SMBCK1 Y2 14.318MHZ NC NC NC NC XTAL_OUT XTAL_IN SDA SCL Load Capacitance=20p C236 33P/50V_4 FSB 15 CG_XOUT [10] CLKUSB_48 Crystal place within 500mil of CK505 [13] 14M_ICH 33/J_4 USB_48M R293 33/J_4 FSC R296 R304 R291 [12] PCLK_ICH [27] LCLK_EC [25] PCLK_DEBUG +3V R312 22/J_4 22/J_4 33/J_4 USB48_2 REF/FSC 10 PCIF/ITP_EN 33M_SEL 11 25MHz/PCI_2/SEL_33MHz R310 *100K_4 17 ITP_EN R311 *20K/J_4 B USB48_1/FSB CFG input hardware strapping to allocate PLL assignment LOW = Both CPU and SRC clock drive from PLL3 HIGH = CPU clock drive from PLL1, SRC clock drive from PLL3 Contains 100kȍ pull-down resistor 12 16 22 24 39 51 56 VSS_PCI VSS_48M VSS_LCD VSS_SATA VSS_SRC VSS_CPU VSS_REF 57 Thermal Pad Reserve 0ohm to connect to CK505, 10Kohm pull up is required LCD_CLK LCD_CLK# 20 21 SATA SATA# 26 25 PM_STPPCI#_R PM_STPCPU#_R DREFCLK_R DREFCLK#_R R251 R229 R299 R300 *0/J_4 *0/J_4 *0/J_4 *0/J_4 [22] [22] [25] [25] [5] [5] C To Mini Card (3G/Wimax) 100 MHz Place R235/ R241/ R248/ R254 close to U13 100 MHz CLK_PCIE_ICH [10] CLK_PCIE_ICH# [10] To SB (DMI CLK) 100 MHz DREFCLK [5] DREFCLK# [5] To CPU (PLL CLK) 96 MHz DREFSSCLK [5] DREFSSCLK# [5] To CPU (DPLSS CLK) 100 MHz registers and logics of the display interface and therefore CLK_PCIE_SATA [11] CLK_PCIE_SATA# [11] To SB (SATA CLK) 100 MHz DPL_REFSSCCLK is used to drive internal needs to be present at all times Add 475ohm resistors to prevent current leakage CLKREQ_A# CLKREQ_B# CLKREQ_C# 47 46 29 CLKREQ_LAN#_R CLKREQ_MPC#_R CLKREQ_MMC#_R CKPWRGD/PD# 55 HWPG R204 R199 R284 475/F_4 475/F_4 475/F_4 CLKREQ_LAN# [22] CLKREQ_MPC# [25] CLKREQ_MMC# [26] HWPG C357 *0.1U/10V_4 SLG8LV631V [13,16,27] B Control SRC_1 Register B5b6 for CLKREQ_A# = SRC1, 1=SRC2 Control SRC_3 Register B5b4 for CLKREQ_B# = SRC3, 1=SRC4 Control SRC_5 Register B5b3 for CLKREQ_C# = SRC5, 1=SRC6 Reserve 0.1F cap to solve that PCICLK (EC 33MHz) sometimes will change to 25MHz after flash BIOS and restart in first time issue +3V +3V A +3V R313 *10K/J_4 R306 10K/J_4 = Pin 43/44 as CPU_ITP R301 10K/J_4 R295 *10K/J_4 ITP_EN = Pin 43/44 as SRC_1 FSC FSB 0 1 1 +3V 33M_SEL = Pin 11 as 33MHz 0= Pin 11 as 25MHz Frequency 133MHz 166MHz 200MHz 100MHz Keep 100MHz as default R289 10K/J_4 R259 *10K/J_4 FSC R317 *10K/J_4 R318 10K/J_4 USB_48M C280 ITP_EN C259 PM_STPPCI#_R R250 10K/J_4 PM_STPCPU#_R R230 10K/J_4 CLKREQ_MPC#_R R213 10K/J_4 CLKREQ_MMC#_R R279 10K/J_4 CLKREQ_LAN#_R R212 10K/J_4 *10P/50V_4 *10P/50V_4 A +3V FSB C279 *10P/50V_4 FSC C245 *10P/50V_4 Quanta Computer Inc FSB 33M_SEL C266 *10P/50V_4 PROJECT : ZE7 Size Document Number Rev C3C CLOCK GENERATOR Date: http://hobi-elektronika.net Sheet Wednesday, August 31, 2011 of 42 03 D D C C B B A A Quanta Computer Inc PROJECT : ZE7 http://hobi-elektronika.net Size Rev C3C Reserved Date: Document Number Wednesday, August 31, 2011 Sheet of 42 DDR_STD(DDR) DIMM0 H=4mm 2.48A M_A_DQ[63:0] [8] M_A_A[15:0] Populate rules: populate SODIMM1 first Strictly follow the mapping between clock/control signal groups and SODIMMs, as well as SMB address Other configurations/mappings will not be supported by MRC +3V DESIGN NOTE: ADDRESS-(A2)H R150 10K/J_4 [8] [8] [8] [8] [8] [8] [8] [8] [8] [8] [8] [8] [8] [8] M_A_BS0 M_A_BS1 M_A_BS2 M_CS#2 M_CS#3 M_CLK2 M_CLK2# M_CLK3 M_CLK3# M_CKE2 M_CKE3 M_A_CAS# M_A_RAS# M_A_WE# [2,13,25] SMBCK1 [2,13,25] SMBDT1 R151 *10K/J_4 C R170 10K/J_4 [8] [8] [8] M_ODT2 M_ODT3 M_A_DM[7:0] [8] M_A_DQS[7:0] [8] M_A_DQS#[7:0] M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14 A15 DIMM1_SA0 DIMM1_SA1 SMBCK1 SMBDT1 109 108 79 114 121 101 103 102 104 73 74 115 110 113 197 201 202 200 BA0 BA1 BA2 S0# S1# CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# W E# SA0 SA1 SCL SDA 116 120 ODT0 ODT1 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 11 28 46 63 136 153 170 187 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 12 29 47 64 137 154 171 188 10 27 45 62 135 152 169 186 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7 PC2100 DDR3 SDRAM SO-DIMM (204P) JDIM1A D DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 15 17 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194 M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 +3V C179 C178 1U/10V_4 1U/10V_4 04 +1.5VSUS [8] [8] DDR3_DRAMRST# +SMDDR_VREF_DQ0 +SMDDR_VREF_DIMM JDIM1B 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 199 VDDSPD 77 122 125 NC1 NC2 NCTEST 198 30 EVENT# RESET# 126 VREF_DQ VREF_CA 13 14 19 20 25 26 31 32 37 38 43 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 PC2100 DDR3 SDRAM SO-DIMM (204P) VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 D C +0.75V_DDR_VTT VTT1 VTT2 203 204 GND GND 205 206 DDR3-DIMM0_H=4_STD PLACE TWO 1K RESISTORS CLOSE TO CPU DIMM ON DDR_VREF_CA +1.5VSUS R198 R191 1K/F_4 *0/J_4 +SMDDR_VREF +SMDDR_VREF_DIMM R205 DDR3-DIMM0_H=4_STD B +SMDDR_VREF +SMDDR_VREF_DIMM_R 0/J_4 B C194 C205 R208 1K/F_4 1U/10V_4 0.1U/50V_6 PLACE TWO 1K RESISTORS CLOSE TO CPU DIMM ON DDR_VREF_DQ Add by DG request Place these Caps near DIMM0 +1.5VSUS +0.75V_DDR_VTT R149 *0/J_4 +SMDDR_VREF 1K/F_4 +SMDDR_VREF_DQ0_R R148 +SMDDR_VREF_DQ0 R146 C172 C200 C190 C185 0/J_4 C176 +1.5VSUS C160 10U/6.3V_6 *10U/6.3V_6 *10U/6.3V_6 1U/6.3V_4 C166 R147 1K/F_4 1U/6.3V_4 1U/10V_4 C171 C169 C193 1U/10V_4 1U/10V_4 1U/10V_4 C163 C168 C198 C199 C197 C196 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 0.1U/50V_6 + C203 *330U/2V_7343 LAYOUT NOTE: PLACE CAPS NEAR DIMM-0 A +SMDDR_VREF A +0.75V_DDR_VTT +1.5VSUS +SMDDR_VREF_DQ0 C191 C162 C173 C164 C165 C161 C192 +SMDDR_VREF_DIMM C175 C184 1U/6.3V_4 1U/6.3V_4 Quanta Computer Inc C189 C170 C167 C216 C214 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/10V_4 2.2U/6.3V_6 1U/10V_4 PROJECT : ZE7 2.2U/6.3V_6 http://hobi-elektronika.net Size Rev C3C DDRIII SO-DIMM-0 Date: Document Number Wednesday, August 31, 2011 Sheet of 42 Cedar View (CPU) R397 R398 U24C *1K/J_4 *1K/J_4 05 +3V CEDARVIEW REV = 1.10 Level Shifter For HDMI DDI0_AUXP DDI0_AUXN T33 T31 [17] [17] [17] [17] [17] [17] [17] [17] TX2_HDMI+ TX2_HDMITX1_HDMI+ TX1_HDMITX0_HDMI+ TX0_HDMITX3_HDMI+ TX3_HDMI- TX2_HDMI+ TX2_HDMITX1_HDMI+ TX1_HDMITX0_HDMI+ TX0_HDMITX3_HDMI+ TX3_HDMI- C66 C67 C61 C68 C43 C44 C41 C42 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 T3 T9 eDP: 7", via, 2.7Gbps R68 R62 +3V *2.2K/J_4 *eDP@2.2K/J_4 [18] DDI1_AUX_DP [18] DDI1_AUX_DN +1.5V R32 0/J_6 C55 DDI1_TX0_DP DDI1_TX0_DN DDI1_TX1_DP DDI1_TX1_DN DDI1_TX2_DP DDI1_TX2_DN DDI1_TX3_DP DDI1_TX3_DN T11 T7 1U/6.3V_4 R45 C DDI0_TXP0 DDI0_TXN0 DDI0_TXP1 DDI0_TXN1 DDI0_TXP2 DDI0_TXN2 DDI0_TXP3 DDI0_TXN3 H15 J15 DDI1_DDC_SCL DDI1_DDC_SDA F25 G27 DDI1_AUX_DP DDI1_AUX_DN D10 C10 D26 DDI1_TX0_DP DDI1_TX0_DN DDI1_TX1_DP DDI1_TX1_DN DDI1_TX2_DP DDI1_TX2_DN DDI1_TX3_DP DDI1_TX3_DN E11 F11 J11 H11 F13 E13 J13 K13 H_RSVD_TP_H17 H_RSVD_TP_J17 J17 H17 BREF1.8V EXT_BANDGAP E15 F15 H21 F22 [13] ACZ_BITCLK_CPU [13] ACZ_SYNC_CPU [13] ACZ_SDINO [13] ACZ_SDOUT_CPU DDI0_HPD G2 G3 F3 F2 D4 C3 B7 A7 R42 33/J_4 ACZ_SDINO_R E22 F21 E21 [13] ACZ_RST#_CPU D14 C14 CRT_RED CRT_GREEN CRT_BLUE B12 B11 C11 CRT_IRTN CRT_IREF D12 A13 CRT_DDC_DATA CRT_DDC_CLK E29 E27 DPL_REFSSCCLKP DPL_REFSSCCLKN F17 E17 CRT_HSYNC CRT_VSYNC CRT_IREF R408 681/F_6 CRT_DDC_SDA CRT_DDC_SCL R414 150/F_4 D DREFSSCLK [2] DREFSSCLK# [2] DREFCLK_R1 DREFCLK#_R1 R406 R405 *0/J_4 *0/J_4 DREFCLK [2] DREFCLK# [2] DDI1_HPD DDI1_TXP0 DDI1_TXN0 DDI1_TXP1 DDI1_TXN1 DDI1_TXP2 DDI1_TXN2 DDI1_TXP3 DDI1_TXN3 RSVD_TP_J17 RSVD_TP_H17 BREF18V BREFREXT LVDS_CLKP LVDS_CLKN AZIL_BCLK AZIL_SYNC H2 H3 LVDS_VREFH LVDS_VREFL LVDS_TXP0 LVDS_TXN0 LVDS_TXP1 LVDS_TXN1 LVDS_TXP2 LVDS_TXN2 LVDS_TXP3 LVDS_TXN3 AZIL_RST# 2.37K/F_4 If you implement XDP, you need the PU 2.2K +3V R426 R428 Remove PU resistor for Intel update Stuff R38/ R39 PU resistor Intel will fixed EDID issue by VGA driver and vbios R61 *0/short_6 *0/short_6 +3V G10 H10 F8 E8 H7 H8 G5 G6 TXLOUT0+ TXLOUT0TXLOUT1+ TXLOUT1TXLOUT2+ TXLOUT2- H4 J4 TXLCLKOUT+ [18] TXLCLKOUT- [18] R39 2.2K/J_4 LCD_CLK R38 2.2K/J_4 LCD_DATA [18] [18] [18] [18] [18] [18] G22 E25 LBKLT_EN F29 INT_LVDS_DIGON_Q PANEL_BKLTCTL PANEL_BKLTEN PANEL_VDDEN AZIL_SDI AZIL_SDO *2.2K/J_4 *2.2K/J_4 LCD_CLK [18] LCD_DATA [18] E10 LIBG F10 LVDS_IBG LVDS_VBG DPL_REFSSCCLK is used to drive internal registers and logics of the display interface and therefore needs to be present at all times T51 T52 G24 H24 LVDS_DDC_CLK LVDS_DDC_DATA DDI1_AUXP DDI1_AUXN [18] [18] [18] LAYOUT NOTE: PLACE THESE RESISTORS CLOSE TO PIN R415 150/F_4 F28 E24 LVDS_CTRL_CLK LVDS_CTRL_DATA DDI1_DDC_SCL DDI1_DDC_SDA R413 150/F_4 [18] [18] R52 R48 RSVD_TP_H15 RSVD_TP_J15 [18] [18] CRT_R CRT_G CRT_B B9 A9 DPL_REFCLKP DPL_REFCLKN IHDA Please follow PDG, we will doing BOM stuff changing in next version CRB 7.5K/F_4 H22 H_RSVD_TP_H15 H_RSVD_TP_J15 DDI1_HPD# [18] DDI1_HPD# [18] [18] [18] [18] [18] [18] [18] [18] DDI0_TX2_DP DDI0_TX2_DN DDI0_TX1_DP DDI0_TX1_DN DDI0_TX0_DP DDI0_TX0_DN DDI0_TX3_DP DDI0_TX3_DN DDI0_AUXP DDI0_AUXN CRT_HSYNC CRT_VSYNC DDI HDMI_DDI0_HPD# [17] HDMI_DDI0_HPD# D C8 B8 DDI0_DDC_SCL DDI0_DDC_SDA VGA H25 J22 [17] DDI0_HDMI_SCL [17] DDI0_HDMI_SDA LVDS HDMI: 7.5", via, 1.65 Gbps C50 *220P/50V_4 +3V INT_LVDS_PWM [18] C51 *220P/50V_4 R58 2.2K/J_4 CRT_DDC_SDA R56 2.2K/J_4 CRT_DDC_SCL R65 *10K/J_4 OF C58 C C65 *220P/50V_4 *220P/50V_4 CDV_22MM_REV1P10 LCD Panel Power (LDS) U24A CEDARVIEW REV = 1.10 +3V C329 U20 ECPWROK TC7SH08FU INT_LVDS_DIGON_Q 1U/10V_4 INT_LVDS_DIGON [18] L3 L2 M3 M2 N2 N1 P2 P3 DMI_TXP0 DMI_TXN0 DMI_TXP1 DMI_TXN1 DMI_TXP2 DMI_TXN2 DMI_TXP3 DMI_TXN3 N9 N8 T2 [2] CLK_PCIE_DMIP [2] CLK_PCIE_DMIN DMI_REF1.5V R360 DMI_RXP0 DMI_RXN0 DMI_RXP1 DMI_RXN1 DMI_RXP2 DMI_RXN2 DMI_RXP3 DMI_RXN3 DMI_TXP0 DMI_TXN0 DMI_TXP1 DMI_TXN1 DMI_TXP2 DMI_TXN2 DMI_TXP3 DMI_TXN3 DMI [10] [10] [10] [10] [10] [10] [10] [10] DMI_REFCLKP DMI_REFCLKN DMI_REF1P5 RSVD_TP_R8 RSVD_TP_R7 DMI_RCOMP K6 K5 L5 L6 L9 L8 N5 N6 R8 R7 T1 DMI_RXP0 DMI_RXN0 DMI_RXP1 DMI_RXN1 DMI_RXP2 DMI_RXN2 DMI_RXP3 DMI_RXN3 DMI_REF1.5V_R R445 [10] [10] [10] [10] [10] [10] [10] [10] 7.5K/F_4 100K_4 R450 +1.5V R355 DMI_REF1.5V Add DMI_REF1.5V to follow CRB v0.7 *0/short_4 OF *0/J_4 C354 1U/10V_4 B CDV_22MM_REV1P10 B Add C354 to follow CRB v0.7 For HDMI deep color mode support (HDM) LCD Panel Backlight (LDS) +3V ECPWROK ECPWROK LBKLT_EN Customer must to use 27MHz due to accuracy concerns(