1 ZH9 Block Diagram (AMD Nile Platform) DDR III,800 MT/s Geneva AMD ASB2 CPU HDT P4 UNBUFFERED DDRIII SODIMM Channel A P15 K125 (Athlon SC) 12W HT1 K325 (Athlon DC) 12W HT1 A A (812 balls ; 27x27mm) P2~5 HyperTransport LINK 16x16 LVDS MUX LVDS CON RS880M P16 HyperTransport LINK0 CPU I/F TMDS(PCIE 4x1) HDMI CON DDRIII DX10 IGP SIDE PORT DDRIII 128MB P17 SIDE PORT MEMORY DAC VGA CON P16 B P6 LVDS B 1X16 PCIE I/F PCIE GEN1 1X4 PCIE I/F WITH SB 6X1 PCIE I/F LAN-AR8152L (21x21mm) P6~9 P21 A-Link X4 3G P23 SB820M WLAN/WiMAX HD AUDIO I/F USB2.0(14)+1.1(2) P23 SATA III(6 PORTS) Headphone Jack MIC In Jack Digital MIC Speaker Header AZALIA CODEC CX20672 P19 4X1 PCIE GEN2 I/F SIM CARD INT RTC SATA II I/F C Mobile 2.5" HDD INT CLK Bluetooth P19 PCI/PCI BDGE P23 C P22 EC P18 HD AUDIO LPC I/F ACPI 1.1 (23x23mm) USB 2.0 P10~14 CCD USB PORT (Lower Right) P20 P16 USB PORT (Upper Right) P20 USB PORT (Left) P20 P24 +1.8V SYSTEM 5V/3V PCU Winbond NPCE781L P27 AMD CPU Core CPU_NB Core P28 DDR 1.5VSUS P30 +1.1V (VLDT) P25 Discharge/+2.5V/ P33 VDDR SMBUS Thermal Protection P31 l.c om EC P32 D P29 Keyboard P34 Touch Pad P18 P18 SPI Flash Charger P25 P26 PWM FAN tm NB CORE ho P26 CPU THERMAL SENSOR P4 f@ BATTERY CHAGER LPC Quanta Computer Inc P4 in IN1 CARDREADER he Document Number xa PROJECT : ZH9 Size Rev 4A Block Diagram Date: Sunday, March 28, 2010 Sheet of 40 D D D U16A HT_CADINN[15 0] HT_CLKINP[1 0] C HT_CLKINN[1 0] HT_CTLINP[1 0] HT_CTLINN[1 0] HT_CADOUTP[15 0] HT_CADOUTN[15 0] HT_CLKOUTP[1 0] HT_CLKOUTN[1 0] HT_CTLOUTP[1 0] HT_CTLOUTN[1 0] HT_CADINP[15 0] HT_CADINN[15 0] HT_CLKINP[1 0] HT_CLKINN[1 0] HT_CTLINP[1 0] HT_CTLINN[1 0] HT_CADOUTP[15 0] HT_CADOUTN[15 0] HT_CLKOUTP[1 0] HT_CLKOUTN[1 0] HT_CTLOUTP[1 0] HT_CTLOUTN[1 0] B AB6HT_CADOUTP15 AB5HT_CADOUTN15 AB9HT_CADOUTP14 AB8HT_CADOUTN14 AC7HT_CADOUTP13 AC6HT_CADOUTN13 AE6HT_CADOUTP12 AE5HT_CADOUTN12 AE9HT_CADOUTP11 AE8HT_CADOUTN11 AH3HT_CADOUTP10 AH4HT_CADOUTN10 AK3HT_CADOUTP9 AK4HT_CADOUTN9 AH1HT_CADOUTP8 AH2HT_CADOUTN8 Y1 HT_CADOUTP7 Y2 HT_CADOUTN7 Y4 HT_CADOUTP6 Y3 HT_CADOUTN6 AB1HT_CADOUTP5 AB2HT_CADOUTN5 AB4HT_CADOUTP4 AB3HT_CADOUTN4 AD4HT_CADOUTP3 AD3HT_CADOUTN3 AF1HT_CADOUTP2 AF2HT_CADOUTN2 AF4HT_CADOUTP1 AF3HT_CADOUTN1 AK1HT_CADOUTP0 AK2HT_CADOUTN0 W7 W6 U6 U5 R7 R6 P6 P5 L6 L5 J6 J5 H4 H3 G6 G5 T3 T4 T2 T1 P3 P4 P2 P1 M2 M1 K3 K4 K2 K1 H2 H1 L0_CADIN_H15 L0_CADIN_L15 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H0 L0_CADIN_L0 HT_CLKINP1 HT_CLKINN1 M8 M7 L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKOUT_H1 L0_CLKOUT_L1 AF6HT_CLKOUTP1 AF5HT_CLKOUTN1 HT_CLKINP0 HT_CLKINN0 M3 M4 L0_CLKIN_H0 L0_CLKIN_L0 L0_CLKOUT_H0 L0_CLKOUT_L0 AD1HT_CLKOUTP0 AD2HT_CLKOUTN0 HT_CTLINP1 HT_CTLINN1 Y6 Y5 L0_CTLIN_H1 L0_CTLIN_L1 L0_CTLOUT_H1 L0_CTLOUT_L1 Y8 HT_CTLOUTP1 Y9 HT_CTLOUTN1 HT_CTLINP0 HT_CTLINN0 V2 V1 L0_CTLIN_H0 L0_CTLIN_L0 L0_CTLOUT_H0 L0_CTLOUT_L0 V4 HT_CTLOUTP0 V3 HT_CTLOUTN0 HT LINK HT_CADINP[15 0] HT_CADINP15 HT_CADINN15 HT_CADINP14 HT_CADINN14 HT_CADINP13 HT_CADINN13 HT_CADINP12 HT_CADINN12 HT_CADINP11 HT_CADINN11 HT_CADINP10 HT_CADINN10 HT_CADINP9 HT_CADINN9 HT_CADINP8 HT_CADINN8 HT_CADINP7 HT_CADINN7 HT_CADINP6 HT_CADINN6 HT_CADINP5 HT_CADINN5 HT_CADINP4 HT_CADINN4 HT_CADINP3 HT_CADINN3 HT_CADINP2 HT_CADINN2 HT_CADINP1 HT_CADINN1 HT_CADINP0 HT_CADINN0 L0_CADOUT_H15 L0_CADOUT_L15 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H0 L0_CADOUT_L0 C B A A Quanta Computer Inc PROJECT : ZH9 Size Document Number Rev 4A ASB2 HT I/F 1/4 Date: Sunday, March 28, 2010 Sheet of 40 A B C D E Processor Memory Interface R29 AC29 AE28 M_A_BANK2 M_A_BANK1 M_A_BANK0 M_A_DQSP7 M_A_DQSN7 M_A_DQSP6 M_A_DQSN6 M_A_DQSP5 M_A_DQSN5 M_A_DQSP4 M_A_DQSN4 M_A_DQSP3 M_A_DQSN3 M_A_DQSP2 M_A_DQSN2 M_A_DQSP1 M_A_DQSN1 M_A_DQSP0 M_A_DQSN0 M_A_CLKP1 M_A_CLKN1 M_A_CLKP2 M_A_CLKN2 MA_ADD15 MA_ADD14 MA_ADD13 MA_ADD12 MA_ADD11 MA_ADD10 MA_ADD9 MA_ADD8 MA_ADD7 MA_ADD6 MA_ADD5 MA_ADD4 MA_ADD3 MA_ADD2 MA_ADD1 MA_ADD0 MA_BANK2 MA_BANK1 MA_BANK0 K30 J29 G29 F29 L28 L29 H29 H27 MA_CHECK7 MA_CHECK6 MA_CHECK5 MA_CHECK4 MA_CHECK3 MA_CHECK2 MA_CHECK1 MA_CHECK0 J27 J26 AJ11 AK12 AG15 AH15 AH22 AG22 AG26 AH26 E28 F28 E25 F25 G17 H17 E12 F12 MA_DQS_H8 MA_DQS_L8 MA_DQS_H7 MA_DQS_L7 MA_DQS_H6 MA_DQS_L6 MA_DQS_H5 MA_DQS_L5 MA_DQS_H4 MA_DQS_L4 MA_DQS_H3 MA_DQS_L3 MA_DQS_H2 MA_DQS_L2 MA_DQS_H1 MA_DQS_L1 MA_DQS_H0 MA_DQS_L0 AK18 AJ17 AH17 AG17 Y28 Y27 AB27 AB26 W27 W26 P26 M26 D18 F19 E20 E19 MA_CLK_H7 MA_CLK_L7 MA_CLK_H6 MA_CLK_L6 MA_CLK_H5 MA_CLK_L5 MA_CLK_H4 MA_CLK_L4 MA_CLK_H3 MA_CLK_L3 MA_CLK_H2 MA_CLK_L2 MA_CLK_H1 MA_CLK_L1 MA_CLK_H0 MA_CLK_L0 M_A_CKE1 M_A_CKE0 M30 M28 M_A_ODT1 M_A_ODT0 AJ29 AF27 AJ30 AG29 MA1_ODT1 MA1_ODT0 MA0_ODT1 MA0_ODT0 M_A_CS#1 M_A_CS#0 AH29 AE29 AH30 AF29 AC27 AF30 AE27 M_A_RAS# M_A_CAS# M_A_WE# M_A_RST# MEMHOT_MA# R285 L27 *0/J_4M32 MA_DATA63 MA_DATA62 MA_DATA61 MA_DATA60 MA_DATA59 MA_DATA58 MA_DATA57 MA_DATA56 MA_DATA55 MA_DATA54 MA_DATA53 MA_DATA52 MA_DATA51 MA_DATA50 MA_DATA49 MA_DATA48 MA_DATA47 MA_DATA46 MA_DATA45 MA_DATA44 MA_DATA43 MA_DATA42 MA_DATA41 MA_DATA40 MA_DATA39 MA_DATA38 MA_DATA37 MA_DATA36 MA_DATA35 MA_DATA34 MA_DATA33 MA_DATA32 MA_DATA31 MA_DATA30 MA_DATA29 MA_DATA28 MA_DATA27 MA_DATA26 MA_DATA25 MA_DATA24 MA_DATA23 MA_DATA22 MA_DATA21 MA_DATA20 MA_DATA19 MA_DATA18 MA_DATA17 MA_DATA16 MA_DATA15 MA_DATA14 MA_DATA13 MA_DATA12 MA_DATA11 MA_DATA10 MA_DATA9 MA_DATA8 MA_DATA7 MA_DATA6 MA_DATA5 MA_DATA4 MA_DATA3 MA_DATA2 MA_DATA1 MA_DATA0 MA_DM8 MA_DM7 MA_DM6 MA_DM5 MA_DM4 MA_DM3 MA_DM2 MA_DM1 MA_DM0 MA_CKE1 MA_CKE0 M_A_DQ[0 63] M_A_DQ63 AG11 M_A_DQ62 AH11 M_A_DQ61 AJ12 M_A_DQ60 AJ14 M_A_DQ59 AF11 M_A_DQ58 AF12 M_A_DQ57 AG12 M_A_DQ56 AH12 M_A_DQ55 AK14 M_A_DQ54 AF15 M_A_DQ53 AH19 M_A_DQ52 AK20 M_A_DQ51 AF14 M_A_DQ50 AG14 M_A_DQ49 AF17 M_A_DQ48 AG19 M_A_DQ47 AG20 M_A_DQ46 AJ20 M_A_DQ45 AF22 M_A_DQ44 AK24 M_A_DQ43 AF19 M_A_DQ42 AF20 M_A_DQ41 AJ23 M_A_DQ40 AG23 M_A_DQ39 AF23 M_A_DQ38 AF25 M_A_DQ37 AH27 M_A_DQ36 AK30 M_A_DQ35 AJ25 M_A_DQ34 AG25 M_A_DQ33 AJ26 M_A_DQ32 AJ28 D28M_A_DQ31 G28M_A_DQ30 D26M_A_DQ29 E26M_A_DQ28 F30M_A_DQ27 E29M_A_DQ26 F27M_A_DQ25 H26M_A_DQ24 H25M_A_DQ23 D24M_A_DQ22 H22M_A_DQ21 E22M_A_DQ20 F26M_A_DQ19 G26M_A_DQ18 D22M_A_DQ17 G23M_A_DQ16 G22M_A_DQ15 G20M_A_DQ14 G15M_A_DQ13 F15M_A_DQ12 D20M_A_DQ11 F22M_A_DQ10 D16M_A_DQ9 E17M_A_DQ8 H15M_A_DQ7 H14M_A_DQ6 G12M_A_DQ5 H12M_A_DQ4 E15M_A_DQ3 E14M_A_DQ2 E11M_A_DQ1 F11M_A_DQ0 H30 AL12M_A_DM7 AK16M_A_DM6 AK22M_A_DM5 AJ27M_A_DM4 E27 M_A_DM3 E23 M_A_DM2 H19 M_A_DM1 G14 M_A_DM0 M_A_DM[0 7] P33 P31 AJ33 T32 T31 AD32 T33 V32 U33 V33 V31 W33 Y31 Y33 Y32 AC33 MB_ADD15 MB_ADD14 MB_ADD13 MB_ADD12 MB_ADD11 MB_ADD10 MB_ADD9 MB_ADD8 MB_ADD7 MB_ADD6 MB_ADD5 MB_ADD4 MB_ADD3 MB_ADD2 MB_ADD1 MB_ADD0 R33 AD33 AE33 MB_BANK2 MB_BANK1 MB_BANK0 K33 K31 G32 F32 L33 K32 H31 G33 MB_CHECK7 MB_CHECK6 MB_CHECK5 MB_CHECK4 MB_CHECK3 MB_CHECK2 MB_CHECK1 MB_CHECK0 J33 H32 AM14 AN14 AL20 AM20 AN26 AM26 AN30 AM30 D33 D32 B28 A28 A21 B20 B16 A15 MB_DQS_H8 MB_DQS_L8 MB_DQS_H7 MB_DQS_L7 MB_DQS_H6 MB_DQS_L6 MB_DQS_H5 MB_DQS_L5 MB_DQS_H4 MB_DQS_L4 MB_DQS_H3 MB_DQS_L3 MB_DQS_H2 MB_DQS_L2 MB_DQS_H1 MB_DQS_L1 MB_DQS_H0 MB_DQS_L0 AN22 AM22 AN21 AM21 AA32 AA33 AB33 AB32 AB31 AB30 AD31 AD30 C22 B22 A22 A23 MB_CLK_H7 MB_CLK_L7 MB_CLK_H6 MB_CLK_L6 MB_CLK_H5 MB_CLK_L5 MB_CLK_H4 MB_CLK_L4 MB_CLK_H3 MB_CLK_L3 MB_CLK_H2 MB_CLK_L2 MB_CLK_H1 MB_CLK_L1 MB_CLK_H0 MB_CLK_L0 N33 P32 MB_CKE1 MB_CKE0 AK31 AH31 AK32 AH33 MB1_ODT1 MB1_ODT0 MB0_ODT1 MB0_ODT0 MA1_CS_L1 MA1_CS_L0 MA0_CS_L1 MA0_CS_L0 AK33 AF33 AJ32 AF31 MB1_CS_L1 MB1_CS_L0 MB0_CS_L1 MB0_CS_L0 MA_RAS_L MA_CAS_L MA_WE_L AF32 AH32 AG33 MB_RAS_L MB_CAS_L MB_WE_L L32 M33 MA_RESET_L FREE|MA_EVENT_L MB_DATA63 MB_DATA62 MB_DATA61 MB_DATA60 MB_DATA59 MB_DATA58 MB_DATA57 MB_DATA56 MB_DATA55 MB_DATA54 MB_DATA53 MB_DATA52 MB_DATA51 MB_DATA50 MB_DATA49 MB_DATA48 MB_DATA47 MB_DATA46 MB_DATA45 MB_DATA44 MB_DATA43 MB_DATA42 MB_DATA41 MB_DATA40 MB_DATA39 MB_DATA38 MB_DATA37 MB_DATA36 MB_DATA35 MB_DATA34 MB_DATA33 MB_DATA32 MB_DATA31 MB_DATA30 MB_DATA29 MB_DATA28 MB_DATA27 MB_DATA26 MB_DATA25 MB_DATA24 MB_DATA23 MB_DATA22 MB_DATA21 MB_DATA20 MB_DATA19 MB_DATA18 MB_DATA17 MB_DATA16 MB_DATA15 MB_DATA14 MB_DATA13 MB_DATA12 MB_DATA11 MB_DATA10 MB_DATA9 MB_DATA8 MB_DATA7 MB_DATA6 MB_DATA5 MB_DATA4 MB_DATA3 MB_DATA2 MB_DATA1 MB_DATA0 AN13 AL14 AL16 AN17 AN12 AM12 AM16 AN16 AL18 AN19 AM24 AN24 AM18 AN18 AL22 AN23 AM25 AL26 AN28 AL28 AL24 AN25 AN27 AM28 AM29 AL30 AL32 AL33 AK28 AN29 AM31 AM32 E33 D31 B31 A31 F33 F31 C32 B32 C30 A29 B26 A26 B30 A30 A27 C26 A24 B24 C18 A18 A25 C24 C20 A19 C16 A16 B14 A13 B18 A17 C14 A14 MB_DM8 MB_DM7 MB_DM6 MB_DM5 MB_DM4 MB_DM3 MB_DM2 MB_DM1 MB_DM0 H33 AN15 AN20 AK26 AN31 C33 C28 A20 D14 MB_RESET_L FREE|MB_EVENT_L l.c om U16C DDR III: CHANNEL A M_A_A15 P30 M_A_A14 M29 M_A_A13AG28 M_A_A12 P28 M_A_A11 T30 M_A_A10AC28 M_A_A9 P27 M_A_A8 R26 M_A_A7 R27 M_A_A6 U28 M_A_A5 V30 M_A_A4 U27 M_A_A3 Y30 M_A_A2 AB29 M_A_A1 W29 M_A_A0 AC26 DDR III: CHANNEL B U16B M_A_A[0 15] ho tm BOM@ASB2_CPU f@ Quanta Computer Inc PROJECT : ZH9 in Route as 60 ohms with 5/10 W/S from CPU pins Note> : AJ00105VT00 : AJ0K125VT02 : AJ0K325VT02 : AJ0K625VT03 Size Document Number xa CPU_TEST23_TSTUPD PD with 1K and add a test point R330 *300/J_4 +1.1V_CPU_VLDT T58 CPU_PRESENT_L V10 CPU_HTREF1 CPU_HTREF0 V9 HTREF1 HTREF0 CPU_TEST9_ANALOGIN G8 CPU_TEST17_BP3 CPU_TEST16_BP2 CPU_TEST15_BP1 CPU_TEST14_BP0 F8 C8 D9 E8 BYPASSCLK_H BYPASSCLK_L PLLTEST0 PLLTEST1 Place them to CPU within 1.5" R76 R75 44.2/F_4 44.2/F_4 +1.1V_CPU_VLDT C T82 T8 T6 T59 CPU_TEST7_ANALOG_T CPU_TEST6_DIECRACKMON CPU_TEST3 CPU_TEST2 BP3 BP2 BP1 BP0 C6 AH7 AK5 AJ7 B10 CPU_TEST29_H_FBCLKOUT_P A10 CPU_TEST29_L_FBCLKOUT_N R310 FBCLKOUT_H FBCLKOUT_L SCANCLK1 TSTUPD SCANSHIFTEN SCANEN SCANCLK2 ANALOGIN CPU_ALERT_L ANALOG_T DIECRACKMON GATE0 DRAIN0 PLLCHRZ_H PLLCHRZ_L SINGLECHAIN BURNIN_L ANALOGOUT DIG_T +3V CPU FAN(THM) CPU_TEST15_BP1 CPU_TEST14_BP0 CPU_TEST21_SCANEN CPU_TEST20_SCANCLK2 CPU_TEST25_L_BYPASSCLK_L CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1 CPU_TEST24_SCANCLK1 CPU_TEST22_SCANSHIFTEN CPU_TEST23_TSTUPD CPU_TEST9_ANALOGIN +1.5VSUS Route as 80ohm, diff Q7 MMBT3904 1K/J_4 300/J_4 510/F_4 1K/J_4 1K/J_4 CPU_DBRDY H9 DBRDY VSS_SENSE VLDT_SENSE VDD_SENSE VDDNB_SENSE VDDIO_SENSE VDDR_SENSE CPU_M_VREF A11 M_ZP AM9 M_ZN AN9 R268 R307 R135 R264 R269 CPU_TEST10_ANALOGOUT DBREQ_L D2 E2 E1 D1 D3 C2 CPU_PRESENT_L CPU_DBREQ# CPU_TEST25_H_BYPASSCLK_H CPU_TEST26_BURNIN_L CPU_TEST27_SINGLECHAIN AN7 CPU_TDO TDO CPU_SIC RB501V-40 2ND_MBDATA M31 CPU_CORE_TYPE RSVD|CORE_TYPE PWROK LDTSTOP_L RESET_L CLOSE TO CPU WITHIN 1" D3 CPU_VLDT_FB_H CPU_M_VREF R271 2ND_MBCLK T60 CPU_VDD_FB_H CPU_VDDNB_FB_H CPU_VDDIO_FB_H CPU_VDDR_FB_H R324 1K/F_4 R53 2.2K/J_4 R50 1K/J_4 CLKIN_H CLKIN_L CPU_SIC AN4 CPU_SID AN5 RSVD_SA0 AM2 CPU_ALERT_L AN3 Layout Note:Routing 10:10 mils and away from noise source with ground gard +1.5VSUS C MISC SideBand Temp sense I2C *10K/J_4 R48 2.2K/J_4 A6 A7 CPU_PWRGD D10 CPU_LDT_STOP# E9 CPU_LDT_RST# F9 THERM_OVERT# R51 2.2K/J_4 U16D VDDA_1 VDDA_2 3900P/25V_4 CPU_PWRGD CPU_LDT_STOP# CPU_LDT_RST# H_THERMDC C366 W/S= 15 mil/20mil +CPUVDDA A8 +CPUVDDA B8 AK7 AG8 AK9 AH9 AM7 CPU_TEST24_SCANCLK1 CPU_TEST23_TSTUPD CPU_TEST22_SCANSHIFTEN CPU_TEST21_SCANEN CPU_TEST20_SCANCLK2 G11 H11 AJ8 AM4 D7 B5 CPU_TEST28_H_PLLCHRZ_P CPU_TEST28_L_PLLCHRZ_N CPU_TEST27_SINGLECHAIN CPU_TEST26_BURNIN_L CPU_TEST10_ANALOGOUT CPU_TEST8_DIG_T 80.6/F_4 T7 route as differential as short as possible testpoint under package T15 T14 T81 AG9 M_TEST +1.5VSUS R44 10K/J_4 R39 10K/J_4 FANSIG +5V *0/J_4 THERM_FAN# THERM_ALERT# *0/short_4 THERM_OVERT# R410 CN13 R34 B CPUFAN# FAN_PWM_CN Q6 CPU_THERMTRIP_L# 25 36 10K/J_4 R411 R45 1K/J_4 B MMBT3904 R41 *0/J_4 R46 *0/short_4 CPU_THERMTRIP# SYS_SHDN# FAN CONN Q5 MMBT3904 R31 +5V *0/short_6 FAN CONN Follow PDC pin define +5V_FANVCC R265 +1.5VSUS 300/J_4 CPU_PROCHOT_L# C29 R273 *0/short_4 R272 *0/short_4 CPU_PROCHOT# SB_PROCHOT# 0.01U/25V_4 HDT Connector +1.5VSUS CPU_DBREQ# CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO *HDT@0.1U/10V_4 KEY 10 12 14 16 18 20 22 24 25 Q18 R371 *HDT@4.7K/J_4 11 13 15 17 19 21 23 A C431 Serial VID +1.5V +3V CPU_LDT_RST# To override VID, Remove three 0ohms and install 220ohm of CPU_PWRGD to GND +1.5V R321 *2.2K/J_4 +1.5VSUS +1.5V R326 R331 1K/J_4 *1K/J_4 +1.5VSUS +1.5V R322 R328 1K/J_4 *1K/J_4 SVC/SVD net are pulled up to VDDIO with 1Kohm *HDT@FDV301N CPU_SVC_R CPU_SVD_R CPU_PWRGD R312 R318 R323 *0/short_4 *0/short_4 *0/short_4 CPU_LDT_RST_HT# R313 R317 R329 CPU_SVC CPU_SVD CPU_PWRGD_SVID_REG CPU_SVC CPU_SVD CPU_PWRGD_SVID_REG Pre-PWROK Metal MODE SVC SVD Voltage Output 0 1 1 1.1V 1.0V 0.9V 0.8V VFIX MODE(Don't Support) Voltage Output 1.4V 1.2V 1.0V 0.8V Quanta Computer Inc *220/J_4 *220/J_4 *220/J_4 PROJECT : ZH9 Size CN18 *HDT@HDT CONN Document Number Rev 4A ASB2 CTRL & DEBUG 3/4 Date: A Sunday, March 28, 2010 Sheet of 40 CPU_CORE +1.5VSUS U16F POWER1 VDD_85 VDD_84 VDD_83 VDD_82 VDD_81 VDD_80 VDD_79 VDD_78 VDD_77 VDD_76 VDD_75 VDD_74 VDD_73 VDD_72 VDD_71 VDD_70 VDD_69 VDD_68 VDD_67 VDD_66 VDD_65 VDD_64 VDD_63 VDD_62 VDD_61 VDD_60 VDD_59 VDD_58 VDD_57 VDD_56 VDD_55 VDD_54 VDD_53 VDD_52 VDD_51 VDD_50 VDD_49 VDD_48 VDD_47 VDD_46 VDD_45 VDD_44 AE12 AD9 AE21 AD21 AD18 AD14 AD12 AD11 AC5 AE18 AC24 AC12 AC10 AB13 AB11 AE14 AA24 AA12 AA10 Y19 Y16 Y14 W5 W20 W18 W15 AE23 V24 V19 V16 V14 T20 T18 T15 T10 R5 R19 R16 R14 AC4 P24 P20 M27 Y26 U26 N32 U32 N30 P29 R28 R30 R32 U29 U30 W28 W30 W32 Y29 AA30 AB28 AE32 AC30 AC32 AE26 AE30 AF28 AG30 AG32 AD25 AA25 AC25 V25 P25 N25 M25 K25 L25 T25 Y25 AB25 VDDIO_1 VDDIO_2 VDDIO_3 VDDIO_4 VDDIO_5 VDDIO_6 VDDIO_7 VDDIO_8 VDDIO_9 VDDIO_10 VDDIO_11 VDDIO_12 VDDIO_13 VDDIO_14 VDDIO_15 VDDIO_16 VDDIO_17 VDDIO_18 VDDIO_19 VDDIO_20 VDDIO_21 VDDIO_22 VDDIO_23 VDDIO_24 VDDIO_25 VDDIO_26 VDDIO_27 VDDIO_28 VDDIO_29 VDDIO_30 VDDIO_31 VDDIO_32 VDDIO_33 VDDIO_34 VDDIO_35 VDDIO_36 VDDIO_37 VDDIO_38 VLDT_A_1 VLDT_A_2 VLDT_A_3 VLDT_A_4 F1 F2 F3 F4 VLDT_B_1 VLDT_B_2 VLDT_B_3 VLDT_B_4 AL1 AL2 AL3 AL4 AK10 AL10 AM10 AN10 VDDR_5 VDDR_6 VDDR_7 VDDR_8 CPU_VDDR 0.8~1.1V CPU_VDDNB_CORE A3 A4 B3 B4 C3 C4 VDDNB_1 VDDNB_2 VDDNB_3 VDDNB_4 VDDNB_5 VDDNB_6 B11 PROGEN_L G7 B7 AH8 AJ6 B25 AM3 AN11 P9 P8 FREE_1 FREE_2 FREE_3 FREE_4 FREE_5 FREE_6 FREE_7 FREE_8 FREE_9 C BOM@ASB2_CPU BOM@ASB2_CPU CPU_CORE BOTTOM SIDE DECOUPLING CPU_CORE 15A Add two 4.7uF for CPU_CORE + PC43 330U/2V_7343 C85 22U/6.3V_8 C87 22U/6.3V_8 C124 22U/6.3V_8 C123 22U/6.3V_8 C120 0.22U/6.3V_4 C125 0.01U/25V_4 CPU_CORE U16H U16G B1 N2 N22 N23 B13 B15 B17 M21 B19 B21 B23 B27 B29 B33 C10 P10 P14 P16 P19 P7 C31 D11 D13 D15 R1 D17 D19 D21 D23 D25 D27 R15 R18 R2 R20 D29 D30 D8 E30 E32 F14 F17 R8 T14 T16 F20 T19 T24 T9 U1 F23 N1 G1 G19 G2 G25 G27 N10 A12 B12 C12 D12 VDDR_1 VDDR_2 VDDR_3 VDDR_4 POWER2 D VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 PROCESSOR POWER AND GROUND +1.1V_CPU_VLDT U16E D4 D5 D6 E5 E6 E7 F5 F6 F7 H7 H8 J8 E4 J10 J12 J14 J18 J20 J21 J23 J9 K10 K12 K14 K18 K20 K21 K23 N4 L11 L13 L7 L9 M10 M12 R4 M5 N11 N24 W4 N9 P15 P18 C130 180P/50V_4 C106 4.7U/6.3V_6 C105 4.7U/6.3V_6 VSS_1 VSS_28 VSS_29 VSS_30 VSS_2 VSS_3 VSS_4 VSS_27 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_12 VSS_13 VSS_14 VSS_15 VSS_36 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_37 VSS_38 VSS_39 VSS_40 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_115 VSS_45 VSS_44 VSS_43 VSS_42 VSS_26 VSS_25 VSS_41 VSS_24 VSS_23 VSS_22 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 W19 W1 V20 V18 M11 L8 V15 L4 L30 L26 L24 L23 L22 L21 L2 L12 L10 L1 K9 M6 K24 K22 K16 M22 K13 M24 K11 M23 J7 W16 J4 W14 J32 J30 M13 J28 U8 J25 U4 J24 U7 U2 J2 J16 J13 J11 J1 H6 H5 H28 H23 H20 J22 M9 G4 G30 N12 AM19 AF7 AF26 AE7 AF8 AF9 AG1 AG2 AG27 AG4 AG5 AG6 AG7 AE4 AE25 AE24 AE22 AE20 AE2 AE16 AE13 AH14 AE11 AE10 AE1 AD24 AD23 AD22 AH20 AH23 AH25 AH28 AD20 AD16 AD13 AD10 AC9 AC8 A2 AC23 AH5 AJ1 AJ15 W2 A32 W8 Y10 Y15 Y18 AJ19 AJ2 AJ22 AJ4 Y20 Y24 AK11 AK13 Y7 AA1 AA11 CPU_VDDNB_CORE VSS_207 VSS_167 VSS_166 VSS_165 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_164 VSS_163 VSS_162 VSS_161 VSS_160 VSS_159 VSS_158 VSS_157 VSS_177 VSS_156 VSS_155 VSS_154 VSS_153 VSS_152 VSS_151 VSS_178 VSS_179 VSS_180 VSS_181 VSS_150 VSS_149 VSS_148 VSS_147 VSS_146 VSS_145 VSS_214 VSS_144 VSS_182 VSS_183 VSS_184 VSS_116 VSS_213 VSS_117 VSS_118 VSS_119 VSS_120 VSS_185 VSS_186 VSS_187 VSS_188 VSS_121 VSS_122 VSS_189 VSS_190 VSS_123 VSS_124 VSS_125 GND2 CPU_CORE GND1 0.7~1.1V AK15 AK17 AK19 AK21 AA2 AA22 AA23 AK23 AA4 AA9 AB10 AB12 AB21 AB22 AB23 AB24 AK25 AK27 AK29 AJ5 AH6 AL31 AM1 AM13 AB7 AC1 AM15 AM17 AC11 AC13 AC2 AC21 AC22 AM23 AM27 AM33 AN2 AN32 AM11 VSS_191 VSS_192 VSS_193 VSS_194 VSS_126 VSS_127 VSS_128 VSS_195 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_137 VSS_138 VSS_205 VSS_206 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_215 D C BOM@ASB2_CPU 2A BOM@ASB2_CPU C86 22U/6.3V_8 C84 22U/6.3V_8 C122 22U/6.3V_8 C121 22U/6.3V_8 C109 0.22U/6.3V_4 C110 0.01U/25V_4 C83 180P/50V_4 C354 22U/6.3V_8 C380 22U/6.3V_8 C371 22U/6.3V_8 PLACE CLOSE TO PROCESSOR AS POSSIBLE +1.5VSUS 3A B CPU_VDDR 1A C103 22U/6.3V_8 C96 22U/6.3V_8 C129 C79 C325 C322 C75 C114 C108 C76 10U/6.3V_8 10U/6.3V_8 0.22U/6.3V_4 0.22U/6.3V_4 0.22U/6.3V_4 0.22U/6.3V_4 0.22U/6.3V_4 0.22U/6.3V_4 +1.5VSUS Add two 0.1uF for +1.5VSUS C71 4.7U/6.3V_6 C327 0.1U/10V_4 C318 0.01U/25V_4 C72 C73 0.22U/6.3V_4 0.22U/6.3V_4 C77 180P/50V_4 R351 C89 C112 10U/6.3V_8 10U/6.3V_8 C360 4.7U/6.3V_6 C350 C343 0.22U/6.3V_4 0.22U/6.3V_4 1.5A For VLDT_A For VLDT_B *0/short_8 +1.1V_CPU_VLDT C319 4.7U/6.3V_6 C317 C321 22U/6.3V_8 0.22U/6.3V_4 C320 180P/50V_4 C368 4.7U/6.3V_6 C356 0.22U/6.3V_4 C352 180P/50V_4 l.c om DECOUPLING BETWEEN PROCESSOR AND DIMMs PLACE CLOSE TO PROCESSOR AS POSSIBLE A C97 4.7U/6.3V_6 C88 4.7U/6.3V_6 C78 4.7U/6.3V_6 C326 C329 0.22U/6.3V_4 0.22U/6.3V_4 C323 180P/50V_4 tm ho C92 4.7U/6.3V_6 Quanta Computer Inc C324 180P/50V_4 in PROJECT : ZH9 f@ +1.5VSUS If VSS plane is cut for VDDIO, place two 0.22uF & 180pF across the VDDIO-VSS Size xa A Group2 Add two 10uF for +1.5VSUS +1.1V C328 0.1U/10V_4 Group1 Document Number Rev 4A ASB2 PWR & GND 4/4 Date: Sunday, March 28, 2010 he B Sheet of 40 U20A D R320 Y25 Y24 V22 V23 V25 V24 U24 U25 T25 T24 P22 P23 P25 P24 N24 N25 HT_RXCAD0P HT_RXCAD0N HT_RXCAD1P HT_RXCAD1N HT_RXCAD2P HT_RXCAD2N HT_RXCAD3P HT_RXCAD3N HT_RXCAD4P HT_RXCAD4N HT_RXCAD5P HT_RXCAD5N HT_RXCAD6P HT_RXCAD6N HT_RXCAD7P HT_RXCAD7N PART OF HT_CADOUTP8 HT_CADOUTN8 HT_CADOUTP9 HT_CADOUTN9 HT_CADOUTP10 HT_CADOUTN10 HT_CADOUTP11 HT_CADOUTN11 HT_CADOUTP12 HT_CADOUTN12 HT_CADOUTP13 HT_CADOUTN13 HT_CADOUTP14 HT_CADOUTN14 HT_CADOUTP15 HT_CADOUTN15 AC24 AC25 AB25 AB24 AA24 AA25 Y22 Y23 W21 W20 V21 V20 U20 U21 U19 U18 HT_RXCAD8P HT_RXCAD8N HT_RXCAD9P HT_RXCAD9N HT_RXCAD10P HT_RXCAD10N HT_RXCAD11P HT_RXCAD11N HT_RXCAD12P HT_RXCAD12N HT_RXCAD13P HT_RXCAD13N HT_RXCAD14P HT_RXCAD14N HT_RXCAD15P HT_RXCAD15N HT_CLKOUTP0 HT_CLKOUTN0 HT_CLKOUTP1 HT_CLKOUTN1 T22 T23 AB23 AA22 HT_RXCLK0P HT_RXCLK0N HT_RXCLK1P HT_RXCLK1N HT_CTLOUTP0 HT_CTLOUTN0 HT_CTLOUTP1 HT_CTLOUTN1 M22 M23 R21 R20 HT_RXCALP HT_RXCALN 301/F_4 C23 A24 HT_RXCTL0P HT_RXCTL0N HT_RXCTL1P HT_RXCTL1N HYPER TRANSPORT CPU I/F HT_CADOUTP0 HT_CADOUTN0 HT_CADOUTP1 HT_CADOUTN1 HT_CADOUTP2 HT_CADOUTN2 HT_CADOUTP3 HT_CADOUTN3 HT_CADOUTP4 HT_CADOUTN4 HT_CADOUTP5 HT_CADOUTN5 HT_CADOUTP6 HT_CADOUTN6 HT_CADOUTP7 HT_CADOUTN7 D24 D25 E24 E25 F24 F25 F23 F22 H23 H22 J25 J24 K24 K25 K23 K22 HT_CADINP0 HT_CADINN0 HT_CADINP1 HT_CADINN1 HT_CADINP2 HT_CADINN2 HT_CADINP3 HT_CADINN3 HT_CADINP4 HT_CADINN4 HT_CADINP5 HT_CADINN5 HT_CADINP6 HT_CADINN6 HT_CADINP7 HT_CADINN7 HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N F21 G21 G20 H21 J20 J21 J18 K17 L19 J19 M19 L18 M21 P21 P18 M18 HT_CADINP8 HT_CADINN8 HT_CADINP9 HT_CADINN9 HT_CADINP10 HT_CADINN10 HT_CADINP11 HT_CADINN11 HT_CADINP12 HT_CADINN12 HT_CADINP13 HT_CADINN13 HT_CADINP14 HT_CADINN14 HT_CADINP15 HT_CADINN15 HT_TXCLK0P HT_TXCLK0N HT_TXCLK1P HT_TXCLK1N H24 H25 L21 L20 HT_CLKINP0 HT_CLKINN0 HT_CLKINP1 HT_CLKINN1 M24 M25 P19 R18 HT_CTLINP0 HT_CTLINN0 HT_CTLINP1 HT_CTLINN1 B24 B25 HT_TXCALP R115 HT_TXCALN HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N HT_TXCTL0P HT_TXCTL0N HT_TXCTL1P HT_TXCTL1N HT_RXCALP HT_RXCALN HT_TXCALP HT_TXCALN HT_CADOUTP[15 0] HT_CADOUTP[15 0] HT_CADOUTN[15 0] HT_CADOUTN[15 0] HT_CLKOUTP[1 0] HT_CLKOUTP[1 0] HT_CLKOUTN[1 0] HT_CLKOUTN[1 0] HT_CTLOUTP[1 0] HT_CTLOUTP[1 0] HT_CTLOUTN[1 0] HT_CTLOUTN[1 0] HT_CADINP[15 0] HT_CADINP[15 0] HT_CADINN[15 0] HT_CADINN[15 0] D HT_CLKINP[1 0] HT_CLKINP[1 0] HT_CLKINN[1 0] HT_CLKINN[1 0] HT_CTLINP[1 0] HT_CTLINP[1 0] HT_CTLINN[1 0] HT_CTLINN[1 0] 301/F_4 RS880M 25mils 0.5A +1.5V_SPM_VDDQ C +1.5V R378 C442 C424 SPM@0.1U/10V_4 SPM@0.1U/10V_4 C425 SPM@1U/10V_4 C *0/short_6 C441 C436 C439 SPM@1U/10V_4 SPM@10U/6.3V_8 SPM@10U/6.3V_8 U20D B SPM_VREFCA SPM_VREFDQ M8 H1 SPM_A0 SPM_A1 SPM_A2 SPM_A3 SPM_A4 SPM_A5 SPM_A6 SPM_A7 SPM_A8 SPM_A9 SPM_A10 SPM_A11 SPM_A12 SPM_A13 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 SPM_BA0 SPM_BA1 SPM_BA2 M2 N8 M3 SPM_CLKP SPM_CLKN SPM_CKE J7 K7 K9 VREFCA VREFDQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 BA0 BA1 BA2 CK CK CKE DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9 E3 F7 F2 F8 H3 H8 G2 H7 SPM_DQ2 SPM_DQ1 SPM_DQ3 SPM_DQ0 SPM_DQ7 SPM_DQ4 SPM_DQ5 SPM_DQ6 D7 C3 C8 C2 A7 A2 B8 A3 SPM_DQ11 SPM_DQ8 SPM_DQ12 SPM_DQ14 SPM_DQ9 SPM_DQ10 SPM_DQ15 SPM_DQ13 B2 D9 G7 K2 K8 N1 N9 R1 R9 T52 PAR OF SPM_A0 SPM_A1 SPM_A2 SPM_A3 SPM_A4 SPM_A5 SPM_A6 SPM_A7 SPM_A8 SPM_A9 SPM_A10 SPM_A11 SPM_A12 SPM_A13 AB12 AE16 V11 AE15 AA12 AB16 AB14 AD14 AD13 AD15 AC16 AE13 AC14 Y14 SPM_BA0 SPM_BA1 SPM_BA2 AD16 AE17 AD17 SPM_RAS# SPM_CAS# SPM_WE# SPM_CS# SPM_CKE SPM_ODT +1.5V_SPM_VDDQ W12 Y12 AD18 AB13 AB18 V14 *SPM@100/F_4 V15 W14 R161 SPM_CLKP SPM_CLKN R358 R359 +1.5V_SPM_VDDQ SPM@40.2/F_4 SPM@40.2/F_4 SPM_COMPP AE12 SPM_COMPN AD12 MEM_A0(NC) MEM_A1(NC) MEM_A2(NC) MEM_A3(NC) MEM_A4(NC) MEM_A5(NC) MEM_A6(NC) MEM_A7(NC) MEM_A8(NC) MEM_A9(NC) MEM_A10(NC) MEM_A11(NC) MEM_A12(NC) MEM_A13(NC) MEM_BA0(NC) MEM_BA1(NC) MEM_BA2(NC) SBD_MEM/DVO_I/F U7 MEM_RASb(NC) MEM_CASb(NC) MEM_WEb(NC) MEM_CSb(NC) MEM_CKE(NC) MEM_ODT(NC) MEM_DQ0/DVO_VSYNC(NC) MEM_DQ1/DVO_HSYNC(NC) MEM_DQ2/DVO_DE(NC) MEM_DQ3/DVO_D0(NC) MEM_DQ4(NC) MEM_DQ5/DVO_D1(NC) MEM_DQ6/DVO_D2(NC) MEM_DQ7/DVO_D4(NC) MEM_DQ8/DVO_D3(NC) MEM_DQ9/DVO_D5(NC) MEM_DQ10/DVO_D6(NC) MEM_DQ11/DVO_D7(NC) MEM_DQ12(NC) MEM_DQ13/DVO_D9(NC) MEM_DQ14/DVO_D10(NC) MEM_DQ15/DVO_D11(NC) AA18 AA20 AA19 Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21 SPM_DQ0 SPM_DQ1 SPM_DQ2 SPM_DQ3 SPM_DQ4 SPM_DQ5 SPM_DQ6 SPM_DQ7 SPM_DQ8 SPM_DQ9 SPM_DQ10 SPM_DQ11 SPM_DQ12 SPM_DQ13 SPM_DQ14 SPM_DQ15 MEM_DQS0P/DVO_IDCKP(NC) MEM_DQS0N/DVO_IDCKN(NC) MEM_DQS1P(NC) MEM_DQS1N(NC) Y17 W18 AD20 AE21 SPM_DQS0P SPM_DQS0N SPM_DQS1P SPM_DQS1N MEM_DM0(NC) MEM_DM1/DVO_D8(NC) W17 AE19 SPM_DM0 SPM_DM1 AE23 AE24 +1.8V_NB_IOPLLVDD18 +1.1V_NB_IOPLLVDD IOPLLVDD18(NC) IOPLLVDD(NC) MEM_CKP(NC) MEM_CKN(NC) MEM_COMPP(NC) MEM_COMPN(NC) IOPLLVSS(NC) AD23 MEM_VREF(NC) AE18 B L46 L45 BOM@1.4A/220ohm_6 BOM@1.4A/220ohm_6 +1.8V +1.1V 15mA 26mA SPM_VREF C410 C409 SPM@2.2U/6.3V_6 SPM@2.2U/6.3V_6 RS880M SPM_ODT SPM_CS# SPM_RAS# SPM_CAS# SPM_WE# K1 L2 J3 K3 L3 SPM_DQS0P SPM_DQS1P F3 C7 SPM_DM0 SPM_DM1 E7 D3 ODT CS RAS CAS WE DQSL DQSU VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9 A1 A8 C1 C9 D2 E9 F1 H2 H9 +1.5V_SPM_VDDQ +1.5V_SPM_VDDQ +1.5V_SPM_VDDQ SPM_DQS0N SPM_DQS1N +1.5V_SPM_VDDQ G3 B7 R376 DML DMU DQSL DQSU SPM@10K/J_4 T2 SP_DDR3_RST# L8 RESET ZQ R373 A SPM@243/F_4 J1 L1 J9 L9 NC#J1 NC#L1 NC#J9 NC#L9 VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9 VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 B1 B9 D1 D8 E2 E8 F9 G1 G9 SDRAM DDR3 BOM@DDR3 SDRAM side port memory use DD3 C443 SPM@0.1U/10V_4 R379 SPM@1K/F_4 C418 SPM@0.1U/10V_4 SPM_VREFDQ C440 SPM@0.1U/10V_4 R366 SPM@1K/F_4 C414 SPM@0.1U/10V_4 SPM_VREFCA R377 SPM@1K/F_4 C417 SPM@0.1U/10V_4 R365 SPM@1K/F_4 w/ sideport: L45,L46:CX8PG221003 w/o sideport: L45,L46:CS00003J951(0ohm) R357 SPM@1K/F_4 SPM_VREF C413 SPM@0.1U/10V_4 R356 SPM@1K/F_4 A w/ sideport: U7: AKD5LGGT506 : SAMSUNG DDRIII 800 1Gb K4W1G1646E-HC12 LF AKD5LZGTW04 : HYNIX DDRIII 800 1Gb H5TQ1G63BFR-12C LF AKD5LGGT700 : ATI DDRIII 800 1Gb 23EY2387MA12-SZ LF+HF w/o sideport: U7 Non-stuff Quanta Computer Inc PROJECT : ZH9 Size Document Number RS880-HT LINK/SPMEM I/F 1/4 Date: Sunday, March 28, 2010 Sheet of 40 Rev 4A TX2_HDMI+_C TX2_HDMI-_C TX1_HDMI+_C TX1_HDMI-_C TX0_HDMI+_C TX0_HDMI-_C TXC_HDMI+_C TXC_HDMI-_C D D C C PCIE_RXP0 PCIE_RXN0 PCIE_RXP1 PCIE_RXN1 PCIE_RXP2 PCIE_RXN2 PCIE_TXP0_C PCIE_TXN0_C PCIE_TXP1_C PCIE_TXN1_C PCIE_TXP2_C PCIE_TXN2_C B B A_TXP0_C A_TXN0_C A_TXP1_C A_TXN1_C A_TXP2_C A_TXN2_C A_TXP3_C A_TXN3_C A_TXP0 A_TXN0 A_TXP1 A_TXN1 A_TXP2 A_TXN2 A_TXP3 A_TXN3 NB_PCIECALRP NB_PCIECALRN A A ... Reserve R266,C315,C316,U15,R276,R410 and stuff R51~R53,R48,Q7~Q9,D2,D3,R411, for AMD SB-TSI L37 3A/30ohm_6 CPU_LDT_RST# CPU_PWRGD CPU_LDT_STOP# W/S= 15 mil/20mil +CPUVDDA +2.5V... +3V R276 CLK_CPU_BCLKP_C CLK_CPU_BCLKN_C ADDRESS: 0x4C(98H) (1001100) CPU_TEST23_TSTUPD PD with 1K and add a test point R330 *300/J_4 +1.1V_CPU_VLDT T58