A B C D E 1 Compal Confidential 2 KALA0 Schematics Document Intel Processor with MCP79 2008-11-25 3 REV:0.4 4 2007/09/14 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2008/04/04 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title SCHEMATIC MB A4681 Size B Date: Document Number Rev B 401627 Sheet Wednesday, December 10, 2008 E of 47 Compal confidential Sub-board Model : KALA0 File Name : LA-4681P LS-4681P- SW/B page 29 Mobile Penryn D Thermal Sensor ADT7421 uFCPGA-478 CPU Fan Control D LS-4682P-USB/B page 33 page 26 page LS-4683P- FP/B page 4-6 HDMI LCD Conn page 21 H_A#(3 35) H_D#(0 63) CRT page 19 FSB page 26 800/1066MHz page 20 DDR3 1333Mhz nVIDIA MCP79 (MX/MH) C USB2.0 page 27 USB connx1 USB port PCI-E BUS Gen2 FCBGA 1437 page 24 page 24 page 26 Card Reader Giga LAN Mini-Card JMB380 Broadcom5764 WLAN Port Port Port page 27 New Card 3.3V 480MHz page 26 page 26 page 26 page 26 Mini2 reserve Finger Printer BT conn USB port USB port USB port USB port USB port SATA2 page 23 page 26 Camera New Card WLAN USB port USB port USB port 11 C page 30 3GHz PE0 Amplifier ALC888 RJ45 1394 Slot page 27 MDC V1.5 page 7-16 HD Audio Codec 5in1 Slot page 19 USB/B connx2 Azalia page 26 Mini-Card Reserve Port DDR3-SO-DIMM X2 page 17,18 Dual Channel page 25 HP Amplifier & Int-Mic LPC BUS APA2051 page 32 page 31 3.3V 33 MHz page 23 Audio Jack Line in MIC HP/SPDIF page 32 B B SATA SATA HDD page 22 RTC BAT ENE KB926 page 35 page 28 SATA Power On/Off CKT SATA ODD page 30 page 22 DC/DC Interface CKT Touch Pad conn page 29 Int.KBD page 29 SPI BIOS page 34,35 page 29 Charger Page 38 Power Circuit DC/DC A A Page 35~44 Compal Secret Data Security Classification Issued Date 2007/10/25 Deciphered Date 2008/10/25 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc SCHEMATIC MB A4681 Size Document Number Rev B 401627 Date: Wednesday, December 10, 2008 Sheet of 47 A B C D SIGNAL STATE Voltage Rails E SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock HIGH HIGH HIGH HIGH ON ON ON ON Power Plane Description S0 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF B+ AC or battery power rail for power circuit N/A N/A N/A +CPU_CORE Core voltage for CPU ON OFF OFF +MCP_CORE Core voltage for MCP79 ON OFF OFF +1.05VS 1.05V switched power rail ON OFF OFF +1.1Valways 1.1Valways switched power rail ON ON ON +1.1VS 1.1Valways switched power rail ON OFF OFF +1.5V 1.5V switched power rail ON ON OFF +1.5VS 1.5V power rail for DDR3 ON OFF OFF Vcc Ra +0.75VS 0.75VS switched power rail ON OFF OFF Board ID +1.8VS 1.8VS switched power rail ON OFF OFF +3VALW 3.3V always on power rail ON ON ON* +3V 3.3V power rail for SB ON ON X +3V_LAN 3.3V power rail for LAN ON ON X +3VS 3.3V switched power rail ON OFF OFF +5VALW 5V always on power rail ON ON ON* +5VS 5V switched power rail ON OFF OFF +VSB VSB always on power rail ON ON ON* +RTCVCC RTC power ON ON ON Full ON S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF Board ID / SKU ID Table for AD channel 3.3V +/- 5% 100K +/- 5% Rb 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF BOARD ID Table Board ID EC SM Bus1 address Address Device Address Smart Battery 0001 011X b BMC1402 1001 100X b Device PCB Revision 0.1 0.2 , 0.3 Default Item V V BOM Structure A01@ mini2@ 385@ 1394@ Amic@ Dmic@ 1.0 EC SM Bus2 address Device MCP79 SM Bus address BTO Option Table MCP79 SM Bus address Address Device Address DDR DIMM0 1010 0000 DDR DIMM1 1010 0010 New card Lan Minicard Minicard 4 2007/09/14 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2007/12/25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title SCHEMATIC MB A4681 Size B Date: Document Number Rev B 401627 Sheet Wednesday, December 10, 2008 E of 47 Place close to CPU within 500mil 56_0402_5% 49.9_0402_1% ITP_PREQ R402 49.9_0402_1% 150_0402_1% 51_0402_1% 1 R379 ITP_TDI R390 ITP_TDO R392 ITP_TMS R391 39_0402_1% H_PROCHOT# R386 68_0402_5% H_BR0# R383 62_0402_5% H_FERR# R377 62_0402_5% H_INTR R378 @ 150_0402_1% H_NMI R376 @ 150_0402_1% H_RESET# R382 @ 200_0402_1% ITP_TCK R398 27_0402_1% ITP_TRST# R397 649_0402_1% H_THERMTRIP# @ Q39 MMBT3904_SOT23 MAINPWON 36,37 C @ @ R375 330_0402_5% @ R380 @ 330_0402_5% E R388 H_THERMTRIP# +1.05VS B D H_IERR# +1.05VS 2 D H_A#[3 35] H_A#[3 35] JCPU1A H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 K3 H2 K2 J3 L1 H_ADSTB#1 H_A20M# H_FERR# H_IGNNE# 7 7 H_STPCLK# H_INTR H_NMI H_SMI# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# H_A20M# H_FERR# H_IGNNE# A6 A5 C4 A20M# FERR# IGNNE# H_STPCLK# H_INTR H_NMI H_SMI# D5 C6 B4 A3 STPCLK# LINT0 LINT1 SMI# M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10] B @ H_ADS# H_BNR# H_BPRI# H5 F21 E1 H_DEFER# H_DRDY# H_DBSY# F1 H_BR0# D20 B3 H_IERR# LOCK# H4 RESET# RS[0]# RS[1]# RS[2]# TRDY# C1 F3 F4 G3 G2 HIT# HITM# G6 E4 BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 H_RESET# XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 ITP_PREQ ITP_TCK ITP_TDI ITP_TDO ITP_TMS ITP_TRST# ITP_DBRESET# H_BR0# 7 7 H_INIT# H_LOCK# H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY# 7 7 H_HIT# H_HITM# 7 XDP Connector JXDP1 ITP_PREQ XDP_BPM#2 XDP_BPM#1 C506 0.1U_0402_16V4Z +1.05VS XDP_BPM2#2 XDP_BPM2#1 CLK_XDP @ 15P_0402_50V8J C540 ITP_DBRESET# ITP_TRST# ITP_TMS 11 13 15 17 19 21 23 25 27 29 11 13 15 17 19 21 23 25 27 29 31 33 GND GND 10 12 14 16 18 20 22 24 26 28 30 10 12 14 16 18 20 22 24 26 28 30 GND GND 32 34 XDP_BPM#4 XDP_BPM#3 XDP_BPM#0 XDP_BPM2#3 C XDP_BPM2#0 H_PWRGOOD_R R400 1K_0402_5% ITP_TCK H_RESET#_R ITP_TDO R396 ITP_TDI XDP_PRE# H_PWRGOOD 5,7 CLK_XDP# H_RESET# 1K_0402_5% @ C541 15P_0402_50V8J @P-TWO_196027-30041 TBD +1.05VS THERMAL PROCHOT# THERMDA THERMDC ICH 7 7 Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 H1 E2 G5 IERR# INIT# BR0# ADDR GROUP H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# DEFER# DRDY# DBSY# CONTROL 7 7 ADS# BNR# BPRI# XDP/ITP SIGNALS H_ADSTB#0 A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# THERMTRIP# D21 A24 B25 H_PROCHOT# H_THERMDA H_THERMDC C7 H_THERMTRIP# QC: ES1: DePOP ALL ES2: POP ALL DC: DEPOP ALL H_PROCHOT# H_THERMTRIP# XDP_BPM2#3 XDP_BPM2#0 R403 XDP_BPM2#1 R405 XDP_BPM2#2 R406 XDP_BPM2#3 R404 @ 51_0402_1% @ 51_0402_1% @ 51_0402_1% @ 51_0402_1% H CLK BCLK[0] BCLK[1] A22 A21 CLK_CPU_BCLK CLK_CPU_BCLK# +1.05VS R395 H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil RESERVED C J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 ADDR GROUP H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 XDP_PRE# 10K_0402_5% B Place close to JITP within 200ps = 1000 mil Merom Ball-out Rev 1a Thermal Sensor SMSC EMC1402(Main) 0.1U_0402_16V4Z +3VS C486 U32 H_THERMDA C487 2H_THERMDC 2200P_0402_50V7K VDD SMCLK DP SMDATA DN ALERT# GND A THERM# EC_SMB_CK2 28 EC_SMB_DA2 28 R374 10K_0402_5% +3VS A EMC1402-1-ACZL-TR_MSOP8 Address:1001_100x ADT7421 Address:1001_101x ADT7421-1 Compal Secret Data Security Classification Issued Date 2007/10/25 Deciphered Date 2008/10/25 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc SCHEMATIC MB A4681 Size Document Number Rev B 401627 Date: Wednesday, December 10, 2008 Sheet of 47 R384 R385 C361 @ 1K_0402_5% @ 1K_0402_5% R381 @ 0.1U_0402_16V4Z +GTL_REF0 TEST1 TEST2 TEST4 @ 0_0402_5% 7 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2 AD26 C23 D25 C24 AF26 AF1 A26 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 B22 B23 C21 BSEL[0] BSEL[1] BSEL[2] @ B CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 166 1 200 266 0 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 MISC H_DSTBN#2 H_DSTBP#2 H_DINV#2 H_D#[48 63] Resistor placed within 0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal COMP[0,2] trace width is 18 mils COMP[1,3] trace width is mils H_DSTBN#3 H_DSTBP#3 H_DINV#3 COMP[0] COMP[1] COMP[2] COMP[3] R26 U26 AA1 Y1 COMP0 COMP1 COMP2 COMP3 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# E5 B5 D24 D6 D7 AE6 H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# H_PSI# H_DPRSTP# 7,44 H_DPSLP# H_DPWR# H_PWRGOOD 4,7 H_CPUSLP# H_PSI# 44 Merom Ball-out Rev 1a H_PWRGOOD R167 @ 150_0402_1% H_CPUSLP# @ 51_0402_1% H_DPRSTP# R149 R150 @ +CPU_CORE JCPU1C R412 +1.05VS 0_0402_5% BR1 220_0402_5% A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067] @ VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 VCCA[01] VCCA[02] B26 C26 VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] AD6 AF5 AE5 AF4 AE3 AF3 AE2 VCCSENSE AF7 VCCSENSE VSSSENSE AE7 VSSSENSE C +1.05VS + C481 330U_D2E_2.5VM_R9 +1.5VS CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 44 44 44 44 44 44 44 2 0.01U_0402_16V7K H_DSTBN#1 H_DSTBP#1 H_DINV#1 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 +CPU_CORE Near pin B26 7 D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# D C489 C D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# DATA GRP Close to CPU pin AD26 within 500mils H_D#16 N22 H_D#17 K25 H_D#18 P26 H_D#19 R23 H_D#20 L23 H_D#21 M24 H_D#22 L22 H_D#23 M23 H_D#24 P25 H_D#25 P23 H_D#26 P22 H_D#27 T24 H_D#28 R24 H_D#29 L25 H_D#30 T25 H_D#31 N25 L26 M26 N24 10U_0805_10V4Z C488 R408 2K_0402_1% Near pin C26 H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[16 31] H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 R393 27.4_0402_1% 2 7 7 +GTL_REF0 Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 R394 54.9_0402_1% R407 1K_0402_1% D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# DATA GRP +1.05VS D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# DATA GRP D H_D#[32 47] JCPU1B H_D#0 E22 H_D#1 F24 H_D#2 E26 H_D#3 G22 H_D#4 F23 H_D#5 G25 H_D#6 E25 H_D#7 E23 H_D#8 K24 H_D#9 G24 H_D#10 J24 H_D#11 J23 H_D#12 H22 H_D#13 F26 H_D#14 K22 H_D#15 H23 J26 H26 H25 R401 27.4_0402_1% H_D#[0 15] DATA GRP R399 54.9_0402_1% B VCCSENSE 44 VSSSENSE 44 Merom Ball-out Rev 1a +CPU_CORE R236 100_0402_1% VCCSENSE R237 100_0402_1% VSSSENSE Close to CPU pin within 500mils A Compal Secret Data Security Classification Issued Date 2007/10/25 2008/10/25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Length match within 25 mils The trace width/space/other is 20/7/25 A Compal Electronics, Inc SCHEMATIC MB A4681 Size Document Number Rev B 401627 Date: Sheet Wednesday, December 10, 2008 of 47 +CPU_CORE Place these capacitors on L8 (North side,Secondary Layer) C321 10U_0805_6.3V6M C320 10U_0805_6.3V6M C330 10U_0805_6.3V6M C341 10U_0805_6.3V6M C342 10U_0805_6.3V6M C324 10U_0805_6.3V6M C325 10U_0805_6.3V6M C331 10U_0805_6.3V6M +CPU_CORE D JCPU1D C Pin F8 Dual Core: GND (internal) Quad Core: Floating (internal) B VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] conn@ VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25 Place these capacitors on L8 (North side,Secondary Layer) C351 10U_0805_6.3V6M C352 10U_0805_6.3V6M C322 10U_0805_6.3V6M C353 10U_0805_6.3V6M C344 10U_0805_6.3V6M C343 10U_0805_6.3V6M C484 10U_0805_6.3V6M C485 10U_0805_6.3V6M +CPU_CORE Place these capacitors on L8 (Sorth side,Secondary Layer) C490 10U_0805_6.3V6M C491 10U_0805_6.3V6M C496 10U_0805_6.3V6M C498 10U_0805_6.3V6M C499 10U_0805_6.3V6M C502 10U_0805_6.3V6M C493 10U_0805_6.3V6M C504 10U_0805_6.3V6M +CPU_CORE Place these capacitors on L8 (Sorth side,Secondary Layer) C494 10U_0805_6.3V6M C495 10U_0805_6.3V6M C497 10U_0805_6.3V6M C500 10U_0805_6.3V6M C501 10U_0805_6.3V6M C505 10U_0805_6.3V6M C492 10U_0805_6.3V6M C503 10U_0805_6.3V6M Mid Frequence Decoupling C +CPU_CORE 330U_D2E_2.5VM_R9 South Side Secondary of CPU Socket C367 1 + C366 330U_D2E_2.5VM_R9 @ C365 + 330U_D2E_2.5VM_R9 + @ C368 + 330U_D2E_2.5VM_R9 C483 330U_D2E_2.5VM_R9 + North Side Secondary of CPU Socket ESR 1980uF + C482 2 330uF ESR 7m ohm X PCS 330U_D2E_2.5VM_R9 B +1.05VS C326 @ Merom Ball-out Rev 1a + 330U_D2E_2.5VM_R9 A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 D C328 0.1U_0402_16V4Z C329 0.1U_0402_16V4Z C340 0.1U_0402_16V4Z C332 0.1U_0402_16V4Z C333 0.1U_0402_16V4Z C345 0.1U_0402_16V4Z Place these inside socket cavity on Bottom layer (North side Secondary) Pin D8,AA8,AC8 and AE8 Reserved for QC A A Compal Secret Data Security Classification Issued Date 2007/10/25 2008/10/25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc SCHEMATIC MB A4681 Size Document Number Rev B 401627 Date: Sheet Wednesday, December 10, 2008 of 47 D H_D#[0 63] U30A 5 H_DSTBP#0 H_DSTBN#0 H_DINV#0 T40 U40 V41 CPU_DSTBP0# CPU_DSTBN0# CPU_DBI0# 5 H_DSTBP#1 H_DSTBN#1 H_DINV#1 W39 W37 V35 CPU_DSTBP1# CPU_DSTBN1# CPU_DBI1# 5 H_DSTBP#2 H_DSTBN#2 H_DINV#2 N37 L36 N35 CPU_DSTBP2# CPU_DSTBN2# CPU_DBI2# 5 H_DSTBP#3 H_DSTBN#3 H_DINV#3 M39 M41 J41 CPU_DSTBP3# CPU_DSTBN3# CPU_DBI3# H_A#[3 35] H_A#[3 35] C 1K_0402_5% R365 @ 4 R472 @ 1K_0402_5% R471 @ 1 R470 @ 1K_0402_5% CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 1K_0402_5% 5 R367 @ 1K_0402_5% R366 @ 1K_0402_5% +1.05VS H_ADSTB#0 H_ADSTB#1 H_REQ#[0 4] 4 4 4 4 B H_ADS# H_BNR# H_BR0# H_DBSY# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# H_PROCHOT# H_THERMTRIP# H_FERR# +1.1VS 4 C196 1U_0402_6.3V4Z AC34 AE38 AE34 AC37 AE37 AE35 AB35 AF35 AG35 AG39 AE33 AG37 AG38 AG34 AN38 AL39 AG33 AL33 AJ33 AN36 AJ35 AJ37 AJ36 AJ38 AL37 AL34 AN37 AJ34 AL38 AL35 AN34 AR39 AN35 CPU_A3# CPU_A4# CPU_A5# CPU_A6# CPU_A7# CPU_A8# CPU_A9# CPU_A10# CPU_A11# CPU_A12# CPU_A13# CPU_A14# CPU_A15# CPU_A16# CPU_A17# CPU_A18# CPU_A19# CPU_A20# CPU_A21# CPU_A22# CPU_A23# CPU_A24# CPU_A25# CPU_A26# CPU_A27# CPU_A28# CPU_A29# CPU_A30# CPU_A31# CPU_A32# CPU_A33# CPU_A34# CPU_A35# AE36 AK35 CPU_ADSTB0# CPU_ADSTB1# H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 AC38 AA33 AC39 AC33 AC35 CPU_REQ0# CPU_REQ1# CPU_REQ2# CPU_REQ3# CPU_REQ4# H_ADS# H_BNR# H_BR0# H_DBSY# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# AD42 AD43 AE40 AD39 AD41 AB42 AD40 AC43 AE41 CPU_ADS# CPU_BNR# CPU_BR0# CPU_DBSY# CPU_DRDY# CPU_HIT# CPU_HITM# CPU_LOCK# CPU_TRDY# T3 PAD H_PROCHOT# H_THERMTRIP# H_FERR# E41 AJ41 AG43 AH40 CPU_PECI CPU_PROCHOT# CPU_THERMTRIP# CPU_FERR# CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 L9 MBK1608121YZF_0603 +V_PLL_CPU H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 49 mA H_RS#0 H_RS#1 H_RS#2 F42 D42 F41 H_RS#0 H_RS#1 H_RS#2 +V_PLL_CPU +1.1VS_V_VPLL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 AC41 AB41 AC42 CPU_RS0# CPU_RS1# CPU_RS2# AH28 U28 +V_PLL_CPU +V_PLL_DP +1.05VS R373 R369 2 149.9_0402_1% BCLK_VML_COMP_VCC 149.9_0402_1% BCLK_VML_COMP_GND AM39 AM40 BCLK_VML_COMP_VDD BCLK_VML_COMP_GND R372 R371 1 249.9_0402_1% 249.9_0402_1% AM43 AM42 CPU_COMP_VCC CPU_COMP_GND CPU_COMP_VCC CPU_COMP_GND A FSB CPU_D0# CPU_D1# CPU_D2# CPU_D3# CPU_D4# CPU_D5# CPU_D6# CPU_D7# CPU_D8# CPU_D9# CPU_D10# CPU_D11# CPU_D12# CPU_D13# CPU_D14# CPU_D15# CPU_D16# CPU_D17# CPU_D18# CPU_D19# CPU_D20# CPU_D21# CPU_D22# CPU_D23# CPU_D24# CPU_D25# CPU_D26# CPU_D27# CPU_D28# CPU_D29# CPU_D30# CPU_D31# CPU_D32# CPU_D33# CPU_D34# CPU_D35# CPU_D36# CPU_D37# CPU_D38# CPU_D39# CPU_D40# CPU_D41# CPU_D42# CPU_D43# CPU_D44# CPU_D45# CPU_D46# CPU_D47# CPU_D48# CPU_D49# CPU_D50# CPU_D51# CPU_D52# CPU_D53# CPU_D54# CPU_D55# CPU_D56# CPU_D57# CPU_D58# CPU_D59# CPU_D60# CPU_D61# CPU_D62# CPU_D63# Y43 W42 Y40 W41 Y39 V42 Y41 Y42 P42 U41 R42 T39 T42 T41 R41 T43 W35 AA37 W33 W34 AA36 AA34 AA38 AA35 U38 U36 U35 U33 U34 W38 R33 U37 N34 N33 R34 R35 P35 R39 R37 R38 L37 L39 L38 N36 N38 J39 J38 J37 L42 M42 P41 N41 N40 M40 H40 K42 H41 L41 H43 H42 K41 J40 H39 M43 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 CPU_BPRI# CPU_DEFER# AA41 AA40 H_BPRI# H_DEFER# BCLK_OUT_CPU_P BCLK_OUT_CPU_N G42 G41 BCLK_OUT_ITP_P BCLK_OUT_ITP_N AL43 AL42 BCLK_OUT_NB_P BCLK_OUT_NB_N AL41 AK42 H_D#[0 63] D C @ H_BPRI# H_DEFER# B C480 15P_0402_50V8J CLK_CPU_BCLK CLK_CPU_BCLK# CLK_XDP CLK_XDP# BCLK_FEEDBACK_P BCLK_FEEDBACK_N @ BCLK_IN_N BCLK_IN_P AK41 AJ40 CPU_A20M# CPU_IGNNE# CPU_INIT# CPU_INTR CPU_NMI CPU_SMI# AF41 AH39 AH42 AF42 AG41 AH41 H_A20M# H_IGNNE# H_INIT# H_INTR H_NMI H_SMI# H_A20M# H_IGNNE# H_INIT# H_INTR H_NMI H_SMI# CPU_PWRGD CPU_RESET# AH43 H38 H_PWRGOOD H_RESET# H_PWRGOOD 4,5 H_RESET# CPU_SLP# CPU_DPSLP# CPU_DPWR# CPU_STPCLK# CPU_DPRSTP# AM33 AN33 AM32 AG42 AN32 H_CPUSLP# H_DPSLP# H_DPWR# H_STPCLK# H_DPRSTP# CLK_CPU_BCLK CLK_CPU_BCLK# C479 15P_0402_50V8J H_CPUSLP# H_DPSLP# H_DPWR# H_STPCLK# H_DPRSTP# 5,44 A MCP79-SLI_PBGA1437 Compal Secret Data Security Classification Issued Date 2007/10/25 2008/10/25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc SCHEMATIC MB A4681 Size Document Number Rev B 401627 Date: Sheet Wednesday, December 10, 2008 of 47 DDR_B_DQS#[0 7] DDR_B_DQS#[0 7] DDR_B_DQS[0 7] D DDR_B_DQS[0 7] 18 18 D U30C 18 DDR_B_D[0 63] DDR_A_DQS[0 7] DDR_A_DQS#[0 7] DDR_A_DQS[0 7] DDR_B_D63 DDR_B_D62 DDR_B_D61 DDR_B_D60 DDR_B_D59 DDR_B_D58 DDR_B_D57 DDR_B_D56 DDR_B_D55 DDR_B_D54 DDR_B_D53 DDR_B_D52 DDR_B_D51 DDR_B_D50 DDR_B_D49 DDR_B_D48 DDR_B_D47 DDR_B_D46 DDR_B_D45 DDR_B_D44 DDR_B_D43 DDR_B_D42 DDR_B_D41 DDR_B_D40 DDR_B_D39 DDR_B_D38 DDR_B_D37 DDR_B_D36 DDR_B_D35 DDR_B_D34 DDR_B_D33 DDR_B_D32 DDR_B_D31 DDR_B_D30 DDR_B_D29 DDR_B_D28 DDR_B_D27 DDR_B_D26 DDR_B_D25 DDR_B_D24 DDR_B_D23 DDR_B_D22 DDR_B_D21 DDR_B_D20 DDR_B_D19 DDR_B_D18 DDR_B_D17 DDR_B_D16 DDR_B_D15 DDR_B_D14 DDR_B_D13 DDR_B_D12 DDR_B_D11 DDR_B_D10 DDR_B_D9 DDR_B_D8 DDR_B_D7 DDR_B_D6 DDR_B_D5 DDR_B_D4 DDR_B_D3 DDR_B_D2 DDR_B_D1 DDR_B_D0 17 17 U30B 17 DDR_A_D[0 63] B AL8 AL9 AP9 AN9 AL6 AL7 AN6 AN7 AR6 AR7 AV6 AW5 AN10 AR5 AU6 AV5 AU7 AU8 AW9 AP11 AW6 AY5 AU9 AV9 AU11 AV11 AV13 AW13 AR11 AT11 AR14 AU13 AR26 AU25 AT27 AU27 AP25 AR25 AP27 AR27 AP29 AR29 AP31 AR31 AV27 AN29 AV29 AN31 AU31 AR33 AV37 AW37 AT31 AV31 AT37 AU37 AW39 AV39 AR37 AR38 AV38 AW38 AR35 AP35 MDQ0_63 MDQ0_62 MDQ0_61 MDQ0_60 MDQ0_59 MDQ0_58 MDQ0_57 MDQ0_56 MDQ0_55 MDQ0_54 MDQ0_53 MDQ0_52 MDQ0_51 MDQ0_50 MDQ0_49 MDQ0_48 MDQ0_47 MDQ0_46 MDQ0_45 MDQ0_44 MDQ0_43 MDQ0_42 MDQ0_41 MDQ0_40 MDQ0_39 MDQ0_38 MDQ0_37 MDQ0_36 MDQ0_35 MDQ0_34 MDQ0_33 MDQ0_32 MDQ0_31 MDQ0_30 MDQ0_29 MDQ0_28 MDQ0_27 MDQ0_26 MDQ0_25 MDQ0_24 MDQ0_23 MDQ0_22 MDQ0_21 MDQ0_20 MDQ0_19 MDQ0_18 MDQ0_17 MDQ0_16 MDQ0_15 MDQ0_14 MDQ0_13 MDQ0_12 MDQ0_11 MDQ0_10 MDQ0_9 MDQ0_8 MDQ0_7 MDQ0_6 MDQ0_5 MDQ0_4 MDQ0_3 MDQ0_2 MDQ0_1 MDQ0_0 DDR_A_DM7 DDR_A_DM6 DDR_A_DM5 DDR_A_DM4 DDR_A_DM3 DDR_A_DM2 DDR_A_DM1 DDR_A_DM0 AN5 AU5 AR10 AN13 AN27 AW29 AV35 AR34 MDQM0_7 MDQM0_6 MDQM0_5 MDQM0_4 MDQM0_3 MDQM0_2 MDQM0_1 MDQM0_0 17 DDR_A_DM[0 7] A MDQS0_7_P MDQS0_7_N MDQS0_6_P MDQS0_6_N MDQS0_5_P MDQS0_5_N MDQS0_4_P MDQS0_4_N MDQS0_3_P MDQS0_3_N MDQS0_2_P MDQS0_2_N MDQS0_1_P MDQS0_1_N MDQS0_0_P MDQS0_0_N AL10 AL11 AR8 AR9 AW7 AW8 AP13 AR13 AV25 AW25 AU30 AU29 AT35 AU35 AU39 AT39 DDR_A_DQS7 DDR_A_DQS#7 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS0 DDR_A_DQS#0 MEMORY PARTITION MRAS0# MCAS0# MWE0# AV17 AP17 AR17 DDR_A_RAS# DDR_A_CAS# DDR_A_WE# MBA0_2 MBA0_1 MBA0_0 AP23 AP19 AW17 DDR_A_BS2 DDR_A_BS1 DDR_A_BS0 MA0_14 MA0_13 MA0_12 MA0_11 MA0_10 MA0_9 MA0_8 MA0_7 MA0_6 MA0_5 MA0_4 MA0_3 MA0_2 MA0_1 MA0_0 AR23 AU15 AN23 AW21 AN19 AV21 AR22 AU21 AP21 AR21 AN21 AV19 AU19 AT19 AR19 DDR_A_MA14 DDR_A_MA13 DDR_A_MA12 DDR_A_MA11 DDR_A_MA10 DDR_A_MA9 DDR_A_MA8 DDR_A_MA7 DDR_A_MA6 DDR_A_MA5 DDR_A_MA4 DDR_A_MA3 DDR_A_MA2 DDR_A_MA1 DDR_A_MA0 DDR_A_RAS# 17 DDR_A_CAS# 17 DDR_A_WE# 17 DDR_A_BS[0 2] 17 DDR_A_MA[0 14] 17 MDQ1_63 MDQ1_62 MDQ1_61 MDQ1_60 MDQ1_59 MDQ1_58 MDQ1_57 MDQ1_56 MDQ1_55 MDQ1_54 MDQ1_53 MDQ1_52 MDQ1_51 MDQ1_50 MDQ1_49 MDQ1_48 MDQ1_47 MDQ1_46 MDQ1_45 MDQ1_44 MDQ1_43 MDQ1_42 MDQ1_41 MDQ1_40 MDQ1_39 MDQ1_38 MDQ1_37 MDQ1_36 MDQ1_35 MDQ1_34 MDQ1_33 MDQ1_32 MDQ1_31 MDQ1_30 MDQ1_29 MDQ1_28 MDQ1_27 MDQ1_26 MDQ1_25 MDQ1_24 MDQ1_23 MDQ1_22 MDQ1_21 MDQ1_20 MDQ1_19 MDQ1_18 MDQ1_17 MDQ1_16 MDQ1_15 MDQ1_14 MDQ1_13 MDQ1_12 MDQ1_11 MDQ1_10 MDQ1_9 MDQ1_8 MDQ1_7 MDQ1_6 MDQ1_5 MDQ1_4 MDQ1_3 MDQ1_2 MDQ1_1 MDQ1_0 AT5 BA2 AY7 BA11 BB34 BB38 AY43 AR42 MDQM1_7 MDQM1_6 MDQM1_5 MDQM1_4 MDQM1_3 MDQM1_2 MDQM1_1 MDQM1_0 18 DDR_B_DM[0 7] MEMORY CONTROL 0A C DDR_A_D63 DDR_A_D62 DDR_A_D61 DDR_A_D60 DDR_A_D59 DDR_A_D58 DDR_A_D57 DDR_A_D56 DDR_A_D55 DDR_A_D54 DDR_A_D53 DDR_A_D52 DDR_A_D51 DDR_A_D50 DDR_A_D49 DDR_A_D48 DDR_A_D47 DDR_A_D46 DDR_A_D45 DDR_A_D44 DDR_A_D43 DDR_A_D42 DDR_A_D41 DDR_A_D40 DDR_A_D39 DDR_A_D38 DDR_A_D37 DDR_A_D36 DDR_A_D35 DDR_A_D34 DDR_A_D33 DDR_A_D32 DDR_A_D31 DDR_A_D30 DDR_A_D29 DDR_A_D28 DDR_A_D27 DDR_A_D26 DDR_A_D25 DDR_A_D24 DDR_A_D23 DDR_A_D22 DDR_A_D21 DDR_A_D20 DDR_A_D19 DDR_A_D18 DDR_A_D17 DDR_A_D16 DDR_A_D15 DDR_A_D14 DDR_A_D13 DDR_A_D12 DDR_A_D11 DDR_A_D10 DDR_A_D9 DDR_A_D8 DDR_A_D7 DDR_A_D6 DDR_A_D5 DDR_A_D4 DDR_A_D3 DDR_A_D2 DDR_A_D1 DDR_A_D0 AT4 AT3 AV2 AV3 AR4 AR3 AU2 AU3 AY4 AY3 BB3 BC3 AW4 AW3 BA3 BB2 BB5 BA5 BA8 BC8 BB4 BC4 BA7 AY8 BA9 BB10 BB12 AW12 BB8 BB9 AY12 BA12 BC32 AW32 BA35 AY36 BA32 BB32 BA34 AY35 BC36 AW36 BA39 AY40 BA36 BB36 BA38 AY39 BB40 AW40 AV42 AV41 BA40 BC40 AW42 AW41 AT40 AT41 AP41 AN40 AU40 AU41 AR41 AP42 MCLK0A_2_P MCLK0A_2_N AW33 AV33 MCLK0A_1_P MCLK0A_1_N BA24 AY24 M_CLK_DDR1 M_CLK_DDR#1 MCLK0A_0_P MCLK0A_0_N BB20 BC20 M_CLK_DDR0 M_CLK_DDR#0 MCS0A_1# MCS0A_0# AT15 AR18 DDR_CS1_DIMMA# DDR_CS0_DIMMA# MODT0A_1 MODT0A_0 AP15 AV15 M_ODT1 M_ODT0 MCKE0A_1 MCKE0A_0 AU23 AT23 DDR_CKE1_DIMMA DDR_CKE0_DIMMA DDR_B_DM7 DDR_B_DM6 DDR_B_DM5 DDR_B_DM4 DDR_B_DM3 DDR_B_DM2 DDR_B_DM1 DDR_B_DM0 M_CLK_DDR1 17 M_CLK_DDR#1 17 M_CLK_DDR0 17 M_CLK_DDR#0 17 DDR_B_DQS7 DDR_B_DQS#7 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS0 DDR_B_DQS#0 MDQS1_7_P MDQS1_7_N MDQS1_6_P MDQS1_6_N MDQS1_5_P MDQS1_5_N MDQS1_4_P MDQS1_4_N MDQS1_3_P MDQS1_3_N MDQS1_2_P MDQS1_2_N MDQS1_1_P MDQS1_1_N MDQS1_0_P MDQS1_0_N AT2 AT1 AY2 AY1 BB6 BA6 BA10 AY11 BB33 BA33 BB37 BA37 BA43 AY42 AT42 AT43 MRAS1# MCAS1# MWE1# AW16 BA15 BA16 DDR_B_RAS# DDR_B_CAS# DDR_B_WE# MBA1_2 MBA1_1 MBA1_0 BB29 BB18 BB17 DDR_B_BS2 DDR_B_BS1 DDR_B_BS0 MA1_14 MA1_13 MA1_12 MA1_11 MA1_10 MA1_9 MA1_8 MA1_7 MA1_6 MA1_5 MA1_4 MA1_3 MA1_2 MA1_1 MA1_0 BA29 BA14 AW28 BC28 BA17 BB28 AY28 BA28 AY27 BA27 BA26 BB26 BA25 BB25 BA18 DDR_B_MA14 DDR_B_MA13 DDR_B_MA12 DDR_B_MA11 DDR_B_MA10 DDR_B_MA9 DDR_B_MA8 DDR_B_MA7 DDR_B_MA6 DDR_B_MA5 DDR_B_MA4 DDR_B_MA3 DDR_B_MA2 DDR_B_MA1 DDR_B_MA0 MCLK1A_2_P MCLK1A_2_N BA42 BB42 MCLK1A_1_P MCLK1A_1_N BB22 BA22 M_CLK_DDR3 M_CLK_DDR#3 MCLK1A_0_P MCLK1A_0_N BA19 AY19 M_CLK_DDR2 M_CLK_DDR#2 MCS1A_1# MCS1A_0# BB14 BB16 DDR_CS3_DIMMB# DDR_CS2_DIMMB# MODT1A_1 MODT1A_0 BB13 AY15 M_ODT3 M_ODT2 MCKE1A_1 MCKE1A_0 AY31 BB30 DDR_CKE3_DIMMB DDR_CKE2_DIMMB MEMORY PARTITION DDR_B_RAS# 18 DDR_B_CAS# 18 DDR_B_WE# 18 DDR_B_BS[0 2] 18 C DDR_B_MA[0 14] MEMORY CONTROL 1A DDR_A_DQS#[0 7] 18 M_CLK_DDR3 18 M_CLK_DDR#3 18 B M_CLK_DDR2 18 M_CLK_DDR#2 18 DDR_CS3_DIMMB# 18 DDR_CS2_DIMMB# 18 M_ODT3 18 M_ODT2 18 DDR_CKE3_DIMMB 18 DDR_CKE2_DIMMB 18 MCP79-SLI_PBGA1437 DDR_CS1_DIMMA# 17 DDR_CS0_DIMMA# 17 M_ODT1 17 M_ODT0 17 DDR_CKE1_DIMMA 17 DDR_CKE0_DIMMA 17 A MCP79-SLI_PBGA1437 Compal Secret Data Security Classification Issued Date 2007/10/25 2008/10/25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc SCHEMATIC MB A4681 Size Document Number Rev B 401627 Date: Sheet Wednesday, December 10, 2008 of 47 U30D D D MCLK1B_0_P MCLK1B_0_N BA20 AY20 AU17 AR15 MCS0B_0# MCS0B_1# MCS1B_0# MCS1B_1# BC16 BA13 AN17 AN15 MODT0B_0 MODT0B_1 MODT1B_0 MODT1B_1 AY16 BC13 AV23 AN25 MCKE0B_0 MCKE0B_1 MCKE1B_0 MCKE1B_1 BA30 BA31 +V_PLL_MCLK +V_DLL_DLCELL_AVDD +V_PLL_FSB AH27 AG27 AG28 MRESET0# AY32 MEM_COMP_GND GND55 GND56 GND57 GND58 GND59 GND60 GND61 GND62 GND63 GND64 C +1.5V 4.77 A C200 C137 C154 C134 C136 0.1U_0402_16V7K C181 +1.5V B C178 C135 C179 C199 C153 C180 0.1U_0402_16V7K AM17 AM19 AM21 AM23 AM25 AM27 AM29 AN16 BC29 AN20 AN24 AT17 AP16 AN22 AP20 AP24 AV16 AR16 AR20 AR24 AW15 AP22 AP18 AU16 AN18 AU24 AT21 AY29 AV24 AU20 AU22 AW27 BC17 AV20 AY17 AY18 AM15 AU18 AY25 AY26 AW19 AW24 BC25 AL30 AM31 0.1U_0402_16V7K +VDD_MEM1 +VDD_MEM2 +VDD_MEM3 +VDD_MEM4 +VDD_MEM5 +VDD_MEM6 +VDD_MEM7 +VDD_MEM8 +VDD_MEM9 +VDD_MEM10 +VDD_MEM11 +VDD_MEM12 +VDD_MEM13 +VDD_MEM14 +VDD_MEM15 +VDD_MEM16 +VDD_MEM17 +VDD_MEM18 +VDD_MEM19 +VDD_MEM20 +VDD_MEM21 +VDD_MEM22 +VDD_MEM23 +VDD_MEM24 +VDD_MEM25 +VDD_MEM26 +VDD_MEM27 +VDD_MEM28 +VDD_MEM29 +VDD_MEM30 +VDD_MEM31 +VDD_MEM32 +VDD_MEM33 +VDD_MEM34 +VDD_MEM35 +VDD_MEM36 +VDD_MEM37 +VDD_MEM38 +VDD_MEM39 +VDD_MEM40 +VDD_MEM41 +VDD_MEM42 +VDD_MEM43 +VDD_MEM44 +VDD_MEM45 0.1U_0402_16V7K GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31 GND32 GND33 GND34 GND35 GND36 GND37 GND38 GND39 GND40 GND41 GND42 GND43 GND44 GND45 GND46 GND47 GND48 GND49 GND50 GND51 GND52 GND53 GND54 0.1U_0402_16V7K B MEM_COMP_GND AA22 AP12 G30 P10 T10 T6 V10 V34 W5 AA39 AB22 AB7 AD22 AE20 AF24 AG24 AH35 AK7 AM28 AT25 AP30 AR36 AU10 F28 BC21 AY9 BC9 D34 F24 G32 H31 K7 M38 M5 M6 M7 M9 N39 N8 P33 P34 P37 P4 P40 P7 R36 R40 R43 R5 T18 T20 AK11 T24 T26 0.1U_0402_16V7K R368 40.2_0402_1% AM41 4.7U_0603_6.3V6K 8mil MEM_COMP_VDD C197 C60 +1.5V 0.1U_0402_16V7K MEM_COMP_VDD AN41 SM_DRAMRST# 17,18 0_0402_5% 4.7U_0603_6.3V6K 8mil R151 0.1U_0402_16V7K C +V_PLL_CPU 197 mA 10U_0805_10V4Z R370 40.2_0402_1% 4.7U_0603_6.3V6K MCLK0B_0_P MCLK0B_0_N 0.1U_0402_16V7K AY23 BA23 BA21 BB21 C198 0.1U_0402_16V7K BA41 BB41 MCLK1B_1_P MCLK1B_1_N MEMORY CONTROL 1B MCLK1B_2_P MCLK1B_2_N MCLK0B_1_P MCLK0B_1_N MEMORY CONTROL 0B MCLK0B_2_P MCLK0B_2_N BB24 BC24 0.1U_0402_16V7K +1.5V AU33 AU34 T33 T34 T35 T37 T38 T7 T9 U18 U20 U22 MCP79-SLI_PBGA1437 A A Compal Secret Data Security Classification Issued Date 2007/10/25 2008/10/25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc SCHEMATIC MB A4681 Size Document Number Rev B 401627 Date: Sheet Wednesday, December 10, 2008 of 47 D @ R56 2@ 0_0402_5% C @ R313 +3VS 10K_0402_5% 26 MINI2_CLKREQ# @ R60 +3V_SB 26 MINI1_CLKREQ# 10K_0402_5% R82 0_0402_5% R64 0_0402_5% R318 @ R45 +3VS 27 EXP_CLKREQ# 27 CP_PE# +3V_SB 24,26,27,28 PCIE_WAKE# 0_0402_5% 10K_0402_5% R78 A01@ 10K_0402_5% 23 PCIE_PTX_C_IRX_P0 23 PCIE_PTX_C_IRX_N0 24 PCIE_PTX_C_IRX_P1 24 PCIE_PTX_C_IRX_N1 +1.1VS B 26 PCIE_PTX_C_IRX_P2 26 PCIE_PTX_C_IRX_N2 R29 27 PCIE_PTX_C_IRX_P3 27 PCIE_PTX_C_IRX_N3 C125 C126 +1.1VS L7 MBK1608121YZF_0603 PE0_PRSNT_16# PE0_REFCLK_P PE0_REFCLK_N E11 D11 PEB_CLKREQ/GPIO_49# PEB_PRSNT# PE1_REFCLK_P PE1_REFCLK_N G11 F11 CLK_PCIE_READER 23 CLK_PCIE_READER# 23 E8 C10 PEC_CLKREQ/GPIO_50# PEC_PRSNT# PE2_REFCLK_P PE2_REFCLK_N J11 J10 CLK_PCIE_LAN 24 CLK_PCIE_LAN# 24 LAN M15 B10 PED_CLKREQ/GPIO_51# PED_PRSNT# PE3_REFCLK_P PE3_REFCLK_N G13 F13 CLK_PCIE_MINI1 26 CLK_PCIE_MINI1# 26 MINI_CARD(WLAN) L16 L18 PEE_CLKREQ/GPIO_16# PEE_PRSNT/GPIO_46# PE4_REFCLK_P PE4_REFCLK_N J13 H13 CLK_PCIE_CARD 27 CLK_PCIE_CARD# 27 NEW CARD M16 M18 PEF_CLKREQ/GPIO_17# PEF_PRSNT/GPIO_47# PE5_REFCLK_P PE5_REFCLK_N L14 K14 M17 M19 PEG_CLKREQ/GPIO_18# PEG_PRSNT/GPIO_48# PE6_REFCLK_P PE6_REFCLK_N N14 M14 F17 PE_WAKE# PEX_RST0# K11 K9 J9 PE1_RX0_P PE1_RX0_N PE1_TX0_P PE1_TX0_N D8 C8 PCIE_TX0_P PCIE_TX0_N C296 PCIE_TX1_P PCIE_TX1_N C46 PE1_RX1_P PE1_RX1_N PE1_TX1_P PE1_TX1_N B8 A8 F9 E9 PE1_RX2_P PE1_RX2_N PE1_TX2_P PE1_TX2_N A7 B7 PCIE_TX2_P PCIE_TX2_N C386 H7 G7 PE1_RX3_P PE1_RX3_N PE1_TX3_P PE1_TX3_N B6 C6 PCIE_TX3_P PCIE_TX3_N C392 newcard@ T17 W19 U17 V19 W16 W17 W18 U16 +DVDD0_PEX1 +DVDD0_PEX2 +DVDD0_PEX3 +DVDD0_PEX4 +DVDD0_PEX5 +DVDD0_PEX6 +DVDD0_PEX7 +DVDD0_PEX8 T19 U19 +DVDD1_PEX1 +DVDD1_PEX2 T16 +V_PLL_PEX @ +AVDD0_PEX1 +AVDD0_PEX2 +AVDD0_PEX3 +AVDD0_PEX4 +AVDD0_PEX5 +AVDD0_PEX6 +AVDD0_PEX7 +AVDD0_PEX8 +AVDD0_PEX9 +AVDD0_PEX10 +AVDD0_PEX11 +AVDD0_PEX12 +AVDD0_PEX13 Y12 AA12 AB12 M12 P12 R12 N12 T12 U12 AC12 AD12 V12 W12 +AVDD1_PEX1 +AVDD1_PEX2 +AVDD1_PEX3 M13 N13 P13 A01@ 10K_0402_5% R314 C297 0.1U_0402_16V7K 0.1U_0402_16V7K C47 0.1U_0402_16V7K 0.1U_0402_16V7K C389 0.1U_0402_16V7K 0.1U_0402_16V7K C393 newcard@ 0.1U_0402_16V7K 0.1U_0402_16V7K 2 C122 C92 C94 C91 LAN B PCIE_ITX_C_PRX_P2 26 PCIE_ITX_C_PRX_N2 26 MINI_CARD(WLAN) PCIE_ITX_C_PRX_P3 27 PCIE_ITX_C_PRX_N3 27 NEW CARD L6 C57 2 +1.1VS KC FBM-L11-201209-221LMAT_0805 10U_0805_10V4Z PEX_CLK_COMP 2.37K_0402_1% A Issued Date Compal Secret Data 2007/10/25 2008/10/25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Card Reader PCIE_ITX_C_PRX_P1 24 PCIE_ITX_C_PRX_N1 24 1.3A +AVDD_PEX C93 PCIE_ITX_C_PRX_P0 23 PCIE_ITX_C_PRX_N0 23 MCP79-SLI_PBGA1437 Security Classification +3V_SB C123 2.2U_0402_6.3VM R59 TV Card Reader MCP_PCIE_RST# H9 G9 A11 CLK_PCIE_MINI2 26 CLK_PCIE_MINI2# 26 2 A C58 1U_0402_6.3V4Z C145 4.7U_0603_6.3V6K +V_PLL_PEX C D5 D9 161 mA C124 1U_0402_6.3V4Z C128 +DVDD_PEX 1U_0402_6.3V4Z 0.1U_0402_16V7K C56 0.1U_0402_16V7K 4.7U_0603_6.3V6K 430 mA PE0_ITX_C_PRX_P0 26 PE0_ITX_C_PRX_N0 26 C9 0_0805_5% PCIE 0.1U_0402_16V7K 0.1U_0402_16V7K 4.7U_0603_6.3V6K PCIE_RST# 23,24,26,27 NC7SZ08P5X_NL_SC70-5 C88 C379 1U_0402_6.3V4Z PE0_TX0_P PE0_TX0_N PE0_TX1_P PE0_TX1_N PE0_TX2_P PE0_TX2_N PE0_TX3_P PE0_TX3_N PE0_TX4_P PE0_TX4_N PE0_TX5_P PE0_TX5_N PE0_TX6_P PE0_TX6_N PE0_TX7_P PE0_TX7_N PE0_TX8_P PE0_TX8_N PE0_TX9_P PE0_TX9_N PE0_TX10_P PE0_TX10_N PE0_TX11_P PE0_TX11_N PE0_TX12_P PE0_TX12_N PE0_TX13_P PE0_TX13_N PE0_TX14_P PE0_TX14_N PE0_TX15_P PE0_TX15_N PE0_TX0_P PE0_TX0_N C378 1U_0402_6.3V4Z G Y PE0_RX0_P PE0_RX0_N PE0_RX1_P PE0_RX1_N PE0_RX2_P PE0_RX2_N PE0_RX3_P PE0_RX3_N PE0_RX4_P PE0_RX4_N PE0_RX5_P PE0_RX5_N PE0_RX6_P PE0_RX6_N PE0_RX7_P PE0_RX7_N PE0_RX8_P PE0_RX8_N PE0_RX9_P PE0_RX9_N PE0_RX10_P PE0_RX10_N PE0_RX11_P PE0_RX11_N PE0_RX12_P PE0_RX12_N PE0_RX13_P PE0_RX13_N PE0_RX14_P PE0_RX14_N PE0_RX15_P PE0_RX15_N C5 D4 C4 B4 A4 A3 B3 B2 C1 D1 D2 E1 E2 F2 F3 F4 G3 H4 H3 H2 H1 J1 J2 J3 K2 K3 L4 L3 M4 M3 M2 M1 0.1U_0402_16V7K A 26 PE0_PTX_C_IRX_P0 26 PE0_PTX_C_IRX_N0 U8 0.1U_0402_16V7K B F7 E7 D7 C7 E6 F6 E5 F5 E4 E3 C3 D3 G5 H5 J7 J6 J5 J4 L11 L10 L9 L8 L7 L6 N11 N10 N9 P9 N7 N6 N5 N4 P 0.1U_0402_16V4Z 0.1U_0402_16V7K C89 MCP_PCIE_RST# U30E +3V_SB D Title Compal Electronics, Inc SCHEMATIC MB A4681 Size Document Number Rev B 401627 Date: Sheet Wednesday, December 10, 2008 10 of 47 ...5 Compal confidential Sub-board Model : KALA0 File Name : LA- 4681P LS -4681P- SW/B page 29 Mobile Penryn D Thermal Sensor ADT7421 uFCPGA-478... DIMM0 1010 0000 DDR DIMM1 1010 0010 New card Lan Minicard Minicard 4 2007/09/14 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2007/12/25 Deciphered Date THIS... 20/7/25 A Compal Electronics, Inc SCHEMATIC MB A4681 Size Document Number Rev B 401627 Date: Sheet Wednesday, December 10, 2008 of 47 +CPU_CORE Place these capacitors on L8 (North side,Secondary Layer)