Acer aspire 3500 (compal LA 2362)

5 D m o c e u l b p o t p a l w W w D C C Sonoma Dothan EAL50_1 LA2362 Schematic B B A A Compal Secret Data Security Classification 2005/03/01 Issued Date Deciphered Date 2006/03/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom LA-2362 Date: Friday, March 11, 2005 Rev Sheet 1 of 52 Compal confidential m o c e u l b p o t p a l w W w Block Diagram Dothan D Clock Generator uFCPGA CPU HA#(3 31) System Bus ICS HD#(0 63) 400 / 533MHz CRT CONN & TV-OUT VGA Board ATI VGA VGA CONN PCI-E 16X Memory BUS(DDR) Dual Channel 2.5V 333MHz Alviso Intel 915 PM/GM GMCH-M Internal GM 1257 FC-BGA Fan Control X1 SO-DIMM X SO-DIMM X BANK 0, LED/B BANK 2, Channel A SW LED BD External PM C D C T/P DMI 1.5V 100MHz MINI PCI PCI BUS 3.3V 33MHz 3.3V 33MHz CardBus Controller VIA6301 1394 AC-LINK 3.3V 24.576MHz ICH6 IDSEL:AD17 (PIRQA/B#,GNT#2,REQ#2) DC IN BT+MDC BATT IN/+2.5V 609 BGA RTL 8110SBL / G 8100CL / 100 AC97 CODEC RTL 250 ATA100 1.5V/1.05V(+VCCP) ENE CB712 B 1394 CONN SDIO CONN Slot B HDD Transformer & RJ45 CDROM 3.3V 33MHz USBPORT 48MHz / 480Mb USB2.0 X BUS USBPORT USBPORT SST39VF080 USBPORT USBPORT Touch Pad PIO Int.KBD 1.8V / 0.9V JUSBP3 BT VCORE JUSBP1 JUSBP1 CHARGER RESERVED RESERVED A RESERVED Compal Secret Data Security Classification Issued Date JUSBP2 USBPORT USBPORT KB910 A FIR AMP & Phone/ MIC Jack LPC BUS USBPORT SIO LPC47N217D 5V/3.3V/15V 2005/03/01 2006/03/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D CustomLA-2362 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Friday, March 11, 2005 Date: Rev Sheet of 52 I2C / SMBUS ADDRESSING m o c e u l b p o t p a l w W w External PCI Devices D DEVICE IDSEL # LAN AD17 REQ/GNT # PIRQ F CARD BUS AD20 A 1394 AD16 E Wireless LAN(MINI PCI) AD18 G,H Power Managment table B Cardreader PCB Rev Bringup-Build SST-Build D PT-Build ST-Build Signal State @ Depop 1@ EAL51 2@ EAL50 1@ EAL51 VALUE (DELETE SIO/1394) Data 0.1 +CPU_CORE +VCCP +5VS +3VS +2.5VS +1.8VS +1.25VS +1.5VS +2.5V +3V +5V +12V +12VALW +3VALW +5VALW S0 ON ON ON S1 ON ON ON S3 ON ON OFF S5 S4/AC ON OFF OFF S5 S4/AC don't exist OFF OFF OFF QT-Build SCHEMATICS VERSION LIST VERSION ISSUE DATE REMARK First Release 0.0A C C Ceramic Capacitor Spec Guide: Temperature Characteristics: Symbol CODE Z5U Z5V Z5P Y5U Y5V A NP0 C0G I H UJ B C BJ CH C D Y5P X5R X7R D E F G CJ CK SH SJ J UK SL Tolerance: A Symbol CODE B +-0.05PF +-0.1PF +-0.25PF +-0.5PF F G +-1PF +-2% V X H +-3% J +-5% B B K +-10% N M +-20% +-30% P Q Z +100,-0% +30,-10% +20,-10% +40,-20% +80,-20% SMBUS Control Table SOURCE SMB_EC_CK1 SMB_EC_DA1 PC87591L SMB_EC_CK2 SMB_EC_DA2 PC87591L ICH_SMBCLK ICH_SMBDATA LCD_DDCCLK A LCD_DDCDATA INVERTER BATT SERIAL EEPROM THERMAL SENSOR (CPU) THERMAL SENSOR (LM75) SODIMM CLK CHIP MINI PCI LCD VGA Thermal ADM1032 ICH6-M Alviso GM-GP A Compal Secret Data Security Classification Issued Date 2005/03/01 Deciphered Date 2006/03/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size C Date: Document Number LA-2362 Rev Friday, March 11, 2005 Sheet of 52 m o c e u l b p o t p a l w W w ACIN +3/5/12VALW D 32ms D ON/OFF# 8.5/2.44/3.792ms t 85 degree C442 10U_0805_6.3V6M High Frequence Decoupling C Near VCORE regulator +CPU_CORE @ C357 + + 330U_D2E_2.5VM_R9 C377 + 330U_D2E_2.5VM_R9 C378 330U_D2E_2.5VM_R9 C358 B + 330U_D2E_2.5VM_R9 ESR 880 uF B +VCCP C664 0.1U_0402_10V6K C665 0.1U_0402_10V6K C666 0.1U_0402_10V6K C667 0.1U_0402_10V6K C668 0.1U_0402_10V6K C669 0.1U_0402_10V6K C670 0.1U_0402_10V6K 2 C671 0.1U_0402_10V6K C672 0.1U_0402_10V6K C673 0.1U_0402_10V6K +VCCP + C525 150U_D2_6.3VM 2 C498 0.1U_0402_10V6K C499 0.1U_0402_10V6K C504 0.1U_0402_10V6K C500 0.1U_0402_10V6K C503 0.1U_0402_10V6K C463 0.1U_0402_10V6K C441 0.1U_0402_10V6K 2 C424 0.1U_0402_10V6K C450 0.1U_0402_10V6K C398 0.1U_0402_10V6K A A Compal Secret Data Security Classification Issued Date 2005/03/01 2006/03/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D CustomLA-2362 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Friday, March 11, 2005 Date: Rev Sheet of 52 Layout Guide will show these signals routed differentially H_ADS# H_TRDY# F8 B5 G6 H_DRDY# F7 H_DEFER# E6 TP_H_EDRDY# F6 @ H_HITM# D6 H_HIT# D4 H_LOCK# B3 H_BR0# E7 H_BNR# A5 H_BPRI# D5 H_DBSY# C6 H_R_CPUSLP# G8 H_RS#0 A4 H_RS#1 C5 H_RS#2 B4 HADS# HTRDY# HDPWR# HDRDY# HDEFER# HEDRDY# HHITM# HHIT# HLOCK# HBREQ0# HBNR# HBPRI# HDBSY# HCPUSLP# HRS0# HRS1# HRS2# J11 C1 C2 T1 L1 D1 P1 HVREF HXRCOMP HXSCOMP HYRCOMP HYSCOMP HXSWING HYSWING R477 40.2_0402_1% R476 40.2_0402_1% @ @ DDR_CKE0 DDR_CKE1 DDR_CKE2 DDR_CKE3 DDR_SCS#0 DDR_SCS#1 DDR_SCS#2 DDR_SCS#3 C385 0.1U_0402_16V4Z SM_CK0 SM_CK1 SM_CK2 SM_CK3 SM_CK4 SM_CK5 AN33 AK1 AE10 AJ33 AF5 AD10 SM_CK0# SM_CK1# SM_CK2# SM_CK3# SM_CK4# SM_CK5# DDR_CKE0 DDR_CKE1 DDR_CKE2 DDR_CKE3 AP21 AM21 AH21 AK21 SM_CKE0 SM_CKE1 SM_CKE2 SM_CKE3 DDR_SCS#0 DDR_SCS#1 DDR_SCS#2 DDR_SCS#3 AN16 AM14 AH15 AG16 SM_CS0# SM_CS1# SM_CS2# SM_CS3# 80.6_0402_1% R489 80.6_0402_1% +VCCP CFG[2:0] CFG5 CFG6 10/20 mils CFG16 (FSB Dynamic ODT) CFG18 (VCC Select) CFG19 (VTT Select) 2 CFG/RSVD DMI DMITXN0 DMITXN1 DMITXN2 DMITXN3 AF22 AF16 AP14 AL15 AM11 AN10 SM_OCDCOMP0 SM_OCDCOMP1 SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3 AK10 AK11 AF37 AD1 AE27 AE28 AF9 AF10 SMRCOMPN SMRCOMPP SMVREF0 SMVREF1 SMXSLEWIN SMXSLEWOUT SMYSLEWIN SMYSLEWOUT CFG0 MCH_CLKSEL1 MCH_CLKSEL0 PAD T25 @ PAD T26 @ CFG5 CFG6 CFG7 G16 H13 G14 F16 F15 G15 E16 D17 J16 D15 E15 D14 E14 H12 C14 H15 J15 H14 G22 G23 D23 G25 G24 J17 A31 A30 D26 D25 MCH_CLKSEL1 MCH_CLKSEL0 D CFG9 CFG12 CFG13 CFG16 CFG18 CFG19 H_THERMTRIP# R57 56_0402_5% @ C BM_BUSY# EXT_TS0# EXT_TS1# THRMTRIP# PWROK RSTIN# J23 J21 H22 F5 AD30 AE29 PM_BMBUSY# PM_EXTTS#0 PM_EXTTS#1 H_THERMTRIP# VGATE PLTRST_MCH# R492 100_0402_1% 10K_0402_5% PLTRST_R# R384 DREF_CLKN DREF_CLKP DREF_SSCLKP DREF_SSCLKN NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 A24 A23 D37 C37 DREFCLK# DREFCLK SSC_DREFCLK SSC_DREFCLK# @ R387 AP37 AN37 AP36 AP2 AP1 AN1 B1 A2 B37 A36 A37 10K_0402_5% @ PM_EXTTS#0 R366 10K_0402_5% PM_EXTTS#1 R365 10K_0402_5% +2.5VS +VCCP Refer to sheet for FSB frequency select CFG0 R367 10K_0402_5% CFG6 R369 2.2K_0402_5% Low = DMI x CFG5 R370 2.2K_0402_5% CFG7 R368 2.2K_0402_5% CFG9 R394 @ 2.2K_0402_5% CFG12 R374 @ 2.2K_0402_5% CFG13 R375 @ 2.2K_0402_5% CFG16 R430 @ 2.2K_0402_5% High = DMI x * Low = DDR-II High = DDR-I B * Low = DT/Transportable CPU High = Mobile CPU * Low = Reverse Lane High = Normal Operation 00 01 10 11 * = Reserved = XOR Mode Enabled = All Z Mode Enabled = Normal Operation (Default) CFG[17:3] have internal pull-up * +2.5VS Low = Disabled High = Enabled 3.5 k reserve for choose * Low = 1.05V (Default) CFG18 CFG19 * High = 1.5V Low = 1.05V (Default) @ 1K_0402_5% @ 1K_0402_5% 1 R37 * High = 1.2V R36 2.2K_0402_5% @ 2.2K_0402_5% @ A R35 R38 CFG[19:18] have internal pull-down 3.5 k reserve for choose 2005/03/01 2006/03/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D CustomLA-2362 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Friday, March 11, 2005 Date: +VCCP Compal Secret Data Security Classification Issued Date SMRCOMPN SMRCOMPP DMIRXP0 DMIRXP1 DMIRXP2 DMIRXP3 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 ALVISO_BGA1257 CFG7 R67 221_0603_1% 1 AM33 AL1 AE11 AJ34 AF6 AC10 C419 0.1U_0402_16V4Z +SDREF_DIMM +VCCP R73 100_0603_1% R397 221_0603_1% 2 R388 100_0402_1% C362 0.1U_0402_16V4Z DDR_CLK0 DDR_CLK1 M_OCDOCMP0 M_OCDOCMP1 CFG[13:12] A DMITXP0 DMITXP1 DMITXP2 DMITXP3 DDR_CLK3# DDR_CLK4# +VCCP H_SWNG1 Y33 AA37 AB33 AC37 DDR_CLK0# DDR_CLK1# H_R_CPUSLP# H_SWNG0 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 DDR_CLK3 DDR_CLK4 CFG9 Note: "Do not install R for Dothan-A, Install R97 for Dothan-B" AA33 AB37 AC33 AD37 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 R484 H_VREF H_XRCOMP H_XSCOMP H_YRCOMP H_YSCOMP H_SWNG0 H_SWNG1 +VCCP DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 +2.5V ALVISO_BGA1257 H_CPUSLP# Y31 AA35 AB31 AC35 DDR_CLK0# DDR_CLK1# M_OCDOCMP0 M_OCDOCMP1 H_RS#[0 2] R418 0_0402_5% H_CPUSLP# DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 HCPURST# DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DMIRXN0 DMIRXN1 DMIRXN2 DMIRXN3 NC H_ADS# H_TRDY# H_DPWR# H_DRDY# H_DEFER# T27 PAD H_HITM# H_HIT# H_LOCK# H_BR0# H_BNR# H_BPRI# H_DBSY# DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 AA31 AB35 AC31 AD35 DDR_CLK3 DDR_CLK4 R372 100_0402_1% H_RESET# H10 Alviso CFG[17:3] has internal pull-up U5B DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DDR_CLK0 DDR_CLK1 R376 200_0402_1% H_RESET# HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3 HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3 HDINV#0 HDINV#1 HDINV#2 HDINV#3 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DDR_CLK3# DDR_CLK4# C379 0.1U_0402_16V7K H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 G4 K1 R3 V3 G5 K2 R2 W4 H8 K3 T7 U5 R66 54.9_0402_1% H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 Layout Guide will show these signals routed differentially H_DSTBP#[0 3] HCLKN HCLKP Layout Note: Rote as short as possible R41 54.9_0402_1% AB1 AB2 CLK_MCH_BCLK# CLK_MCH_BCLK H_DSTBN#[0 3] B HPCREQ# HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 HADSTB#0 HADSTB#1 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 E4 E1 F4 H7 E2 F1 E3 D3 K7 F2 J7 J8 H6 F3 K8 H5 H1 H2 K5 K6 J4 G3 H3 J1 L5 K4 J5 P7 L7 J3 P5 L3 U7 V6 R6 R5 P3 T8 R7 R8 U8 R4 T4 T5 R1 T3 V8 U6 W6 U3 V5 W8 W7 U2 U1 Y5 Y2 V4 Y7 W1 W3 Y3 Y6 W2 HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63# R44 24.9_0402_1% TP_H_PCREQ# H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_ADSTB#0 H_ADSTB#1 H_ADSTB#0 H_ADSTB#1 A11 A7 D7 B8 C7 A8 B9 E13 PAD C HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31# R77 24.9_0402_1% T1 H_REQ#[0 4] Alviso G9 C9 E9 B7 A10 F9 D8 B10 E10 G10 D9 E11 F10 G11 G13 C10 C11 D11 C12 B13 A12 F12 G12 E12 C13 B11 D13 A13 F13 HOST H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_D#[0 63] DDR MUXING m o c e u l b p o t p a l w W w U5A H_A#[3 31] D CLK PM C428 0.1U_0402_16V4Z Rev Sheet of 52 D m o c e u l b p o t p a l w W w DDR_A_DQS[0 7] DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2 AK15 AK16 AL21 SA_BS0# SA_BS1# SA_BS2# DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 AJ37 AP35 AL29 AP24 AP9 AP4 AJ2 AD3 SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 AK36 AP33 AN29 AP23 AM8 AM4 AJ1 AE5 SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7 AK35 AP34 AN30 AN23 AN8 AM5 AH1 AE4 SA_DQS0# SA_DQS1# SA_DQS2# SA_DQS3# SA_DQS4# SA_DQS5# SA_DQS6# SA_DQS7# DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 AL17 AP17 AP18 AM17 AN18 AM18 AL19 AP20 AM19 AL20 AM16 AN20 AM20 AM15 SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 DDR_A_CAS# DDR_A_RAS# TP_MA_RCVENIN# TP_MA_RCVENOUT# DDR_A_WE# AN15 AP16 AF29 AF28 AP15 C DDR_A_MA[0 13] DDR_A_CAS# DDR_A_RAS# T36 PAD T35 PAD DDR_A_WE# DDR MEMORY SYSTEM A U5C DDR_A_BS#0 DDR_A_BS#1 T38 PAD DDR_A_DM[0 7] SA_CAS# SA_RAS# SA_RCVENIN# SA_RCVENOUT# SA_WE# B SADQ0 SADQ1 SADQ2 SADQ3 SADQ4 SADQ5 SADQ6 SADQ7 SADQ8 SADQ9 SADQ10 SADQ11 SADQ12 SADQ13 SADQ14 SADQ15 SADQ16 SADQ17 SADQ18 SADQ19 SADQ20 SADQ21 SADQ22 SADQ23 SADQ24 SADQ25 SADQ26 SADQ27 SADQ28 SADQ29 SADQ30 SADQ31 SADQ32 SADQ33 SADQ34 SADQ35 SADQ36 SADQ37 SADQ38 SADQ39 SADQ40 SADQ41 SADQ42 SADQ43 SADQ44 SADQ45 SADQ46 SADQ47 SADQ48 SADQ49 SADQ50 SADQ51 SADQ52 SADQ53 SADQ54 SADQ55 SADQ56 SADQ57 SADQ58 SADQ59 SADQ60 SADQ61 SADQ62 SADQ63 AG35 AH35 AL35 AL37 AH36 AJ35 AK37 AL34 AM36 AN35 AP32 AM31 AM34 AM35 AL32 AM32 AN31 AP31 AN28 AP28 AL30 AM30 AM28 AL28 AP27 AM27 AM23 AM22 AL23 AM24 AN22 AP22 AM9 AL9 AL6 AP7 AP11 AP10 AL7 AM7 AN5 AN6 AN3 AP3 AP6 AM6 AL4 AM3 AK2 AK3 AG2 AG1 AL3 AM2 AH3 AG3 AF3 AE3 AD6 AC4 AF2 AF1 AD4 AD5 DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 D U5D DDR_A_D[0 63] DDR_B_BS#0 DDR_B_BS#1 T37 PAD DDR_B_BS#0 DDR_B_BS#1 DDR_B_BS#2 This Symbol as same as Intel CRB schematic, So Layout Guide will show these signals routed differentially DDR_B_MA[0 13] DDR_B_CAS# DDR_B_RAS# T33 PAD T34 PAD DDR_B_WE# ALVISO_BGA1257 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_CAS# DDR_B_RAS# TP_MB_RCVENIN# TP_MB_RCVENOUT# DDR_B_WE# AJ15 AG17 AG21 SB_BS0# SB_BS1# SB_BS2# AF32 AK34 AK27 AK24 AJ10 AK5 AE7 AB7 SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7 AF34 AK32 AJ28 AK23 AM10 AH6 AF8 AB4 SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7 AF35 AK33 AK28 AJ23 AL10 AH7 AF7 AB5 SB_DQS0# SB_DQS1# SB_DQS2# SB_DQS3# SB_DQS4# SB_DQS5# SB_DQS6# SB_DQS7# AH17 AK17 AH18 AJ18 AK18 AJ19 AK19 AH19 AJ20 AH20 AJ16 AG18 AG20 AG15 SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 AH14 AK14 AF15 AF14 AH16 DDR SYSTEM MEMORY B SB_CAS# SB_RAS# SB_RCVENIN# SB_RCVENOUT# SB_WE# SBDQ0 SBDQ1 SBDQ2 SBDQ3 SBDQ4 SBDQ5 SBDQ6 SBDQ7 SBDQ8 SBDQ9 SBDQ10 SBDQ11 SBDQ12 SBDQ13 SBDQ14 SBDQ15 SBDQ16 SBDQ17 SBDQ18 SBDQ19 SBDQ20 SBDQ21 SBDQ22 SBDQ23 SBDQ24 SBDQ25 SBDQ26 SBDQ27 SBDQ28 SBDQ29 SBDQ30 SBDQ31 SBDQ32 SBDQ33 SBDQ34 SBDQ35 SBDQ36 SBDQ37 SBDQ38 SBDQ39 SBDQ40 SBDQ41 SBDQ42 SBDQ43 SBDQ44 SBDQ45 SBDQ46 SBDQ47 SBDQ48 SBDQ49 SBDQ50 SBDQ51 SBDQ52 SBDQ53 SBDQ54 SBDQ55 SBDQ56 SBDQ57 SBDQ58 SBDQ59 SBDQ60 SBDQ61 SBDQ62 SBDQ63 AE31 AE32 AG32 AG36 AE34 AE33 AF31 AF30 AH33 AH32 AK31 AG30 AG34 AG33 AH31 AJ31 AK30 AJ30 AH29 AH28 AK29 AH30 AH27 AG28 AF24 AG23 AJ22 AK22 AH24 AH23 AG22 AJ21 AG10 AG9 AG8 AH8 AH11 AH10 AJ9 AK9 AJ7 AK6 AJ4 AH5 AK8 AJ8 AJ5 AK4 AG5 AG4 AD8 AD9 AH4 AG6 AE8 AD7 AC5 AB8 AB6 AA8 AC8 AC7 AA4 AA5 C B ALVISO_BGA1257 A A Compal Secret Data Security Classification Issued Date 2005/03/01 2006/03/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D CustomLA-2362 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Friday, March 11, 2005 Date: Rev Sheet of 52 m o c e u l b p o t p a l w W w +2.5VS MISC 1@ R428 R392 4.99K_0603_1% 0_0402_5% CLK_DDC2 DAT_DDC2 CLK_DDC2 DAT_DDC2 CRT_BLU CRT_GRN CRT_RED VSYNC HSYNC R429 255_0402_1% BIA TVDAC_A TVDAC_B TVDAC_C TV_REFSET TV_IRTNA TV_IRTNB TV_IRTNC TV 1@ A15 C16 A17 J18 B15 B16 B17 1@ R34 150_0402_1% 1@ R33 150_0402_1% R32 150_0402_1% Y/G COMP/B C/R E24 E23 E21 D21 C20 B20 A19 B19 H21 G21 J20 DDCCLK DDCDATA BLUE BLUE# GREEN GREEN# RED RED# VSYNC HSYNC REFSET VGA CLK_MCH_3GPLL# CLK_MCH_3GPLL BK_EN R396 100K_0402_1% 2 BIA BK_EN R404100K_0402_1% LCD_CLK LCD_DAT EN_LCDVDD LCTLA_CLK LCTLB_DAT LCD_CLK LCD_DAT EN_LCDVDD R3781.5K_0402_1% LVDS_ACLVDS_AC+ LVDS_BCLVDS_BC+ LVDS_A0 LVDS_A1 LVDS_A2 LVDS_A0+ LVDS_A1+ LVDS_A2+ B LVDS_B0 LVDS_B1 LVDS_B2- LVDS_ACLVDS_AC+ LVDS_BCLVDS_BC+ B30 B29 C25 C24 LVDS_A0LVDS_A1LVDS_A2- B34 B33 B32 LVDS_A0+ LVDS_A1+ LVDS_A2+ A34 A33 B31 LVDS_B0LVDS_B1LVDS_B2- C29 D28 C27 LVDS_B0+ LVDS_B1+ LVDS_B2+ LVDS_B0+ LVDS_B1+ LVDS_B2+ E25 F25 C23 C22 F23 F22 F26 C33 C31 F28 F27 C28 D27 C26 LBKLT_CTL LBKLT_EN LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA LVDD_EN LIBG LVBG LVREFH LVREFL LACLKN LACLKP LBCLKN LBCLKP LADATAN0 LADATAN1 LADATAN2 LADATAP0 LADATAP1 LADATAP2 LBDATAN0 LBDATAN1 LBDATAN2 LBDATAP0 LBDATAP1 LBDATAP2 LVDS C D36 D34 PEGCOMP EXP_RXN0/SDVO_TVCLKIN# EXP_RXN1/SDVO_INT# EXP_RXN2/SDVO_FLDSTALL# EXP_RXN3 EXP_RXN4 EXP_RXN5 EXP_RXN6 EXP_RXN7 EXP_RXN8 EXP_RXN9 EXP_RXN10 EXP_RXN11 EXP_RXN12 EXP_RXN13 EXP_RXN14 EXP_RXN15 E30 F34 G30 H34 J30 K34 L30 M34 N30 P34 R30 T34 U30 V34 W30 Y34 PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15 EXP_RXP0/SDVO_TVCLKIN EXP_RXP1/SDVO_INT EXP_RXP2/SDVO_FLDSTALL EXP_RXP3 EXP_RXP4 EXP_RXP5 EXP_RXP6 EXP_RXP7 EXP_RXP8 EXP_RXP9 EXP_RXP10 EXP_RXP11 EXP_RXP12 EXP_RXP13 EXP_RXP14 EXP_RXP15 D30 E34 F30 G34 H30 J34 K30 L34 M30 N34 P30 R34 T30 U34 V30 W34 PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15 EXP_TXN0/SDVOB_RED# EXP_TXN1/SDVOB_GREEN# EXP_TXN2/SDVOB_BLUE# EXP_TXN3/SDVOB_CLKN EXP_TXN4/SDVOC_RED# EXP_TXN5/SDVOC_GREEN# EXP_TXN6/SDVOC_BLUE# EXP_TXN7/SDVOC_CLKN EXP_TXN8 EXP_TXN9 EXP_TXN10 EXP_TXN11 EXP_TXN12 EXP_TXN13 EXP_TXN14 EXP_TXN15 E32 F36 G32 H36 J32 K36 L32 M36 N32 P36 R32 T36 U32 V36 W32 Y36 PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15 D32 E36 F32 G36 H32 J36 K32 L36 M32 N36 P32 R36 T32 U36 V32 W36 PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15 EXP_COMPI EXP_ICOMPO PCI - EXPRESS GRAPHICS D R29 @ 3K_0402_5% U5G H24 SDVOCTRL_DATA H25 SDVOCTRL_CLK R30 @ 3K_0402_5% AB29 GCLKN AC29 GCLKP +1.5VS_PCIE R40 24.9_0603_1% PEG_RXN[0 15] PEG_RXP[0 15] PEG_RXN[0 15] +2.5VS PEG_RXP[0 15] LCD_CLK R362 2.2K_0402_5% LCD_DAT R363 2.2K_0402_5% LCTLA_CLK R385 2.2K_0402_5% LCTLB_DAT R364 2.2K_0402_5% CLK_DDC2 R360 2.2K_0402_5% DAT_DDC2 R361 2.2K_0402_5% This Symbol as same as Intel CRB schematic, So Layout Guide will show these signals routed differentially 1 1 C PEG_TXN[0 15] PEG_TXN[0 15] PEG_TXP[0 15] EXP_TXP0/SDVOB_RED EXP_TXP1/SDVOB_GREEN EXP_TXP2/SDVOB_BLUE EXP_TXP3/SDVOB_CLKP EXP_TXP4/SDVOC_RED EXP_TXP5/SDVOC_GREEN EXP_TXP6/SDVOC_BLUE EXP_TXP7/SDVOC_CLKP EXP_TXP8 EXP_TXP9 EXP_TXP10 EXP_TXP11 EXP_TXP12 EXP_TXP13 EXP_TXP14 EXP_TXP15 D PEG_TXP[0 15] B ALVISO_BGA1257 A A Compal Secret Data Security Classification Issued Date 2005/03/01 2006/03/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D CustomLA-2362 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Friday, March 11, 2005 Date: Rev Sheet 10 of 52 A C m o c e u l b p o t p a l w W w PJPD1 P1 BATT++ PL2 HCB4532K-800T90_1812 BATT++ PC7 0.01U_0402_25V7Z PC8 1000P_0402_50V7K 2 PR5 10_1206_5% PC4 560P_0402_50V7K BATT_TEMP PR15 1K_0402_5% RLZ24B_LL34 PJP1 PJPB1 battery connector SMART Battery: 1.BAT+ 2.ID 3.B/I 4.TS 5.SMD 6.SMC 7.GND BATT+ ID B/I TS SMD G SMC G GND PR18 1K_0402_5% 2 +3VALWP SUYIN_200275MR007G113ZL PR21 25.5K_0402_1% SMB_EC_DA1 SMB_EC_CK1 PR22 100_0402_5% PR14 2.2M_0402_5% VL BATT_TEMP PD30 PC3 12P_0402_50V8J SINGA_2DC-S756B200 PC2 12P_0402_50V8J 2 PC1 560P_0402_50V7K G G 1 BATT+ VIN FBM-L18-453215-900LMA90T_1812 PL1 P1 D BATT+ B PR25 100_0402_5% VS B+ PR17 499K_0402_1% PU1A LM393M_SO8 D BATT ONLY Precharge detector Min typ Max H >L 6.138V 6.214V 6.359V L >H 7.196V 7.349V 7.505V A 1 RHU002N06_SOT323 PQ1 G 47K_0402_5% PR24 PACIN PD1 1N4148_SOD80 VIN+ PR11 1.5K_1206_5% B+ PR12 1.5K_1206_5% PACIN S PR23 34K_0402_1% VIN PQ2 DTC115EUA_SC70 PR26 66.5K_0402_1% PR13 1.5K_1206_5% +5VALWP 4 PC10 1000P_0402_50V7K VL Precharge detector Min typ Max H >L 14.589V 14.84V 15.243V L >H 15.562V 15.97V 16.388V PR20 499K_0402_1% 191K_0402_1% ACIN PR10 1.5K_1206_5% 2 PC11 0.1U_0603_25V7K PR19 1 PRG++ - 2 RB715F_SOT323 + O PC12 1000P_0402_50V7K 1 P G PD2 ACON PR16 100K_0402_1% 20,41,44> MAINPWRON 3 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE CUSTODY OF THE COMPETENT DIVISION OFTHE R&D DEPARTMENT EXCEPT AS TRANSFERRED FROM AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B C Compal Electronics, Inc Title DCIN & DETECTOR & Precharge Size B Date: Document Number Rev LA-2362 Sheet Friday, March 11, 2005 D 39 of 52 A B C D E Charger Iadp=0~3A(65W) m o c e u l b p o t p a l w W w P2 PR161 10K_0402_5% 2 PR1 0_0402_5% 2 PC145 0.1U_0603_25V7K 2 LDO PL17 16UH_D104C-919AS-160M_3.7A_20% PD27 1SS355_SOD323 22 DLOV BATT+ PR165 0.015_2512_1% PR170 33_1206_5% PC151 1U_0603_10V6K PGND 1908LDO 19 18 16 CSIP CSIN BATT PC150 1U_0805_25V4Z MAX1908-CCS 2 BATT+ PC154 0.1U_0402_16V7K PR177 0_0402_5% BATT+ 4S CC-CV MODE : 16.8V PR181 300K_0603_0.1% BATT_OVP + - PR182 20K_0402_1% +2.5V PR194 681K_0603_1% P G PACIN BATT-OVP=0.111*BATT+ LI-3S :17.8V BATT-OVP=1.9758V PU14A LM358A_SO8 PR179 845K_0603_1% 0.01U_0402_25V7Z PR180 150K_0402_1% OVP voltage : Charge voltage 1 VIN VS PC155 0.1U_0402_16V7K PC156 2P4S:4300mAH/cell 0.7C=3.0A PR193 100K_0402_5% PR178 10K_0402_5% 2 FSTCHG PQ40 DTC115EUA_SC70 1 24 BST PD31 RLZ4.3B_LL34 DLO IINP CCV CCI @ 158K_0603_1% 28 PC152 1000P_0402_50V7K 2 PR173 100K_0402_1% 3 1 PACIN ACOK# SHDN# ACIN ICHG 1908LDO 10K_0402_5% PR175 PR4 10K_0402_5% ACIN ACIN VCTL ICTL 11 10 GND 0_0402_5% PACIN 23 21 20 0_0402_5% PR169 PR172 PR171 22K_0402_5% 15 13 14 PC149 0.01U_0402_16V7K IREF PR190 LX PC18 1000P_0402_50V7K AO4912_SO8 REFIN CCS PR168 @ PD26 1SS355_SOD323 PQ36 DTC114EKA_SC59 1 25 10K PC153 1000P_0402_50V7K 2 12 PR184 15K_0402_1% 0_0402_5% ACON DHI 2 PC148 4.7U_1206_25V6K CLS 1 26 G2 D2 D1/S2/K D2 D1/S2/K G1 D1/S2/K S1/A REF PR174 1K_0402_1% ACON S PC144 PR166 0.1U_0402_16V7K 9.31K_0402_1% ACOFF# G D PR167 100K_0402_1% RHU002N06_SOT323 PD28 1SS355_SOD323 1908LDO CSSN CELLS 27 17 10K PQ38 CSSP PC146 4.7U_1206_25V6K 150K_0402_1% PR164 PQ39 PD24 @ 1SS355_SOD323 PQ37 RHU002N06_SOT323 2 PC142 1U_0603_10V6K PC143 0.1U_0603_25V7K PR163 0_0402_5% ACOFF ACOFF# PU13 MAX1908ETI_QFN28 DCIN 3 S PD32 @ RLZ22B_LL34 PD25 VIN 1 PQ35 DTC115EUA_SC70 PR162 150K_0402_5% VIN PC147 4.7U_1206_25V6K @ @ 1SS355_SOD323 D PR160 47K_0402_5% 1 2 G PC140 4.7U_1206_25V6K PC139 4.7U_1206_25V6K + PQ33 AO4407_SO8 2 0.1U_0603_25V7K PC158 0.01_2512_1% 2 PC138 4.7U_1206_25V6K 1 PC14 220U_25V_M PR159 200K_0402_1% 1 47K 47K PL16 HCB4532K-800T90_1812 PR157 DTA144EUA_SC70 PQ34 2 0.1U_0603_25V7K PC141 PR158 47K_0402_5% 1 P3 VIN B+ PQ32 AO4407_SO8 PC159 0.1U_0603_25V7K PQ31 AO4407_SO8 2 VS PR191 10K_0402_1% PU14B LM358A_SO8 PC157 0.01U_0402_25V7Z PR183 143K_0402_1% + - +SDREF PR192 10K_0402_1% Compal Electronics, Inc Title PROPRIETARY NOTE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size B Date: A B C D Charger Document Number Rev LA-2362 Sheet Friday, March 11, 2005 E 40 of 52 A B C D E +3.3V/+5V/+12V +3VALWP Choke DCR = 26.5mΩ Current limit Threshold Min.=80 mV Mx.=120mV OCP Min.= 80mV/1.27K*(1.27K+1.27K)/26.6=6.038A OCP Max.=120mV/1.27K*(1.27K+1.27K)/26.5=9.056A m o c e u l b p o t p a l w W w PD29 EC11FS2_SOD106 PC161 @470P_0805_100V7K 2 B+ 10U_1210_25V6M PC160 PL8 2 1 2 2 1 1 LX5 DL5 1 2.5VREF PR99 PC83 698_0402_1% 0.47U_0603_16V7K PR102 0_0402_5% PR96 1.54K_0402_1% PC87 4.7U_0805_6.3V6K +5VALWP PC86 1000P_0402_50V7K PR95 2M_0402_1% DH5 VL 21 22 V+ RUN/ON3 BST5 28 PR100 @ 300K_0402_5% 1 18 16 17 19 20 14 13 12 15 11 2 1 10 23 12OUT VDD BST5 DH5 LX3 LX5 DL3 DL5 PGND MAX1902EAI_SSOP28 CSH5 CSH3 CSL5 CSL3 FB5 FB3 SEQ SKIP# REF SHDN# SYNC RST# TIME/ON5 DH3 26 24 BST3 GND PC82 PR98 10K_0402_5% PR101 3.57K_0402_1% PD17 SKUL30-02AT_SMA 1 PD18 SKS10-04AT_TSMA 2 PR103 10.2K_0402_1% 1 + PC89 100P_0402_50V8J PC88 150U_D2_6.3VM_R45 VS MAINPWRON PR105 0_0402_5% PR104 10K_0402_1% 2 27 PC84 100P_0402_50V8J PC79 47P_0402_50V8J 150U_D2_6.3VM_R45 + S PR91 0_0402_5% G PR94 1M_0402_1% PU6 25 0.47U_0603_16V7K PR97 619_0402_1% PC85 D PC162 4.7U_1206_25V6K PQ41 @ RHU002N06_SOT323 PR93 1.27K_0402_1% ACIN ACIN PC78 0.1U_0603_25V7K 1 2 PR2 33_1206_5% AO4912_SO8 PC75 4.7U_0805_6.3V6K PR187 @ 2.7K_1206_5% 1 PD15 1SS355_SOD323 G2 D2 D1/S2/K D2 D1/S2/K G1 D1/S2/K S1/A PC77 4.7U_1206_25V6K PC76 @2200P_0402_50V7K PQ18 PR89 0_0402_5% DH3 PC81 47P_0402_50V8J +3VALWP B+++ +12VALWP VS VL DL3 PR92 1.27K_0402_1% 10uH_SDT-1205P-100-118_5A_20% PD14 DAP202U_SOT323 LX3 PL10 10UH_D104C-919AS-100M_4.5A_20% FLYBACK PL9 AO4912_SO8 0.1U_0603_25V7K PC72 D2 G2 D2 D1/S2/K G1 D1/S2/K S1/A D1/S2/K PC74 4.7U_1206_25V6K 2 PC73 @ 2200P_0402_50V7K PQ17 PR186 @ 22_1206_5% B+++ SNB BST51 PC71 0.1U_0603_25V7K BST31 FBM-L18-453215-900LMA90T_1812 2 1 PR106 10K_0402_1% PC90 2.2U_0805_10V6K PC91 @1U_0805_25V4Z +5VALWP Choke DCR = 40mΩ Current limit Threshold Min.=80 mV Mx.=120mV OCP Min.= 80mV/0.698K*(1.54K+0.698K)/40=6.412A OCP Max.=120mV/0.698K*(0.698K+1.54K)/40=9.593A 4 RS2(PR64)=RS1(PR58)*RS3(PR61)/(RS1+RS3) L/RL(DCR)=RS1*RS3(PR61)/(RS1+RS3)*Cs(PC56) Compal Electronics, Inc Title 3.3V / 5V / 12V THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINSSize CONFIDENTIAL Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Friday, March 11, 2005 Date: Rev LA-2362 A B C D 0.1 Sheet E 41 of 52 m o c e u l b p o t p a l w W w 27 24 28 PR61 499_0402_1% UVP PC47 0.1U_0603_25V7K 1 DH1 BST2 DH2 LX1 LX2 DL1 DL2 MAX8743EEI_QSOP28 CS2 CS1 OUT1 OUT2 FB2 FB1 ON2 PC41 0.1U_0603_25V7K 1 21 19 18 17 20 16 +2.5VP BST2.5A VDD PC42 4.7U_1206_25V6K PL6 4.7UH_D104C-919AS_4R7N_5.2A_20% LX2.5 DH2.5 DL2.5 @ + B 15 14 12 VCC 26 BST1 PU4 25 22 PC46 0.1U_0603_25V7K PC43 4.7U_1206_25V6K AO4912_SO8 PR55 0_0402_5% V+ 1 @ B 2 PC51 4.7U_0805_6.3V6K + PC50 150U_D2_6.3VM_R45 @ G2 D2 D1/S2/K D2 D1/S2/K G1 D1/S2/K S1/A PC48 150U_D2_6.3VM_R45 PR53 20_0603_5% +VCCPP PQ13 4.7U_0805_6.3V6K PC49 2 PR54 0_0402_5% PL5 4.7UH_D104C-919AS_4R7N_5.2A_20% 1 BST2.5B 1U_0805_25V4Z PC44 0.1U_0603_25V7K PC38 AO4912_SO8 PC40 2200P_0402_50V7K PD7 DAP202U_SOT323 PQ12 D2 G2 D2 D1/S2/K G1 D1/S2/K S1/A D1/S2/K PC6 @ 1U_0805_50V4Z C @ B+ PC5 @ 0.1U_0603_25V7K +5VALW D PL3 FBM-L18-453215-900LMA90T_1812 PC39 4.7U_0805_6.3V6K MAX8743_B+ PC36 4.7U_1206_25V6K PC34 2200P_0402_50V7K C Vin=19V,Vo=2.5V,Io=4.5A,Fs=255KHZ,L=4.7UH Mosfet Rds(on) tpy.=19.7mΩ Max=24mΩ,Delta I =1.8115A Iimit=ILIM(V)/10/Rds(on)+1/2 delta I Iimit Min=1.98V*100K/(100K+33K)/10/31.2mΩ+0.905=5.6765A Iimit Max=2.02V*100K/(100K+33K)/10/19.7mΩ+0.905=8.614A +2.5VP = 5.6765A ~ 8.614A Vin=19V,Vo=2.5V,Io=4.5A,Fs=345KHZ,L=4.7UH Mosfet Rds(on) tpy.=19.7mΩ Max=24mΩ,Delta I =0.6118A Iimit=ILIM(V)/10/Rds(on)+1/2 delta I Iimit Min=1.98V*100K/(100K+15K)/10/31.2mΩ+0.3059=5.824A Iimit Max=2.02V*100K/(100K+15K)/10/19.7mΩ+0.3059=9.821A +VCCPP = 5.824A ~ 9.821A PC35 0.1U_0603_25V7K D 13 SYSON +3VALWP PR69 10K_0402_5% 15K_0402_1% PR67 0_0402_5% PR66 100K_0402_1% PR58 33K_0402_1% PR59 2 PC45 0.22U_0603_10V7K ILIM2 ILIM1 PR65 100K_0402_1% REF 10 GND SKIP 23 PC54 @ 0.01U_0402_25V8K PGOOD TON ON1 PR68 0_0402_5% 11 OVP 1 SUSP# PR64 10K_0402_1% +VCCP_PWRGD PD3 RB751V_SOD323 A A PC17 @ 1000P_0402_50V7K SUSP# COMPAL ELECTRONICS, INC Title +2.5VP & +VCCPP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINSSize CONFIDENTIAL Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Friday, March 11, 2005 Rev LA-2362 Sheet 42 of 52 m o c e u l b p o t p a l w W w PJP2 3MM PJP3 2MM +5VALW +2.5VP PU9 +12VALWP +12VALW PJP7 3MM +3VALW +VCCPP VIN VCNTL GND NC VREF NC VOUT NC TP +3VALW PC93 10U_1206_6.3V7K PR107 1K_0402_1% PC92 1U_0603_16V6K C PJP4 3MM C +3VALWP 1 2 1 +5VALWP D D +VCCP +2.5V PC97 0.1U_0603_25V7K PR108 1K_0402_1% 2 PJP6 3MM +2.5VP 1 APL5331KAC-TR_SO8 +1.25VS SUSP D S PQ20 RHU002N06_SOT323 G +1.25VSP +1.5VS @ + PC98 150U_D2_6.3VM +1.5VSP PR109 0_0402_5% PJP10 3MM 1 1 +1.25VSP PJP8 3MM PC99 4.7U_0805_6.3V6K B B A A Compal Electronics, Inc Title +1.25VSP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2362 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev Sheet Friday, March 11, 2005 43 of 52 A B C Ipeak=Iocset*Rocset/RDS(ON)high side Iocset=40uA, Pocset=4.12K RDS(on)=25.5mΩ Ipeak min=40uA*4.12/(25.5*1.3)=4.97A Ipeak max=40uA*4.12/25.5=6.46A m o c e u l b p o t p a l w W w PH2 under CPU botten side : CPU thermal protection at 80 degree C Recovery at 44(45) degree C PR72 47K_0402_1% VL VS + TM_REF1 - MAINPWRON O PC60 0.1U_0402_16V7K 2 PR77 4.12K_0402_1% PD12 1SS355_SOD323 PQ42 RHU002N06_SOT323 1 LGATE GND PR82 8.87K_0603_1% APW7057KC-TR_SOP8 PR79 33_1206_5% TP0610K_SOT23 PQ16 +1.5VSP PC66 0.1U_0402_16V7K RB751V_SOD323 PHASE PL7 4.7UH_D104C-919AS_4R7N_5.2A_20% FB S PC61 0.1U_0402_16V7K BATT+ SI4814DY_SO8 D G PD10 UGATE 2 1 PD9 1N4148_SOD80 SUSP PR189 0_0402_5% VIN BOOT OCSET G1 D1 S1/D2 D1 S1/D2 G2 S1/D2 S2 + PC62 150U_D2_6.3VM_R45 VS @ PC64 4.7U_0805_6.3V6K VCC PU8 PR76 150K_0402_1% PQ15 1 1 PC59 470P_0402_50V7K PR75 150K_0402_1% PR78 2.2_0402_5% VL PC58 4.7U_0805_6.3V6K LM393M_SO8 2 1U_0805_16V7K PC56 10KB_0603_1%_TH11-3H103FT PH1 2 PU1B P PC55 0.1U_0603_25V7K G PR73 16.9K_0402_1% 1000P_0402_50V7K +5VALW 1 PR71 47K_0402_1% PR74 2.15K_0402_1% PC57 VL D 1 PC65 0.22U_1206_25V7K 2 PR81 100K_0402_5% 51ON# PR84 10K_0402_1% PC63 0.1U_0603_25V7K 2 PR80 200_0805_5% PR83 22K_0402_5% RTCVREF PU7 G920AT24U_SOT89 CHGRTCP IN OUT 1 GND A 2 PC67 1U_0805_25V4Z PR85 300_0402_5% CHGRTC PR86 300_0402_5% PC68 4.7U_0805_6.3V6K THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B C Compal Electronics, Inc Title RTC Battery & OTP & +1.5VP Size B Date: Document Number Rev LA-2362 Sheet Friday, March 11, 2005 D 44 of 52 B+ CPU_B+ +5VS 1 TON BSTS 35 REF DHS 33 ILIM LXS 34 PC127 470P_0402_50V7K PR141 PR151 20K_0402_1% 18 SKIP CSN 39 11 GND GNDS 13 MAX1532AETL_TQFN40 PC131 27P_0402_50V8J 1 S OAIN+ PR7 0_0402_5% PC136 0.22U_0603_16V7K PQ28 AO4410_SO8 B PQ30 HMBT2222A_SOT23 2 PC13 0.1U_0603_25V7K PC9 1U_0805_50V4Z PC118 68U_25V_M Vin=19V,Vo=1.484V,Io=12.5A,Fs=300KHZ,L=0.56UH Current sense tpy.=1mΩ Max=1.1mΩ,Delta I =8.12A Iimit=ILIM(V)/20/DCR+1/2 delta I Iimit Min={1.99V*78.7K/(78.7K+470K)/20/1.01mΩ+4.22A}*2=36.69A Iimit Max={2.01V*78.7K/(78.7K+470K)/20/0.99mΩ+4.22A}*2=37.56A B PC137 0.47U_0603_16V7K PC16 680P_0603_50V7K A @ E PR150 100K_0402_1% @ PL15 0.56UH_ETQP4LR56WFC_21A_20% RHU002N06_SOT323 PC20 1000P_0402_50V7K CPU_B+ PD22 EP10QY03 PC19 1000P_0402_50V7K D PC129 PR146 0.022U_0402_16V7K 0_0402_5% PQ27 AO4408_SO8 2 2 PR143 3K_0603_1% 1 40 PC135 0.01U_0402_25V7Z 32 CSP DLS SUS +5VS 1 @ OFS OAIN+ C PR153 10K_0402_1% PQ29 G 909_0402_1% 2 PC125 1000P_0402_50V7K FB PR137 3K_0603_1% 15 14 0.47U_0603_16V7K 499_0402_1% FB CCI @ PR136 OAIN- 499_0402_1% 16 PC124 PR135 OAIN- 909_0402_1% SHDN# CPU VCC SENSE PR134 PR132 OAIN+ CCV @100K_0402_1% 17 38 OAIN+ 0.001_2512_5% CMN S1 S0 TIME PC116 0.01U_0402_25V7Z 12 PC115 4.7U_1206_25V6K PC114 4.7U_1206_25V6K 37 909_0402_1% PR155 2 1 PSI# 31 CMP PR154 100K_0402_1% C PGND VROK 2 +5VS D5 25 PQ24 AO4410_SO8 S PQ26 RHU002N06_SOT323 S G PR149 0_0402_5% PM_DPRSLPVR D 19 PR129 PC134 4.7U_1206_25V6K PC130 100P_0402_50V8J 3 PQ25 RHU002N06_SOT323 PR147 D G H_STP_CPU# B PC128 0.22U_0603_16V7K 2 PR145 100K_0402_1% 10.7K_0402_1% FB PR142 470K_0402_5% 29 +CPU_CORE PL14 0.56UH_ETQP4LR56WFC_21A_20% PR3 4.7K_1206_5% PR8 4.7K_1206_5% PR144 78.7K_0603_1% 2 27 DLM 0_0402_5% 1 LXM D4 PR6 2 PC133 4.7U_1206_25V6K PC126 270P_0402_50V7K D3 20 2 30.1K_0402_1% 21 PR125 2_0402_5% VR_ON PR140 28 PC15 680P_0603_50V7K DHM PD23 EC31QS04 D2 2200P_0402_50V7K PC132 C VCC 22 PR139 @ 100K_0402_5% 26 D @ PC123 0.22U_0603_16V7K VGATE PR138 0_0402_5% 36 BSTM @ @ VID5 V+ D1 + VID4 D0 23 PC122 0.01U_0402_25V7Z 30 2_0402_5% VID3 24 VDD PR148 VID2 VCC VID1 10 VCC PC117 2200P_0402_50V7K PQ23 AO4408_SO8 PC121 PU12 1U_0603_16V6K PR123 0_0402_5% PR124 0_0402_5% PR126 0_0402_5% PR128 0_0402_5% PR130 0_0402_5% PR131 0_0402_5% PR133 0_0402_5% VID0 PC120 2.2U_0603_6.3V6K PR122 33K_0402_5% D PD20 EP10QY03 PD21 EC31QS04 1 PR121 10_0402_5% m o c e u l b p o t p a l w W w +3V FBM-L18-453215-900LMA90T_1812 PL13 2 A PR156 909_0402_1% Compal Electronics, Inc Title +CPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B LA-2362 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Friday, March 11, 2005 Rev Sheet 45 of 52 m o c e u l b p o t p a l w W w Version change list (P.I.R List) D Item Fixed Issue Page of Reason for change Rev Modify List B.Ver# Phase ICH_PME# pull up +3VALW add R 10K 0.2 DVT LID_SW# pull up +3VALW add R 10K 0.2 DVT SB +1.5V regulator footprint error 0.2 DVT SB +1.5V regulator footprint error U8 need to reverse 0.2 DVT R76 take off 0.2 DVT PR191 power plane 2.5vref change to +2.5V 0.2 DVT R398 remove to R401 0.2 DVT H_DPRSLP# add pull up to +vccp power plane POP R546 0.2 DVT POP U9 for lose and foot print error 0.2 DVT 10 U3 pin6 & pin need to swap 0.2 DVT 11 Add R476/7 40.2 Ohm for memory 0.2 DVT 12 R259 short 0.2 DVT 13 PR122 chang power plane to +3V for EC voltage leakage 0.2 DVT 14 Add R224/R290/R407 470ohm and Q34/9/11 2N7002 0.1 DVT-2 15 ADD R 39K//220p to GND at R518 for modify SIRQ 0.1 DVT-2 16 Reverse the JHP1 & JMIC1 Symble error 0.1 DVT-2 17 Modify NB FSB speed select for Dothan 0.1 DVT-2 18 Modify ACIN for SB 0.1 DVT-2 19 CardReader pin swap for flash memory 0.1 DVT-2 20 Reverse the JHP1 & JMIC1 Symbl 0.1 DVT-2 21 Add VCCP noise cap at CPU C664/5/6/7/8/9 C670/1/2 0.2 DVT-3 22 Change R362/3 2.2K to 10K for Panel select 0.2 DVT-3 C B PG# D C B A A Compal Electronics, Inc Title PIR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2362 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev Sheet Friday, March 11, 2005 46 of 52 m o c e u l b p o t p a l w W w Version change list (P.I.R List) D C B Item Fixed Issue Page of Reason for change Rev PG# Modify List 23 Add C674/5/6/7/8 C680/1/2/3/4/5 C686/7/8/9 C690/1/2/3/4/5/6/7/8/9 C702/3 for NB VCCP noise cap 24 ADD C646/7/8/9 C650/1/2/3/4/5 for DDR RAM 1.25V noise cap B.Ver# Phase 0.2 DVT-3 0.2 DVT-3 25 ADD C704/5 for JVGAP1 2.5V for noise 0.2 DVT-3 26 Change R17/8/9 from 75 to 150 OHM for TV-out signal 0.2 DVT-3 27 ADD R774/5 for cost down U29 parts 0.2 DVT-3 28 Change SB(U5) sus power from V plane to Always power plane and R457 R69 R456 R455 R456 R451 U7.T2 +1.5VR 0.2 DVT-3 29 R154 remove for FIR function 0.2 DVT-3 30 ADD C656/7 C659/8 for +5VS HDD CDROM power noise 0.2 DVT-3 31 U9 replace the new package to RM8 and remove to TOP 0.2 DVT-3 32 ADD C706/7/8/9/10/11 for SB 1.5Vrun noise 0.2 DVT-3 33 R129 change to +5VALW 0.2 DVT-3 34 Q3 cahnge to AO3400 for current rating not enough 0.2 DVT-3 35 JMPCI1 P.24 change to +3V for wireless power 0.2 DVT-3 36 Remove KB910 & 39VF080 ROM 0.2 DVT-3 37 R705 change to 13K for MB ID 0.2 DVT-3 38 Change the Killer switch circuit for EC detect method then light on the LED 0.2 DVT-3 39 Move U32 to near NB 0.2 DVT-3 40 ADD 5VALW noise cap C714/5/2/3, 0.2 DVT-3 D C B 41 42 43 44 A A Compal Electronics, Inc Title PIR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2362 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev Sheet Friday, March 11, 2005 47 of 52 A B C D Version change list (P.I.R List) m o c e u l b p o t p a l w W w Item 1 Fixed Issue Reason for change Delete the charge circuit Delete the charge circuit Change the CPU OTP circuit from active H to active L E Page of Rev PG# Modify List 1.Delete the PU5 0.2 38 B.Ver# Phase IC LM393M (SM) 2.Delete PD1 S DIO 1N4148 (SM) 0.2 DVT 0.2 DVT 0.2 DVT 3.Delete PR10,PR11,PR12,PR13 S RES 1/4W 1.5K +-5% 1206 1.Delete PQ14 S TR DTC115EUA NPN (UMT3) Delete PD8 S DIO 1SS355 3.Change PR75 and PR76 from S RES 1/16W 100K +-1% 0402 to S RES 1/16W 150K +-1% 0402 Change the CPU OTP circuit from active H to active L 4.Change PR73 from S RES 1/16W 15K +-1% 0402 to S RES 0.2 43 1/16W 16.9K +-1% 0402 5.Change PC56 from S CER CAP 22U 16V K X7R 0603 to S CER CAP 1U 16V K X7R 0805 6.Change PR74 from S RES 1/16W 3.4K +-1% 0402 to S S RES 1/16W 2.15K +-1% 0402 For cost down solution For cost down solution To cost down for RTC charge circuit 0.2 43 To prevent the KB-910 damag To prevent the KB-910 damag 0.2 40 To cost down for +1.5VP 0.2 43 1.Change the PD12 from DIO 1N4148 (SM) to DIO 1SS355 1.Delete the PD33 S ZEN DIO RLZ4.3B (LL-34) 0.2 DVT 0.2 DVT 1.Change the PD17 from SCH DIO SKS10-04AT TSMA to SCH DIO SKUL30-02AT THIN SMA For cost down solution To cost down for +1.5VP for +12VALWP circuit 0.2 40 1.Delete PR187 S RES 1/8W 2.7K +-5% 1206 S7 0.2 DVT For cost down solution To cost down for DDR 2.5V 0.2 41 1.Delete PR62 S RES 1/16W +-5% 0402 0.2 DVT For cost down solution To cost down for CPU_CORE 0.2 44 1.Delete PR127 and PR152 S RES 1/16W +-5% 0402 0.2 DVT For cost down solution To cost down for snubber circuit 0.2 40 0.2 DVT 10 0.2 DVT For cost down solution 0.2 DVT 1.Deete PR127 and PR152 S RES 1/16W +-5% 0402 2.Delete the PC161 S CER CAP 470P 100V K X7R 0805 39 0.2 1.Delete PC41,PC158 and PC159 S CER CAP 1U 25V K X7R 0603 40 To cost down for EMI capacitor 2.Delete PC40,PC73 and PC76 CER CAP 2200P 50V K X7R 0402 41 10 Don't has pull high resister on VGATE pin Add pull high resister on VGATE pin 0.2 44 Adjustment resistor divider 0.2 41 1.Add the S RES 1/16W 100K +-5% 0402 1.Change the PR60 from S RES 1/16W 681 +-1% 0402 to 10 11 VCCPP output voltage has error 0.2 S RES 1/16W 1.69K +-1% 0603 DVT 1.Change PL7 from 4.7UH_FDV0630-4.7UH_5.5A_20% Choke Rating not enough for +1.5VP Choke Rating not enough for +1.5VP 0.2 43 0.2 DVT to 4.7UH_D104C-919AS_4R7N_5.2A_20% 4 Compal Electronics, Inc Title PIR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D LA-2362 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Friday, March 11, 2005 Rev Sheet E 48 of 52 A B C D Page of Version change list (P.I.R List) m o c e u l b p o t p a l w W w Item 1 Fixed Issue Reason for change E Rev PG# Modify List B.Ver# Phase Don't has pull down resister on SHDN# Add pull down resister on SHDN# pin 0.2 39 1.Add PR193 the S RES 1/16W 100K +-5% 0402 0.2 DVT 0.2 DVT pin for charger Change the Vin Detector from LM393 to Change the Vin Detector from LM393 to charger ACOK# charger ACOK# 1.Add the PQ40 S TR DTC115EUA NPN (UMT3) 2.Delete the PR3,PR4,PR8 and PR9 RES 1/16W 10K +-1% 0402 3.Add the PR193,PR172 and PR173 RES 1/16W 100K +-5% 0402 4.Delete PR6 the S RES 1/16W 22K +-1% 0402 5.Delete PR1 the S RES 1/16W 1M +-1% 0402 6.Change PR182 from S RES 1/16W 150K +-1% 0402 to S 0.2 38,39 S RES 1/16W 20K +-1% 0402 7.Delete the PR7 S RES 1/16W 20K +-1% 0402 8.Delete the PR2 S RES 1/16W 84.5K +-1% 0402 9.Add the PR175 S RES 1/16W 158K +-1% 0402 10.Add the PR175 S RES 1/16W 681K +-1% 0402 11.Delete PC6 from 12 Delete PC5 from For ACIN pin, ACIN pin don't have connect to system 0.2 39 S CER CAP 1U 25V K X7R 0603 S CER CAP 1000P 50V +-10% X7R 0402 1.Add PR4 the 10K +-5% 0402 0.2 DVT 0.2 DVT 1.Change PU10 from S IC G965-18P1U SOP-8L REG to S IC APW7057KC-TR SOP-8 PWM 2.Add PR197 S RES 1/16W 12.7K +-1% 0402 3.Add the PQ44 S TR RHU002N06 1N SOT323 4.Delete PQ43 the S TR AO4912 2N SO8 W/D 5.Add PD33 the S DIO 1SS355 6.Add PR195 the S RES 1/16W 2.2 +-5% 0402 0.2 +1.8VSP power rating not enough 42 7.Add PR198 the S RES 1/16W 10K +-1% 0402 +1.8VSP power rating isnot enough 8.Add PR196 the S RES 1/16W 4.12K +-1% 0402 3 9.Add the PC167 the S CER CAP 4.7U 10V Z Y5V 0805 10.Add the PC164 S CER CAP 470P 50V +-10% X7R 0402 11.Add the PC163,PC165 and PC168 S CER CAP 1U 16V +-10% X7R 0402 12.Delete PC96 the S CER CAP 10U 6.3V K X7R 1206 13.Add the PC166 S POLY CAP 150U 6.3V M V(D2) T520 LESR 14.Add PL18 the S COIL 5.0UH +-20% TPRH6D38-5R0M-N 2.9A 1.Change PC50 from S POLY CAP 150U 6.3V M V(D2) T520 LESR to S POLY C 220U 4V M V(D2) T520 LESR VCCP's transients cannot meet spec For CPU_CORE's EMI, 0.2 41 VCCP's transients cannot meet spec For CPU_CORE's EMI, 2.Change PL6 from S COIL 4.7UH +-20% D104C-919AS-4R7M 5.2A to S COIL 1.8UH +-30% D104C-919AS-1R8N 9.5A 0.2 44 1.Change the PR125 and PR148 from S RES 1/16W +-5% 0402S to RES 1/16W +-5% 0402 0.2 DVT 0.2 DVT 4 Compal Electronics, Inc Title PIR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D LA-2362 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Friday, March 11, 2005 Rev Sheet E 49 of 52 A B C D Version change list (P.I.R List) m o c e u l b p o t p a l w W w Item Fixed Issue CPU's transients cannot meet spec Reason for change E Page of Rev PG# Add one current sense on phase 0.2 44 PACIN pin's high level is only 2.3V To adjust PACIN pin's level 0.2 39 The 5VALWP rising time is faster than PACIN's To delay timer of 5VALWP 0.3 40 The charge has error on change mode To adjust input and output current regulation loop compensation 0.3 39 Modify List B.Ver# 1.Delete PC124 and PC137 the S CER CAP 0.47U 16V +-10% X7R 0603 2.Delete PR134,PR141,PR155 and PR156 the S RES 1/16W 909+-1% 0402 3.Add PR134 S RES 1W 0.01 +-1%2512 Phase 0.2 DVT 0.2 DVT 0.3 DVT2 0.3 DVT2 1.Delete PR175 the S RES 1/16W 158K+-1% 0402 2.Change the PR172 from S RES 1/16W 100K +-1% 0402 S to RES 1/16W 10K +-1% 0402 1.Change the PR105 from S RES 1/16W 47K +-1% 0402 S to RES 1/16W 100K +-1% 0402 2.Change the PC91 from S CER CAP 047U 25V M X7R 0603 to CAP 1U 25V Z F Y5V 0805 1.Change PC152 and PC153 from the S CER CAP 0.01U 16V +-10% X7R to CER CAP 0.001U 16V +-10% X7R 2 42 For cost down solution 0.3 For cost down solution 1.Change PC58,PC68,PC95 and PC99 from the S CER CAP 4.7U 25V K X5R 1206 to CAP 4.7U 10V K X7R 0805 0.3 DVT2 43 The charger has EMI issue Add a resistor on charger's boost for EMI 0.3 39 1.Add the PR1 S RES 1/16W +-5% 0402 0.3 DVT2 Change the current limit's from sense DRC to resister To adjust current limit point for CPU_CORE 0.3 44 1.Change the PR142 from S RES 1/16W 200K +-5% 0402 to S RES 1/16W 470K +-5% 0402 0.3 DVT2 To preven in-rush current for B+ of MAX1902 To preven in-rush current for B+ of MAX1902 0.3 40 1.Add PR2 S RES 1/8W 33 +-5% 1206 0.3 DVT2 0.3 DVT2 1.Add PQ26 SB502060000 S TR RHU002N06 1N SOT323 2.Add PR134,PR141,PR155,PR156 S RES 1/16W 909 +-1% 0402 0.3 The CPU's dual choke will shortage 44 3.Delete PL14 S COIL 5UH +-30% CXZT1050-R50 28A Change to single choke 4.Add the PL14,PL15 S COIL 56UH +-20% ETQP4LR56 WFC 21A 5.Add the PC124,PC137 0.47U 16V +-10% X7R 0603 S8 3 4.Add the PL14,PL15 S COIL 56UH +-20% ETQP4LR56 WFC 21A 1.Delete the PU10 S IC APW7057KC-TR SOP-8 PWM 2.Delete the PQ43 S TR AO4912 2N SO8 W/D 3.Delete the PR188 S RES 1/16W +-5% 0402 4.Delete the PR195 S RES 1/16W 2.2 +-5% 0402 5.Delete the PR196 S RES 1/16W 4.12K +-1% 0402 6.Delete the PR198 S RES 1/16W 10K +-1% 0402 10 7.Delete the PR197 S RES 1/16W 12.7K +-1% 0402 Delete the +1.8VSP on M/B Delete the +1.8VSP on M/B 0.3 42 8.Delete the PL18 S COIL 5.0UH +-20% TPRH6D38-5R0M-N 2.9A 9.Delete the PC166 S POLY CAP 150U 6.3V M V(D2) T520 LESR 0.3 DVT2 10.Change the PC75 and PC87 from S CER CAP 4.7U 10V Z Y5V 0805 to S CER CAP 4.7U 6.3V +-10% X5R 0805 11.Delete PC95 S CER CAP 4.7U 10V Z Y5V 0805 12.Delete PC163,PC165,PC168 1U 16V +-10% X7R 0402 13.Delete PC164 S CER CAP 470P 50V +-10% X7R 0402 4 14.Delete PD33 S DIO 1SS355 Compal Electronics, Inc Title PIR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D LA-2362 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Friday, March 11, 2005 Rev Sheet E 50 of 52 A B C D Version change list (P.I.R List) m o c e u l b p o t p a l w W w Item 1 Fixed Issue Max1902 protect When power cord fast plug-out and plug-in Reason for change E Page of Rev PG# Modify List 1.Add PQ1 SB502060000 B.Ver# Phase S TR RHU002N06 1N SOT323 2.Add PQ2 S TR DTC115EUA NPN (UMT3) 3.Add PD2 S SCH DIO RB715F UMD3 4.Add PD1 S DIO 1N4148 (SM) 5.Add PR10,PR11,PR12 and PR13 S RES 1/4W 1.5K +-5% 1206 6.Add PR16 S RES 1/16W 100K +-1% 0402 7.Add PR17 and PR20 S RES 1/16W 499K +-1% 0402 0.3 38 Add the pre-chagre circuit 0.3 DVT2 8.Add PR19 S RES 1/16W 191K +-1% 0402 9.Add PR23 S RES 1/16W 34K +-1% 0402 10.Add PR26 S RES 1/16W 66.5K +-1% 0402 11.Add PR14 S RES 1/16W 2.2M +-5% 0402 12.Add PR24 S RES 1/16W 47K +-5% 0402 13.Add PC10 and PC12 S CER CAP 1000P 50V +-10% X7R 0402 14.Add PC11 S CER CAP 1U 25V K X7R 0603 2 The 5VALWP choke rating is not enough TP0610T will EOL Change the choke 0.3 40 1.Change the PL9 from S COIL 10UH +-30% SDT-1050P-100118 3.5A to S COIL 10uH +-20% SDT-1205P-100-118 0.3 DVT2 Change the part 0.3 43 1.Change the PQ16 S TR TP0610T 1P SOT-23 to.S TR TP0610K 1P SOT-23 0.3 DVT2 3 4 Compal Electronics, Inc Title PIR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D LA-2362 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Friday, March 11, 2005 Rev Sheet E 51 of 52 A B C D Version change list (P.I.R List) m o c e u l b p o t p a l w W w Item Fixed Issue Reason for change E Page of Rev PG# Modify List B.Ver# Phase To adjust sequence for +5VALWP and +3VALWP To adjust sequence for +5VALWP and +3VALWP LA-2362-0.2 41 1.Change PC90 from 47U 16V X7R 0603 to 2.2U 10V X5R 0805 LA-2362-0.2 DVT3 Change the pull-high resistor for VGTE pin For HW request LA-2362-0.2 45 1.Change PR122 from 100K 0402 to 10K 0402 The system has re-boot issue when running the 3D mark The HW has noise by interference from B+ LA-2362-0.2 42 The CPU's B+ has nosie issue when system into C3/C4 The CPU's B+ has nosie issue when system into C3/C4 LA-2362-0.2 To cost down for 150uf/6.3V To cost down for 150uf/6.3V LA-2362-0.2 41,45 Change the IC solution from ISL6227 to MAX8743 for +2.5V and +VCCPP The ISL6227 has shut down issue when windows idle LA-2362-0.2 42 LA-2362-0.2 DVT3 1.Add the PL3 FBL-18-453215-900LM90T_1812 LA-2362-0.2 DVT3 2.Add the PC35 and PC41 0.1U 25V X7R 0603, 45 1.Add the PC14 220U 25V LA-2362-0.2 DVT3 1.Change the vendor form KEMET to EPCOS LA-2362-0.2 DVT3 LA-2362-0.2 DVT3 2 3 4 Compal Electronics, Inc Title PIR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D LA-2362 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Friday, March 11, 2005 Rev Sheet E 52 of 52 m o c e u l b p o t p a l w W w ... EE_DOUT EE_DIN F12 LAN_CLK AA3 AA5 LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LAN AA2 P2 N3 N5 N4 B11 LAN_RSTSYNC E12 E11 C13 LANRXD[0] LANRXD[1] LANRXD[2] C12 C11 E13 LANTXD[0] LANTXD[1] LANTXD[2] @ C400... LAN_TX3+ D LAN_TX3C3741 TCT1 TD1+ LAN_TX3- V_DAC LAN_TX2+ LAN_TX2- LAN_TX2- V_DAC LAN_RX1+ 0.1U_0402_16V4Z LAN_RX1+ LAN_RX1- LAN_RX1C3701 0.1U_0402_16V4Z 2@ LAN_TX2+... 115 114 113 NC/MDI2+ NC/MDI2NC/MDI3+ NC/MDI3- LAN_TX0+ LAN_TX0LAN_RX1+ LAN_RX1- 14 15 18 19 LAN_TX2+ LAN_TX2LAN_TX3+ LAN_TX3- X1 X2 121 122 LWAKE ISOLATE# RTSET NC/SMBCLK NC/SMBDATA 105 23 127