Acer aspire 4735z 4736z 4935z 4936z COMPAL LA 5272p KALG1 REV 0 1sec

A B C D E 1 Compal Confidential KALG1- M/B Schematics Document 2 Intel Penryn Processor with Cantiga + DDRII + ICH9M 2009-04-17 REV 01 3 4 2008/11/10 Issued Date hexainf@hotmail.com GRATIS - FOR FREE A Compal Electronics, Inc Compal Secret Data Security Classification 2008/11/24 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Cover Page Rev 0.1 KALG1- Date: B C D Friday, April 24, 2009 Sheet E of 45 A B C D E Compal Confidential Model Name : KALG1File Name : LA-XXXXP Intel Penryn Processor Fan Control Thermal Sensor Clock Generator EMC 1402 ICS9LPRS387 page uPGA-478 Package (Socket P) page LCD Conn page 24 page 16 4,5,6 FSB 667/800/1066MHz H_A#(3 35) HDMI Conn page H_D#(0 63) CRT Conn page 17 TMDS page 18 LVDS HDMI ASM1442T Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2 Intel Cantiga LVDS Dual Channel 1.8V DDRII 667/800 uFCBGA-1329 PCI-Express page 14,15 BANK 0, 1, 2, page 7,8,9,10,11,12,13 page 24 DMI USB conn x3 C-Link USB port 0, 1, page 29 PCI-Express Intel ICH9-M 3.3V 48MHz Bluetooth Conn LAN(GbE) MINI Card x1 ATHEROS AR8131 AES1610 NEW Card page 29 USB HD Audio BGA-676 Card Reader RTS5159-GR page 20,21,22,23 page 25 WLAN ESATA Conn page 29 CDROM Conn page 23 GMCH HDA port RJ45 page 27 page 28 port page 28 port page 26 Finger Print page 17 page 29 3.3V 24.576MHz/48Mhz S-ATA LS-4494P CMOS Camera page 08 MDC 1.5 Conn page 32 SATA HDD Conn page 23 HDA Codec ALC888S-VC page 33 Audio AMP APA2051 page 34 LPC BUS Phone Jack x3 ENE KB926 page 34 page 30 RTC CKT page 20 Int.KBD Touch Pad page 31 page 31 Power On/Off CKT page 32 DC/DC Interface CKT page 37 BIOS CIR page 31 page 30 4 Power Circuit DC/DC page 38,39,40,41,42,43 2008/11/10 Issued Date POWER SW Compal Electronics, Inc Compal Secret Data Security Classification 2008/11/24 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Page 36 Date: A B C D Block Diagrams Document Number Rev 0.1 KALG1Friday, April 24, 2009 Sheet E of 45 A B C D SIGNAL STATE Voltage Rails Full ON E SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock HIGH HIGH HIGH HIGH ON ON ON ON S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF N/A N/A S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF Power Plane Description S1 S3 VIN Adapter power supply (19V) N/A B+ AC or battery power rail for power circuit N/A +CPU_CORE Core voltage for CPU ON OFF OFF +0.75VS 0.75VS power rail for DDR3 terminator ON OFF OFF +1.05VS 1.05V switched power rail ON OFF OFF +1.5V 1.5V power rail for HDA ON ON OFF +1.5VS 1.5V switched power rail ON OFF OFF +1.8V 1.8V power rail for NB(LVDS) ON ON OFF +3VALW 3.3V always on power rail ON ON ON* Vcc Ra/Rc/Re +3V_LAN 3.3V power rail for LAN ON ON ON Board ID +3V 3.3V power rail for SB ON ON OFF +3VS 3.3V switched power rail ON OFF OFF +5VALW 5V always on power rail ON ON ON* +5V 5V power rail for SB ON ON OFF +5VS 5V switched power rail ON OFF OFF +VSB VSB always on power rail ON ON ON* +RTCVCC RTC power ON ON ON Board ID / SKU ID Table for AD channel 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf V AD_BID V V AD_BID typ V V AD_BID max V Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF BOARD ID Table Board ID External PCI Devices Device IDSEL# EC SM Bus1 address Device Address Smart Battery 0001 011X b REQ#/GNT# Interrupts EC SM Bus2 address Device BTO Option Table BTO Item GL40 GM45 Address 1001 100X b EMC1402 PCB Revision PCB 08Y LA-5271P REV1 M/B BOM Structure GL40@ GM45@ BOM Configuration Table Project KALG1_GM45 KALG1_GL40 KAL90+_GL40 KAL90+_GM45 KALH0+_GL40 KALH0+_GM45 ICH9M SM Bus address Device Address Clock Generator (ICS9LPRS387, SLG8SP556V) 1101 001Xb DDR2 DIMMA 1001 000Xb DDR2 DIMMB 1001 010Xb BOM Configuration GM45@/KALG1@/KAL90_G0_90+@ GL40@/KALG1@/KAL90_G0_90+@ GL40@/KAL90_H0_90+@/KAL90_90+@/KAL90_G0_90+@ GM45@/KAL90_H0_90+@/KAL90_90+@/KAL90_G0_90+@ GL40@/KAL90_H0_90+@/KALH0@ GM45@/KAL90_H0_90+@/KALH0@ 4 2008/11/10 Issued Date hexainf@hotmail.com GRATIS - FOR FREE A Compal Electronics, Inc Compal Secret Data Security Classification 2008/11/24 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: B C D Notes List Document Number Rev 0.1 KALG1Friday, April 24, 2009 Sheet E of 45 [7] H_A#[3 35] H_A#[3 35] H_REQ#[0 4] [7] H_REQ#[0 4] [7] H_RS#[0 2] H_RS#[0 2] FAN1 Conn +5VS JCPU1A A20M# FERR# IGNNE# [20] [20] [20] [20] H_STPCLK# H_INTR H_NMI H_SMI# D5 C6 B4 A3 STPCLK# LINT0 LINT1 SMI# RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] IERR# INIT# D20 B3 C1 F3 F4 G3 G2 HIT# HITM# G6 E4 EN_DFAN1 H_IERR# H_INIT# [20] 0.1U_0402_16V4Z H_LOCK# [7] H_RESET# H_RS#0 H_RS#1 H_RS#2 +VCC_FAN1 R43 300_0402_5% D16 1SS355_SOD323-2 GND GND GND GND [7] H_HIT# H_HITM# [7] [7] BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 XDP_BPM#5 XDP_TCK XDP_TDI PROCHOT# THERMDA THERMDC D21 A24 B25 H_PROCHOT# H_THERMDA H_THERMDC THERMTRIP# BAS16_SOT23-3 C88 10U_0805_10V4Z 2 H_RESET# [7] H_TRDY# D15 APL5605KI-TRL SOP 8P C73 +3VS C82 1000P_0402_50V7K H4 [30] VEN VIN VO VSET R46 10K_0402_5% 40mil LOCK# RESET# RS[0]# RS[1]# RS[2]# TRDY# [7] JP27 +VCC_FAN1 [30] FAN_SPEED1 +1.05VS XDP_TMS XDP_TRST# XDP_DBRESET# C83 1000P_0402_50V7K ACES_85205-03001 CONN@ XDP_DBRESET# [21] C7 H_THERMTRIP# [8,20] A22 A21 CLK_CPU_BCLK [16] CLK_CPU_BCLK# [16] OCP# [21] Q5 MMBT3904_SOT23-3 @ +1.05VS XDP_TDI R108 54.9_0402_1% XDP_TMS R109 54.9_0402_1% XDP_BPM#5 R117 54.9_0402_1% H_PROCHOT# R53 56_0402_5% H_IERR# R52 56_0402_5% XDP_TRST# R107 54.9_0402_1% XDP_TCK R116 54.9_0402_1% H CLK BCLK[0] BCLK[1] C R48 @ 56_0402_5% THERMAL ICH B ADDR GROUP_1 M4 N5 T2 V3 B2 D2 D22 D3 F6 H_BR0# U4 A6 A5 C4 F1 D H_A20M# H_FERR# H_IGNNE# H_DEFER# [7] H_DRDY# [7] H_DBSY# [7] +5VS 10U_0805_10V4Z C [20] [20] [20] A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# H5 F21 E1 [7] [7] [7] E H_ADSTB#1 [7] CONTROL REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 C BR0# H_ADS# H_BNR# H_BPRI# B H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 K3 H2 K2 J3 L1 DEFER# DRDY# DBSY# C81 H1 E2 G5 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 ADS# BNR# BPRI# XDP/ITP SIGNALS H_ADSTB#0 A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# RESERVED [7] J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 ADDR GROUP_0 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 D left NC if no ITP @ 39Ohm Layout Note: H_THERMDA&H_THERMDC Trace / Space = 10 / 10 mil Penryn CONN@ B +3VS C90 0.1U_0402_16V4Z U5 H_THERMDA C92 2200P_0402_50V7K BSEL2 BSEL1 BSEL0 BCLK 0 266 200 1 166 H_THERMDC A VDD SMCLK DP SMDATA DN ALERT# THERM# GND EC_SMB_DA2 [30,31] R49 10K_0402_5% +3VS A EMC1402-1-ACZL-TR_MSOP8 Compal Electronics, Inc Compal Secret Data Security Classification 2008/11/10 Issued Date Deciphered Date 2008/11/24 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC EC_SMB_CK2 [30,31] Title Penryn (1/3) & FAN Conn Size B Date: Document Number Rev 0.1 KALG1Friday, April 24, 2009 Sheet of 45 H_D#[0 63] H_D#[0 63] [7] [7] [7] H_DSTBN#0 H_DSTBP#0 H_DINV#0 C +1.05VS R385 1K_0402_1% R386 2K_0402_1% R54 R55 H_DSTBN#1 H_DSTBP#1 H_DINV#1 2 C457 @ @ @ 1 T28 T31 GTL_REF0 1K_0402_5% TEST1 1K_0402_5% TEST2 @ TEST3 PAD 0.1U_0402_16V4Z TEST4 @ TEST5 PAD Width=4 mil , Spacing: 15mil (55Ohm) Trace Close CPU < 0.5' [7] [7] [7] [16] CPU_BSEL0 [16] CPU_BSEL1 [16] CPU_BSEL2 D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# AD26 C23 D25 C24 AF26 AF1 A26 C3 B22 B23 C21 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2] Penryn MISC D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 DATA GRP N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 DATA GRP H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# DATA GRP D E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 DATA GRP H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 JCPU1C [7] +CPU_CORE JCPU1B COMP[0] COMP[1] COMP[2] COMP[3] R26 U26 AA1 Y1 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# E5 B5 D24 D6 D7 AE6 H_DSTBN#2 [7] H_DSTBP#2 [7] H_DINV#2 [7] H_DSTBN#3 [7] H_DSTBP#3 [7] H_DINV#3 [7] COMP0 COMP1 COMP2 COMP3 R51 R50 R105 R106 1 1 H_PW RGOOD H_CPUSLP# 2 2 27.4_0402_1% 54.9_0402_1% 27.4_0402_1% 54.9_0402_1% H_DPRSTP# [8,20,43] H_DPSLP# [20] H_DPW R# [7] H_PW RGOOD [20] H_CPUSLP# [7] PSI# [43] CONN@ TRACE CLOSELY CPU < 0.5' COMP0, COMP2 layout : Width 16mils and Space 25mils (27.4Ohms) COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms) B A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067] Penryn VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 VCCA[01] VCCA[02] B26 C26 VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] AD6 AF5 AE5 AF4 AE3 AF3 AE2 VCCSENSE AF7 VCCSENSE VSSSENSE AE7 VSSSENSE +CPU_CORE D C +1.05VS 20mils +1.5VS CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 R88 C426 [43] [43] [43]0.01U_0402_16V7K 2 [43] [43] 10U_0805_10V4Z [43] [43] 100_0402_1% B +CPU_CORE VCCSENSE [43] VSSSENSE [43] CONN@ R89 C425 100_0402_1% A A 2008/11/10 Issued Date hexainf@hotmail.com GRATIS - FOR FREE Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2008/11/24 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Penryn (2/3) Size B Date: Document Number Rev 0.1 KALG1Friday, April 24, 2009 Sheet of 45 JCPU1D + C145 900P_PFAF250E128MNTTE_2.5VM +CPU_CORE C447 C448 C428 C429 10U_0805_6.3V6M 10U_0805_6.3V6M C446 10U_0805_6.3V6M 10U_0805_6.3V6M C445 10U_0805_6.3V6M 10U_0805_6.3V6M C C430 C431 B +1.05VS CONN@ C444 C440 2 C427 C449 C441 0.1U_0402_16V4Z C182 0.1U_0402_16V4Z 330U_D2_2.5VY_R9M A + 0.1U_0402_16V4Z 0.1U_0402_16V4Z Penryn D 0.1U_0402_16V4Z B +CPU_CORE 0.1U_0402_16V4Z C P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25 VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] 10U_0805_6.3V6M D VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] 10U_0805_6.3V6M A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 C432 A Compal Electronics, Inc Compal Secret Data Security Classification 2008/11/10 Issued Date Deciphered Date 2008/11/24 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Penryn (3/3) Size B Date: Document Number Rev 0.1 KALG1Friday, April 24, 2009 Sheet of 45 [5] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 C +1.05VS R349 221_0402_1% B H_SW ING H_RCOMP F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6 C5 E3 R351 24.9_0402_1% [4] [5] H_RESET# H_CPUSLP# H_RESET# H_CPUSLP# C12 E11 H_AVREF A11 B11 width:spacing=10mil:20mil (