A B C D E Compal Confidential Model Name : P5WE0 File Name : LA-6901P BOM P/N:43 p su /x / Compal Confidential 2 yc om P5WE0 M/B Schematics Document // m Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH Nvidia N12P GS/GV 2010-08-11 REV:0.1 h tt p: 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/08/11 2011/08/11 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Cover Page Size Document Number Custom Rev 0.1 P5WE0 M/B LA-6901P Schematic Date: Sheet Friday, August 27, 2010 E of 59 A B C D E Fan Control page 38 1 PEG(DIS) 100MHz PCI-E 2.0x16 5GT/s PER LANE Nvidia N12P GS/GV Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2 Dual Channel Intel Sandy Bridge 133MHz page 12,13 BANK 0, 1, 2, 1.5V DDRIII 1066/1333 Processor page23~31 rPGA989 HDMI Conn FDI x8 LVDS Conn CRT Conn page 32 page 33 page 34 LVDS(DIS) DMI x4 100MHz 100MHz 2.7GT/s 1GB/s x4 LVDS(UMA/OPTIMUS) CRT(UMA/OPTIMUS) TMDS(UMA/OPTIMUS) Intel Cougar Point-M port 2,3 LAN(GbE) & Card Reader MINI Card x2 USB 3.0 conn x1 WLAN, WWAN BCM57785 USB port 12,13 page 38 page 45 SATA x (GEN1 1.5GT/S ,GEN2 3GT/S) port page 36 RJ45 page 37 37 USBx14 3.3V 48MHz HD Audio 3.3V 24MHz page 32 page 43 SPI SPI ROM x1 Int Speaker Phone Jack x page 44 LPC BUS 33MHz ENE KB930 page 40 CPU XDP Touch Pad Int.KBD page 41 LS-6902P USB port 9,12 on 3G/B page 32 HDA Codec FPC for USB3.0 page 14 Power On/Off CKT 35 h RTC CKT USB port 10 page 39 page 44 LF-6901P USB 2.0/B 2Port USB Port0,1 page 39 USB port 13 page 14 SATA CDROM Conn page 35 tt Sub-board LS-6901P USB port 0,1 on USB/B page 39 3G connector ALC271X/277X page 14~22 p: Card Reader Conn page CMOS Camera port port 0,1 SATA HDD Conn page Bluetooth Conn 989pin BGA // m port 100MHz yc om PCH 100MHz PCI-Express x (ARD PCIE2.0 2.5GT/s) USB 2.0 conn x2 p su CRT(DIS) /x / page 5~11 HDMI(DIS) page page 41 PWR/B PCH XDP page 42 page 39 BIOS ROM DC/DC Interface CKT page 46 page 14 page 40 LS-6903P 3G/B page 41 Power Circuit DC/DC page 48~56 LS-6904P USB 3.0 /B port as USB3.0 port as USB2.0 Issued Date 2010/08/11 2011/08/11 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC page 41 A Compal Electronics, Inc Compal Secret Data Security Classification B C D Title Block Diagrams Size Document Number Custom P5WE0 M/B LA-6901P Schematic Date: Sheet Friday, August 27, 2010 E of 59 Rev 0.1 A B C D Voltage Rails SIGNAL S1 S3 S5 VIN Adapter power supply (19V) N/A N/A N/A BATT+ Battery power supply (12.6V) N/A N/A N/A B+ AC or battery power rail for power circuit N/A N/A N/A +CPU_CORE Core voltage for CPU ON OFF OFF +VGA_CORE Core voltage for GPU ON OFF OFF +VGFX_CORE Core voltage for UMA graphic ON OFF OFF +0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF +1.05VSDGPU +1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU ON OFF OFF +VALW +V +VS Clock HIGH HIGH HIGH HIGH ON ON ON ON S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF +1.05VS_VTT +1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU ON OFF OFF +1.05VS_VCCP to +1.05VS_PCH power for PCH ON OFF OFF +1.5V +1.5VP to +1.5V power rail for DDRIII ON ON OFF +1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF Vcc Ra/Rc/Re +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF Board ID (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON OFF OFF +1.8VSDGPU +1.8VS to +1.8VSDGPU switched power rail for GPU ON OFF OFF +3VALW +3VALW always on power rail ON ON ON* +3VALW_EC +3VALW always to KBC ON ON ON* +3V_LAN +3VALW to +3V_LAN power rail for LAN ON ON ON* +3VALW to +3VALW_PCH power rail for PCH (Short Jumper) ON ON ON* +3VALW to +3VS power rail ON OFF OFF +5VALW +5VALWP to +5VALW power rail ON ON ON* +5VALW_PCH +5VALW to +5VALW_PCH power rail for PCH (Short resister) ON ON ON* +5VS +5VALW to +5VS switched power rail ON OFF OFF +VSB +VSBP to +VSB always on power rail for sequence control ON ON ON* +RTCVCC RTC power ON ON ON EC SM Bus1 address Address Smart Battery 0001 011X b EC SM Bus2 address Address Device PCH SM Bus address 1101 0010b 1001 000Xb DDR DIMM2 1001 010Xb 3G & BT & USB30 & USB20 Config USB30 SKU: USB30@ 3G SKU: 3G@ BT SKU: BT@ USB20 SKU: USB20@ LAN Chip A0 version: A0@ LAN chip B0 Version: B0@ Board ID OPTMIUS SKU: OPT@ Non-OPTMIUS SKU: NOPT@ UHCI0 UHCI1 EHCI1 UHCI3 X76***BOL01: Samsung X76***BOL02: Hynix VRAM P/N : Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P) Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V ) UHCI4 EHCI2 UHCI5 UHCI6 10 11 12 13 External USB Port USB/B (Right Side) USB/B (Right Side) USB 2.0 & USB3.0 Conn BTO Item UMA Only UMA with OPTIMUS Dis with OPTIMUS DIS Only OPTIMUS Non-OPTIMUS 3G Blue Tooth USB2.0 USB3.0 VRAM Connector Unpop LAN Chip A0 version LAN Chip B0 version 2010/08/11 B C BOM Structure UMAO@ UMA@ DIS@ DISO@ OPT@ NOPT@ 3G@ BT@ USB20@ USB30@ X76@ CONN@ @ A0@ B0@ Compal Electronics, Inc 2011/08/11 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A EVT DVT PVT Pre-MP Mini Card 1(WLAN) 3G/B(WWAN) Camera Mini Card 2(Reserved) SIM Card (3G/B) Blue Tooth Compal Secret Data Security Classification Issued Date V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V BTO Option Table PCB Revision 0.1 0.2 0.3 1.0 USB 2.0 USB 1.1 Port UHCI2 BOM Config BT@/3G@/USB30@/UMA@/UMAO@/NOPT@/A0@ UMA Only: BT@/3G@/USB30@/UMA@/DIS@/X76@/OPT@/A0@ OPTIMUS: BT@/3G@/USB30@/DISO@/DIS@/X76@/NOPT@/A0@ DIS Only: VRAM BOM Config V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V USB Port Table tt Clock Generator (9LVS3199AKLFT, RTM890N-631-VB-GRT) DDR DIMM0 p: Address h Device V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V BOARD ID Table // m Device 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC p su +1.5VSDGPU +3VALW_PCH Board ID / SKU ID Table for AD channel +1.8VS +3VS SLP_S1# SLP_S3# SLP_S4# SLP_S5# Full ON +1.05VS_PCH Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF STATE yc om Description /x / Power Plane E D Title Notes List Size Document Number Custom P5WE0 M/B LA-6901P Schematic Date: Sheet Friday, August 27, 2010 E of 59 Rev 0.1 +1.05VS_VTT R517 24.9_0402_1% G21 E22 F21 D21 DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] 15 15 15 15 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 G22 D22 F20 C21 DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] 15 15 15 15 15 15 15 15 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 A21 H19 E19 F18 B21 C20 D18 E17 FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] 15 15 15 15 15 15 15 15 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 A22 G19 E20 G18 B20 C19 D19 F17 FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] 15 FDI_FSYNC0 15 FDI_FSYNC1 J18 J17 FDI0_FSYNC FDI1_FSYNC 15 FDI_INT H20 FDI_INT 15 FDI_LSYNC0 15 FDI_LSYNC1 J19 H17 FDI0_LSYNC FDI1_LSYNC A18 A17 B16 eDP_COMPIO eDP_ICOMPO eDP_HPD EDP_COMP p: B // m R145 24.9_0402_1% eDP_AUX eDP_AUX# C17 F16 C16 G15 eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3] C18 E16 D16 F15 eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3] h tt C15 D15 PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] J22 J21 H22 PEG_COMP K33PEG_GTX_C_HRX_N15 M35PEG_GTX_C_HRX_N14 L34PEG_GTX_C_HRX_N13 J35PEG_GTX_C_HRX_N12 PEG_GTX_C_HRX_N11 J32 PEG_GTX_C_HRX_N10 H34 PEG_GTX_C_HRX_N9 H31 PEG_GTX_C_HRX_N8 G33 PEG_GTX_C_HRX_N7 G30 PEG_GTX_C_HRX_N6 F35 PEG_GTX_C_HRX_N5 E34PEG_GTX_C_HRX_N4 E32PEG_GTX_C_HRX_N3 D33PEG_GTX_C_HRX_N2 D31PEG_GTX_C_HRX_N1 B33PEG_GTX_C_HRX_N0 C32 PEG_GTX_C_HRX_P15 J33 PEG_GTX_C_HRX_P14 L35PEG_GTX_C_HRX_P13 K34PEG_GTX_C_HRX_P12 H35PEG_GTX_C_HRX_P11 H32PEG_GTX_C_HRX_P10 G34PEG_GTX_C_HRX_P9 G31PEG_GTX_C_HRX_P8 F33PEG_GTX_C_HRX_P7 F30PEG_GTX_C_HRX_P6 E35PEG_GTX_C_HRX_P5 E33PEG_GTX_C_HRX_P4 F32PEG_GTX_C_HRX_P3 D34PEG_GTX_C_HRX_P2 E31PEG_GTX_C_HRX_P1 C33PEG_GTX_C_HRX_P0 B32 PEG_HTX_GRX_N15 M29PEG_HTX_GRX_N14 M32PEG_HTX_GRX_N13 M31PEG_HTX_GRX_N12 L32 PEG_HTX_GRX_N11 L29 PEG_HTX_GRX_N10 K31PEG_HTX_GRX_N9 K28PEG_HTX_GRX_N8 J30 PEG_HTX_GRX_N7 J28 PEG_HTX_GRX_N6 H29PEG_HTX_GRX_N5 G27PEG_HTX_GRX_N4 E29PEG_HTX_GRX_N3 F27PEG_HTX_GRX_N2 D28PEG_HTX_GRX_N1 F26PEG_HTX_GRX_N0 E25 PEG_HTX_GRX_P15 M28PEG_HTX_GRX_P14 M33PEG_HTX_GRX_P13 M30PEG_HTX_GRX_P12 L31 PEG_HTX_GRX_P11 L28 PEG_HTX_GRX_P10 K30PEG_HTX_GRX_P9 K27PEG_HTX_GRX_P8 J29 PEG_HTX_GRX_P7 J27 PEG_HTX_GRX_P6 H28PEG_HTX_GRX_P5 G28PEG_HTX_GRX_P4 E28PEG_HTX_GRX_P3 F28PEG_HTX_GRX_P2 D27PEG_HTX_GRX_P1 E26PEG_HTX_GRX_P0 D25 p su DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] yc om 15 15 15 15 PCI EXPRESS* - GRAPHICS DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] DMI B28 B26 A24 B23 Intel(R) FDI DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 eDP_COMPIO and ICOMPO signals should be shorted near balls, Trace Width for EDP_COMPIO=4mils, EDP_ICOMPO=12mils, and both length less than 500 mils should not be left floating ,even if disable eDP function 15 15 15 15 DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] +1.05VS_VTT DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] eDP C 15 15 15 15 B27 B25 A25 B24 Sandy Bridge_rPGA_Rev0p61 CONN@ PEG_ICOMPI and PEG_RCOMPO signals should be shorted and routed, max length = 500 mils,trace width=4mils PEG_ICOMPO signals should be routed with - max length = 500 mils,trace width=12mils spacing =15mils C46 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N15 PEG_GTX_HRX_N14 C49 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N13 C51 DIS@ 0.22U_0402_10V6K C53 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N12 PEG_GTX_HRX_N11 C60 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N10 C71 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N9 C75 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_N8 C82 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_N7 C92 DIS@ 0.22U_0402_10V6K C93 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N6 PEG_GTX_HRX_N5 C102 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_N4 C111 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_N3 C113 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N2 C125 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N1 C129 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_N0 C144 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P15 C47 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_P14 C50 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_P13 C52 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_P12 C56 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_P11 C66 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P10 C68 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P9 C81 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P8 C86 PEG_GTX_HRX_P7 DIS@ 0.22U_0402_10V6K C89 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_P6 C100 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P5 C105 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_P4 PEG_GTX_HRX_P3 C106 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P2 C117 DIS@ 0.22U_0402_10V6K C119 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_P1 C135 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_P0 C138 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N15 C516 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N14 C520 1 DIS@ 0.22U_0402_10V6K C529 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_N12 C534 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N11 C538 PEG_HTX_C_GRX_N10 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N9 C540 DIS@ 0.22U_0402_10V6K C542 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N8 C544 2DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N7 C546 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N6 C548 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N5 C550 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N4 C552 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N3 PEG_HTX_C_GRX_N2 C554 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N1 C556 DIS@ 0.22U_0402_10V6K C558 DIS@ 0.22U_0402_10V6K 1 2 PEG_HTX_C_GRX_N0 C560 DIS@ 0.22U_0402_10V6K D PEG_GTX_HRX_N[0 15] 22 PEG_GTX_HRX_P[0 15] 22 PEG_HTX_C_GRX_N[0 15] 22 PEG_HTX_C_GRX_P[0 15] 22 /x / D JCPU1A C PEG_HTX_C_GRX_P15 DIS@ 0.22U_0402_10V6KPEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_P13 0.22U_0402_10V6K 0.22U_0402_10V6K DIS@ DIS@ PEG_HTX_C_GRX_P12 C536 DIS@ 0.22U_0402_10V6KPEG_HTX_C_GRX_P11 C539 1 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_P9 C541 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P8 C543 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P7 C545 DIS@ 0.22U_0402_10V6K C547 2DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P6 PEG_HTX_C_GRX_P5 C549 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P4 C553 0.22U_0402_10V6K C551 0.22U_0402_10V6K 1 DIS@ DIS@ PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_P2 C555 DIS@ 0.22U_0402_10V6K C557 DIS@ 0.22U_0402_10V6KPEG_HTX_C_GRX_P1 C559 DIS@ 0.22U_0402_10V6KPEG_HTX_C_GRX_P0 C561 DIS@ 0.22U_0402_10V6K C515 C528 C533 1 B Typ- suggest 220nF The change in AC capacitor value from 100nF to 220nF is to enable compatibility with future platforms having PCIE Gen3 (8GT/s) A A Compal Secret Data Security Classification 2010/08/11 Issued Date Deciphered Date 2011/08/11 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PROCESSOR(1/7) DMI,FDI,PEG Size Document Number Custom Rev 0.1 P5WE0 M/B LA-6901P Schematic Date: Friday, August 27, 2010 Sheet of 59 +1.05VS_VTT +1.05VS_VTT +1.05VS_VTT @ JXDP1 R59 4.7K_0402_5% H_CPUPWRGD SMB_CLK_S3 R54 R55 15,39 PBTN_OUT# +3VS CFG0 SYS_PWROK CFG0 R56 R57 @ @ 1 @ @ 1 1K_0402_5% 0_0402_5% H_CPUPWRGD_XDP CFD_PWRBTN#_XDP 1K_0402_5% 0_0402_5% XDP_HOOK2 SYS_PWROK_XDP SMB_DATA_S3 SMB_CLK_S3 Q6B DMN66D0LDW-7_SOT363-6 @ XDP_TCK SNB_IVB# had changed the name to PROC_SELCT#,function for future platform, connect to the DF_TVS strap on the PCH C JCPU1B C26 17 H_SNB_IVB# T6 Processor Pullups R84 H_CPUPWRGD_R 10K_0402_5% +1.05VS_VTT 18,39 R91 @ R93 0_0402_5% H_PECI 62_0402_5% H_PROCHOT# 39,49 H_PROCHOT# R97 0_0402_5% H_THEMTRIP#_R +3VS +1.05VS_VTT C162 0.1U_0402_16V4Z A RESET#: ᣦ SN74LVC1G07DCKR_SC70-5 @ R88 0_0402_1% ƮἜᢃOK UNCOREPWRGOOD: CORE PECI AL32 AN32 PROCHOT# PM_DRAM_PWRGD_R AP33 V8 +3VS XDP_DBRESET# CLK_CPU_ITP CLK_CPU_ITP# @ 1K_0402_5% PLT_RST# 17,35,38,39,45 C BCLK BCLK# A28 A27 DPLL_REF_SSCLK DPLL_REF_SSCLK# A16 A15 SM_DRAMRST# SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] R8 AK1 A5 A4 PM_SYNC UNCOREPWRGOOD SM_DRAMPWROK RESET# CLK_CPU_DMI CLK_CPU_DMI# R516 R518 CLK_CPU_DMI 14 CLK_CPU_DMI# 14 1K_0402_5% 1K_0402_5% SM_DRAMRST# SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST# R231 140_0402_1% R566 R571 25.5_0402_1% 200_0402_1% DDR3 Compensation Signals PU/PD for JTAG signals TCK TMS TRST# TDI TDO DBR# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] 0_0402_5% @ 1R80 @ 1R83 0_0402_5% XDP_PRDY#_R AP29XDP_PREQ#_R AP27 XDP_TCK AR26 XDP_TMS AR27 XDP_TRST# AP30 XDP_TDI_R AR28 XDP_TDO_R AP26 AL35 AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32 XDP_TMS XDP_PRDY# XDP_PREQ# XDP_TDI_R R106 R99 +1.05VS_VTT 51_0402_5% 51_0402_5% XDP_TDO ESD request 2010/07/27 R105 51_0402_5% B XDP_TCK R100 R110 XDP_TDI 0_0402_5%XDP_TDO 0_0402_5% R101 0_0402_5% XDP_TRST# R95 XDP_DBRESET# DBRESET#_R XDP_BPM#0_R XDP_BPM#1_R XDP_BPM#2_R XDP_BPM#3_R XDP_BPM#4_R XDP_BPM#5_R XDP_BPM#6_R XDP_BPM#7_R 0_0402_5% @ R111 51_0402_5% 51_0402_5% XDP_DBRESET# 15 XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7 R79 0_0402_5% @ R75 0_0402_5% @ @ R73 0_0402_5% 1R66 0_0402_5%2 @ @ 1R51R62 0_0402_5% 0_0402_5% @@ R52 0_0402_5% 1R53 Sandy Bridge_rPGA_Rev0p61 CONN@ 1 R205 B O A 2 0_0402_1% R203 39_0402_1% A PM_DRAM_PWRGD_R R204 G 200_0402_5% 15 SYS_PWROK U11 74AHC1G09GW_TSSOP5 PM_SYS_PWRGD_BUF P A @ Compal Secret Data Security Classification Issued Date 2010/08/11 2011/08/11 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC If use External Graphic or use integrated without eDP DPLL_REF_SSCLK PD 1K_5% to GND DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT +1.05VS_VTT ESD request 2010/07/27 +1.5V_CPU_VDDQ 15 PM_DRAM_PWRGD 1K_0402_5% XDP_TDO XDP_TRST# XDP_TDI XDP_TMS +3VALW C307 0.1U_0402_16V4Z R40 CLK_CPU_ITP 14 CLK_CPU_ITP# 14 XDP_RST#_R R39 XDP_DBRESET# PRDY# PREQ# BUF_CPU_RST# AR33 D THERMTRIP# SM_DRAMPWROK:DRAM power ok ኅokࠤCPU reset p: BUFO_CPU_RST# AN33 AM34 R81 0_0402_5% H_CPUPWRGD_R h Y CATERR# H_PM_SYNC_R tt P U7 NC R64 2 0_0402_5% 18 H_CPUPWRGD R87 43_0402_1% BUF_CPU_RST# G PLT_RST# R90 75_0402_5% @ R782 0_0402_5% R96 0_0402_5% 15 H_PM_SYNC AL33 // m Buffered reset to CPU B H_PECI_ISO R92 56_0402_5% H_PROCHOT#_R 18 H_THRMTRIP# H_CATERR# PAD SNB_IVB# SKTOCC# yc om AN34 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 p su XDP_BPM#6 XDP_BPM#7 CLOCKS SMB_DATA_S3 Q6A DMN66D0LDW-7_SOT363-6 @ +3VS 14,37 PCH_SMBCLK XDP_BPM#4 XDP_BPM#5 DDR3 MISC 14,37 PCH_SMBDATA +3VS JTAG & BPM D XDP_BPM#2 XDP_BPM#3 MISC R58 4.7K_0402_5% XDP_BPM#0 XDP_BPM#1 @ GND1 OBSFN_C0 OBSFN_C1 GND3 OBSDATA_C0 OBSDATA_C1 GND5 OBSDATA_C2 OBSDATA_C3 GND7 OBSFN_D0 OBSFN_D1 GND9 OBSDATA_D0 OBSDATA_D1 GND11 OBSDATA_D2 OBSDATA_D3 GND13 ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 GND15 TD0 TRST# TDI TMS GND17 SAMTE_BSH-030-01-L-D-A THERMAL +3VS GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16 PWR MANAGEMENT @ C128 0.1U_0402_16V4Z C59 0.1U_0402_16V4Z Place near JXDP1 /x / 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 XDP_PREQ# XDP_PRDY# 1 Title Compal Electronics, Inc PROCESSOR(2/7) PM,XDP,CLK Size Document Number Custom Rev 0.1 P5WE0 M/B LA-6901P Schematic Date: Friday, August 27, 2010 Sheet of 59 JCPU1D AE10 AF10 V6 11 DDR_A_CAS# 11 DDR_A_RAS# 11 DDR_A_WE# AE8 AD9 AF9 @ R184 0_0402_5% R217 1K_0402_5% 2 A G R186 4.99K_0402_1% 11,12,14 RST_GATE DDR_A_DQS0 DDR_A_DQS1 D4 DDR_A_DQS2 F6 DDR_A_DQS3 K3 DDR_A_DQS4 N6 AL5 DDR_A_DQS5 AM9 DDR_A_DQS6 AR11 DDR_A_DQS7 AM14 DDR_A_MA0 AD10 DDR_A_MA1 W1 DDR_A_MA2 W2 DDR_A_MA3 W7 DDR_A_MA4 DDR_A_MA5 V3 DDR_A_MA6 V2 W3 DDR_A_MA7 W6 DDR_A_MA8 DDR_A_MA9 V1 W5 DDR_A_MA10 AD8 DDR_A_MA11 DDR_A_MA12 V4 DDR_A_MA13 W4 DDR_A_MA14 AF8 DDR_A_MA15 V5 V7 SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] /x / DDR_A_DQS#[0 7] 11 yc om DDR_A_DQS#0 C4 DDR_A_DQS#1 G6 DDR_A_DQS#2 J3 DDR_A_DQS#3 M6 DDR_A_DQS#4 AL6 DDR_A_DQS#5 AM8 DDR_A_DQS#6 AR12 DDR_A_DQS#7 AM15 DDR_A_DQS[0 7] 11 DDR_A_MA[0 15] 11 12 DDR_B_BS0 12 DDR_B_BS1 12 DDR_B_BS2 12 DDR_B_CAS# 12 DDR_B_RAS# 12 DDR_B_WE# AA9 AA7 R6 AA10 AB8 AB9 SB_CLK[0] SB_CLK#[0] SB_CKE[0] SB_CLK[1] SB_CLK#[1] SB_CKE[1] AE2 AD2 R9 SB_CLK_DDR0 12 SB_CLK_DDR#0 12 DDRB_CKE0_DIMMB 12 AE1 AD1 R10 SB_CLK_DDR1 12 SB_CLK_DDR#1 12 DDRB_CKE1_DIMMB 12 AB2 AA2 T9 SB_CLK[2] SB_CLK#[2] SB_CKE[2] AA1 AB1 T10 SB_CLK[3] SB_CLK#[3] SB_CKE[3] AD3 AE3 AD6 AE6 SB_CS#[0] SB_CS#[1] SB_CS#[2] SB_CS#[3] SB_BS[0] SB_BS[1] SB_BS[2] SB_CAS# SB_RAS# SB_WE# DDRB_CS0_DIMMB# 12 DDRB_CS1_DIMMB# 12 SB_ODT[0] AE4 SB_ODT[1] AD4 SB_ODT[2] AD5 SB_ODT[3] AE5 SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] D7 F3 K6 N3 AN5 AP9 AK12 AP15 SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] C7 G3 J6 M3 AN6 AP8 AK11 AP14 SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] D AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4 SB_ODT0 12 SB_ODT1 12 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 DDR_B_DQS#[0 7] DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS[0 7] DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 DDR_B_MA[0 15] 12 C 12 12 B Sandy Bridge_rPGA_Rev0p61 CONN@ CONN@ R155 1K_0402_5% 2 D S DIMM_DRAMRST#_R Q12 BSS138_NL_SOT23-3 SA_ODT0 11 SA_ODT1 11 C9 A7 D10 C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2 J7 J8 K10 K9 J9 J10 K8 K7 M5 N4 N2 N1 M4 N5 M2 M1 AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9 AJ11 AT8 AT9 AH11 AR8 AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15 +1.5V SM_DRAMRST# SM_DRAMRST# SA_ODT[0] AH3 SA_ODT[1] AG3 SA_ODT[2] AG2 SA_ODT[3] AH2 SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] SA_CAS# SA_RAS# SA_WE# Follow CRB1.0 ᆢ⁽DIMM reset AB3 AA3 W10 DDRA_CS0_DIMMA# 11 DDRA_CS1_DIMMA# 11 SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] Sandy Bridge_rPGA_Rev0p61 CPU AB4 AA4 W9 SA_CS#[0] AK3 SA_CS#[1] AL3 SA_CS#[2] AG1 SA_CS#[3] AH1 SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] SA_BS[0] SA_BS[1] SA_BS[2] SA_CLK_DDR1 11 SA_CLK_DDR#1 11 DDRA_CKE1_DIMMA 11 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 p su SA_CLK[3] SA_CLK#[3] SA_CKE[3] AA5 AB5 V10 p: 11 DDR_A_BS0 11 DDR_A_BS1 11 DDR_A_BS2 SA_CLK[2] SA_CLK#[2] SA_CKE[2] SA_CLK_DDR0 11 12 DDR_B_D[0 63] SA_CLK_DDR#0 11 DDRA_CKE0_DIMMA 11 tt B SA_CLK[1] SA_CLK#[1] SA_CKE[1] AB6 AA6 V9 h C SA_CLK[0] SA_CLK#[0] SA_CKE[0] SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] DDR SYSTEM MEMORY A D C5 D5 D3 D2 D6 C6 C2 C3 F10 F8 G10 G9 F9 F7 G8 G7 K4 K5 K1 J1 J5 J4 J2 K2 M8 N10 N8 N7 M10 M9 N9 M7 AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8 AP11 AN11 AL12 AM12 AM11 AL11 AP12 AN12 AJ14 AH14 AL15 AK15 AL14 AK14 AJ15 AH15 // m 11 DDR_A_D[0 63] DDR SYSTEM MEMORY B JCPU1C DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 C293 0.047U_0402_16V7K DIMM_DRAMRST# 11,12 S0 RST_GATE hgih ,MOS ON SM_DRAMRST# HIGH,DIMM_DRAMRST# HIGH Dimm not reset S3 RST_GATE Low ,MOS OFF SM_DRAMRST# lo,DIMM_DRAMRST# HIGH Dimm not reset S4,5 RST_GATE Low ,MOS OFF SM_DRAMRST# lo,DIMM_DRAMRST# low Dimm reset A Compal Secret Data Security Classification Issued Date 2010/08/11 2011/08/11 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc PROCESSOR(3/7) DDRIII Size Document Number Custom Rev 0.1 P5WE0 M/B LA-6901P Schematic Date: Friday, August 27, 2010 Sheet of 59 CFG Straps for Processor CFG2 R112 1K_0402_1% D JCPU1E AJ26 RSVD6 and RSVD7 had changed to SA_DIMM_VREFDQ and SB_DIMMVREFDQ SA_DIMM_VREFDQ SB_DIMM_VREFDQ SA_DIMM_VREFDQ SB_DIMM_VREFDQ For Future CPU M3 support, Sandey bridge not supportM3, Check list1.0&CRB say can NC R164 1K_0402_1% 2 R154 1K_0402_1% VCCIO_SEL B R513 10K_0402_5% @ * RSVD6 RSVD7 F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 VCCIO_SEL For 2012 CPU support J20 B18 A19 J15 1/NC : (Default) +1.05VS_VTT 0: +1.0VS_VTT RSVD24 RSVD25 RSVD26 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 * RSVD26 had changed the name to VCCIO_SEL Need PH +3VALW 10K at +1.05VS_VTT source for 2012 processor +1.05V and +1.0V select C : Disabled; No Physical Display Port attached to Embedded Display Port : Enabled; An external Display Port device is connected to the Embedded Display Port CFG6 B34 A33 A34 B35 C35 CFG5 R107 1K_0402_1% @ @ R108 1K_0402_1% AJ32 AK32 AH27 change to VCC_DIE_SENSE RSVD53 PAD AH27 T7 @ PCIE Port Bifurcation Straps RSVD54 RSVD55 RSVD56 RSVD57 RSVD58 AN35 AM35 RSVD54 and RSVD55 had changed to BCLK_ITP and BCLK_ITP# 11: (Default) x16 - Device functions and disabled CFG[6:5] *10: x8, x8 - Device function enabled ; function B disabled 01: Reserved - (Device function disabled ; function enabled) 00: x8,x4,x4 - Device functions and enabled AT2 AT1 AR1 RSVD27 tt A19 B4 D1 CFG4 KEY B1 CFG7 h VCCIO_SEL RSVD5 11 SA_DIMM_VREFDQ 12 SB_DIMM_VREFDQ RSVD41 RSVD42 RSVD43 RSVD44 RSVD45 RSVD1 RSVD2 RSVD3 RSVD4 AJ31 AH31 AJ33 AH33 Display Port Presence Strap AR35 AT34 AT33 AP35 AR34 PAD @ PAD @ PAD @ PAD @ R109 1K_0402_1% T4 T2 T3 T5 T8 J16 H16 G16 @ to VAXG_VAL_SENSE to VSSAXG_VAL_SENSE to VCC_VAL_SENSE to VSS_VAL_SENSE 0:Lane Reversed CFG4 change change change change definition matches R102 1K_0402_1% @ Sandy Bridge_rPGA_Rev0p61 AJ31 AH31 AJ33 AH33 RSVD37 RSVD38 RSVD39 RSVD40 // m C RSVD33 RSVD34 RSVD35 * AT26 AM33 AJ27 /x / CFG4 CFG5 CFG6 CFG7 1: Normal Operation; Lane # socket pin map definition CFG2 p su CFG2 RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] L7 AG7 AE7 AK2 W8 yc om AK28 AK29 AL26 AL27 AK26 AL29 AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29 RESERVED CFG0 CFG0 PEG Static Lane Reversal - CFG2 is for the 16x p: D CONN@ PEG DEFER TRAINING CFG7 1: (Default) PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training A Compal Secret Data Security Classification Issued Date 2010/08/11 2011/08/11 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title A Compal Electronics, Inc PROCESSOR(4/7) RSVD,CFG Size Document Number Custom Rev 0.1 P5WE0 M/B LA-6901P Schematic Date: Friday, August 27, 2010 Sheet of 59 JCPU1F QC 94A DC 53A /x / PEG AND DDR p su yc om D J23 +1.05VS_VTT 1 CORE SUPPLY R447 75_0402_5% 2 SVID VIDALERT# VIDSCLK VIDSOUT R448 43_0402_1% R446 R449 0_0402_5% 1 0_0402_5% H_CPU_SVIDALRT# AJ29 H_CPU_SVIDCLK AJ30 H_CPU_SVIDDAT AJ28 VR_SVID_ALRT# 54 VR_SVID_CLK 54 VR_SVID_DAT 54 Place the PU resistors close to VR B Place the PU resistors close to CPU +CPU_CORE R445 100_0402_1% 2010/08/11 VCC_SENSE VSS_SENSE VCCSENSE_R VSSSENSE_R AJ35 AJ34 R444 R443 VSSIO_SENSE B10 A10 VCCIO_SENSE VSSIO_SENSE VSSIO_SENSE 2 VCCSENSE 54 VSSSENSE 54 0_0402_5% 0_0402_5% VCCIO_SENSE 52 change to VSS_SENSE_VCCIO R442 100_0402_1% R163 10_0402_5% SENSE LINES // m p: tt h C641 22U_0805_6.3V6M C291 22U_0805_6.3V6M C292 22U_0805_6.3V6M + C229 22U_0805_6.3V6M 2 C Should change to connect form power cirucit & layout differential with VCCIO_SENSE Compal Secret Data 2011/08/11 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC + R450 130_0402_5% Sandy Bridge_rPGA_Rev0p61 2 INTEL Recommend 2*330uF,12*22uF from PDDG 1.0 +1.05VS_VTT Security Classification IssuedCONN@ Date @ C638 330U_D2_2V_Y A @ C232 22U_0805_6.3V6M B 2 C616 330U_D2_2V_Y VCCIO40 C288 22U_0805_6.3V6M + VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39 C648 22U_0805_6.3V6M E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 C289 22U_0805_6.3V6M + +1.05VS_VTT C649 22U_0805_6.3V6M C562 470U_D2_2VM_R4M PAW00 use 470uF*2 330uF*3 + C151 470U_D2_2VM_R4M C626 470U_D2_2VM_R4M + C233 470U_D2_2VM_R4M C152 470U_D2_2VM_R4M + AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12 C652 22U_0805_6.3V6M Follow Power Suggestion , place 3-pin Cap for CPU_CORE VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24 C650 22U_0805_6.3V6M +CPU_CORE VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 C647 22U_0805_6.3V6M C606 22U_0805_6.3V6M 2 C607 22U_0805_6.3V6M 1 C160 22U_0805_6.3V6M C171 22U_0805_6.3V6M C172 22U_0805_6.3V6M 1 C608 22U_0805_6.3V6M 2 C609 22U_0805_6.3V6M 1 C575 22U_0805_6.3V6M 2 C610 22U_0805_6.3V6M 1 C635 22U_0805_6.3V6M 2 C226 22U_0805_6.3V6M 1 C627 22U_0805_6.3V6M C225 22U_0805_6.3V6M INTEL Recommend 4*470uF,16*22uF and 10*10uF from PDDG 1.0 C574 22U_0805_6.3V6M 2 C224 22U_0805_6.3V6M C C622 22U_0805_6.3V6M +1.05VS_VTT 8.5A C651 22U_0805_6.3V6M +CPU_CORE AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 C290 22U_0805_6.3V6M C222 10U_0805_6.3V6M C202 10U_0805_6.3V6M 2 C207 10U_0805_6.3V6M 1 C203 10U_0805_6.3V6M ' C218 10U_0805_6.3V6M 2 C204 10U_0805_6.3V6M C223 10U_0805_6.3V6M 2 C227 10U_0805_6.3V6M 1 C205 10U_0805_6.3V6M D C206 10U_0805_6.3V6M 1 POWER +CPU_CORE SV type CPU 2 Title A Compal Electronics, Inc PROCESSOR(5/7) PWR,BYPASS Size Document Number Custom Rev 0.1 P5WE0 M/B LA-6901P Schematic Date: Friday, August 27, 2010 Sheet of 59 D SENSE LINES p su 2 +1.5V_CPU_VDDQ +1.5V J1 10A VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1 2 2 2 2 PAD-OPEN 4x4m @ +1.5VS J2 PAD-OPEN 4x4m @ Short for +1.5VS to +1.5V_1 INTEL Recommend 1*330uF,6*10uF from PDDG 1.0 B +VCCSA 6A +VCCSA VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8 VCCSA_SENSE M27 M26 L26 J26 J25 J24 H26 H25 2 @ R1371 + 2 0_0402_5% VCCSA_SENSE If possible,use os-con cap if not,use the D2 size R1411 0_0402_5% VSSSA_SENSE 51 VCCSA_SENSE 51 H23 VCCSA VCCSA_VID0 VCCSA_VID1 C22 C24 FC_C22 change to VCCSA_VID0 VCCSA_VID1 51 VID0 VID1 Vout 2011CPU 2012CPU 0 0.9V V V 0.8V V V 0.725V X V 1 0.675V X V FC_C22 VCCSA_VID1 R143 10K_0402_5% R138 @ 0_0402_5% CONN@ Compal Secret Data Security Classification 2010/08/11 2011/08/11 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC + INTEL Recommend 1*330uF,3*10uF from PDDG 1.0 Sandy Bridge_rPGA_Rev0p61 Issued Date VREF DDR3 -1.5V RAILS SA RAIL A INTEL Recommend 1*330uF,1*10uF and 2*1uF(0402) from PDDG 1.0 VCCPLL1 VCCPLL2 VCCPLL3 MISC p: B6 A6 A2 R575 100_0402_1% C221 330U_D2_2V_Y C653 1U_0402_6.3V6K 2 C654 1U_0402_6.3V6K A C655 10U_0805_6.3V6M + C664 330U_D2_2V_Y 1 C213 10U_0603_6.3V6M +1.8VS_VCCPLL C688 0.1U_0402_16V4Z C219 10U_0805_6.3V6M 1.2A R528 0_0805_5% +V_SM_VREF C605 10U_0805_6.3V6M +1.8VS AL1 C214 10U_0805_6.3V6M h tt motherboard design (Gfx VR keeps VAXG from floating) if the VR is stuffed SM_VREF C R582 100_0402_1% C355 330U_D2_2V_Y supports external graphics and if GFX VR is not stuffed in a common motherboard design, Ʉ VAXG can be left floating in a common +V_SM_VREF should have 20 mil trace width C361 10U_0805_6.3V6M Ʉ Can connect to GND if motherboard only +1.5V_CPU_VDDQ C365 10U_0805_6.3V6M Vaxg B VCC_AXG_SENSE 54 VSS_AXG_SENSE 54 C341 10U_0805_6.3V6M UMA@ AK35 AK34 C362 10U_0805_6.3V6M UMA@ VAXG_SENSE VSSAXG_SENSE C364 10U_0805_6.3V6M 2 VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54 C363 10U_0805_6.3V6M @ UMA@ C599 22U_0805_6.3V6M @ C600 22U_0805_6.3V6M UMA@ C273 22U_0805_6.3V6M UMA@ C275 22U_0805_6.3V6M UMA@ C242 22U_0805_6.3V6M UMA@ AT24 AT23 AT21 AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17 AL24 AL23 AL21 AL20 AL18 AL17 AK24 AK23 AK21 AK20 AK18 AK17 AJ24 AJ23 AJ21 AJ20 AJ18 AJ17 AH24 AH23 AH21 AH20 AH18 AH17 yc om JCPU1G GRAPHICS 2 C271 22U_0805_6.3V6M 2 C208 22U_0805_6.3V6M + C274 22U_0805_6.3V6M 2 C645 330U_D2_2V_Y UMA@ + C646 330U_D2_2V_Y UMA@ C209 22U_0805_6.3V6M C210 22U_0805_6.3V6M UMA@ UMA@ C231 22U_0805_6.3V6M C UMA@ C211 22U_0805_6.3V6M UMA@ C272 22U_0805_6.3V6M UMA@ C212 22U_0805_6.3V6M UMA@ C625 22U_0805_6.3V6M UMA@ C611 22U_0805_6.3V6M R151 0_0402_5% DISO@ POWER QC 33A DC 26A // m +VGFX_CORE 1.8V RAIL INTEL Recommend 2*470uF,12*22uF from PDDG 1.0 /x / D Title Compal Electronics, Inc PROCESSOR(6/7) PWR Size Document Number Custom Rev 0.1 P5WE0 M/B LA-6901P Schematic Date: Friday, August 27, 2010 Sheet of 59 JCPU1H D h T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 P9 P8 P6 P5 P3 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34 L33 L30 L27 L9 L8 L6 L5 L4 L3 L2 L1 K35 K32 K29 K26 J34 J31 H33 H30 H27 H24 H21 H18 H15 H13 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 /x / AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2 p su VSS tt B JCPU1I VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 yc om C VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 // m AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10 AT7 AT4 AT3 AR25 AR22 AR19 AR16 AR13 AR10 AR7 AR4 AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10 AP7 AP4 AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10 AN7 AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10 AM7 AM4 AM3 AM2 AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10 AL7 AL4 AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10 AK7 AK4 AJ25 p: D Sandy Bridge_rPGA_Rev0p61 VSS F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3 C B Sandy Bridge_rPGA_Rev0p61 CONN@ CONN@ A A Compal Secret Data Security Classification Issued Date 2010/08/11 2011/08/11 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc PROCESSOR(7/7) VSS Size Document Number Custom Rev 0.1 P5WE0 M/B LA-6901P Schematic Date: Sheet Friday, August 27, 2010 10 of 59 C366 C367 1 1 11 U3TXDP2_L 2 2 2 2 USB30@USB30@ USB30@ 22 1U_0402_16V7K 1U_0402_16V7K 1U_0402_16V7K 1U_0402_16V7K 1U_0402_16V7K USB30@ USB30@ USB30@ USB30@ USB30@ 7K for customer request, can use other kind of capacitor, like Y5V +1.05VR D7 P13 U2AVDD10 H3 H4 L5 H11 K11 K12 L8 VDD10 VDD10 VDD10 VDD10 VDD10 VDD10 VDD10 VDD10 VDD10 E11 E12 E3 E4 VDD10 VDD10 C8 C9 D8 D9 VDD10 VDD10 VDD10 VDD10 C4 C5 C6 C7 D5 VDD10 VDD10 VDD10 VDD10 VDD10 N4 N5 N6 P3 VDD33 VDD33 VDD33 VDD33 L9 L10 L13 L14 VDD33 VDD33 U3AVDO33 /x / PERXP PERXN U3TXDP2 U3TXDN2 U2DM2 U2DP2 U3RXDP2 U3RXDN2 H2 K1 K2 J2 @ R604 100_0402_1% J1 SMI_R R602 USB30@2 10K_0402_5% H1 SMIB_R R605 @ 0_0402_5% 18,38 SMIB P4 R600 USB30@2 0_0402_5% +3V_USB3.0 P5 R611 USB30@2 10K_0402_5% SPI_CLK_USB 1 2 M2 SPI_CS_USB# D21 USB_SO_SPI_SI N2 1SS355TE-17_SOD323-2 N1 USB_SI_SPI_SO USB30@ M1 USB30@ K13 K14 J13 +3V_USB3.0 PERSTB PEWAKEB PECREQB AUXDET PSEL SMI SMIB Can be attach to EC, either PCI Express/ExpressCard select signal 1:others 0:Express Card or Mini card PONRSTB C702 1U_0603_10V6K SPISCK SPISCB SPISI SPISO GND GND GND OCI2B OCI1B PPON2 PPON1 U3TXDP1 U3TXDN1 U2DM1 U2DP1 U3RXDP1 U3RXDN1 @ MX25L5121EMC-20G_SO8 USB3_XT1 USB3_XT2 +3V_USB3.0 R665 100_0402_5% Place as close as possibile to U3.N14 and U3.M14 24MHZ_12PF_X5H024000DC1H C709 USB30@ 12P_0402_50V8J USB30@ C707 12P_0402_50V8J USB30@ Pin compare table for support USB remote wakeup or not AUXDET(Pin J2) CSEL(Pin P6) CLK pull high 10k to VDD33 Tied to GND Must use 24MHz crystal: mount Y1,R19,C40,C41 Not support USB remote wakeup Tied to GND pull high to VDD33 Can use either 48MHz or 24MHz When use 48MHz clock: mount R22,R25 U3RXDP2 4 U2DN2 4 R683 @ D 0_0402_5% 0_0402_5% +USB3_VCCA C705.1U_0402_16V7K U3TXDP2_L USB30@ U3TXDN2_L USB30@ C706.1U_0402_16V7K + 2 D24 +3V_USB3.0 D22 I/O1 I/O4 U3RXDP2 I/O2 REF1 REF2 I/O2 I/O3 U3TXDP2 C U3TXDN2 D33 +USB3_VCCA I/O1 REF1 REF2 PJUSB208H_SOT23-6 @ P10 B12 I/O4 I/O2 I/O3 +USB3_VCCA PJUSB208H_SOT23-6 @ +USB3_VCCA +5VALW A12 P12 N12 U3AVSS D6 C432 1U_0402_16V7K R298 1.6K_0402_1% 38,43 SYSON# USB30@ W=60mils GND VIN VIN EN VOUT VOUT VOUT FLG OCI2B 0_0402_5% R313 AP2301MPG-13_MSOP8 U2DN2 @ P14 P11 P9 P7 P2 P1 N13 N9 N7 N3 M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 L12 L11 L7 L6 USB20_N2 L52 R687 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND +USB3_VCCA U2DP2 I/O3 For ESD request U3RXDN2 A10 N10 I/O4 REF1 REF2 PJUSB208H_SOT23-6 @ H14 J14 B10 I/O1 U2DN2 R307 USB30@2 10K_0402_5% R308 10K_0402_5% USB30@ 17 UPD720200AF1-DAP-A_FBGA176~DSecurity Classification USB30@ Support USB remote wakeup R657 @ B USB30@0_0402_5% 1 USB20@ R314 USB_OC2# 17 0_0402_5% 1 17 4 U2DP2 WCM2012F2S-900T04_0805 USB20_P2 C417 @ 0.1U_0402_16V4Z @ with L52 Resister overlap R686 0_0402_5% +USB3_VCCA U3TXDP2 JUSB5 U3TXDN2 U2DP2 U2DN2 U3RXDP2 U3RXDN2 SSTX+ VBUS SSTXD+ GND DSSRX+ GND SSRX- For customer request GND_FRAME GND GND GND GND R693 0_0603_5% 10 11 12 13 R617 0_0603_5% ACON_TARA4-9K1311 CONN@ GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND A GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND USB30@ U2DP2 1 C726 A 1U_0402_16V7K C12 C13 D3 D4 D11 D12 D13 D14 E1 E2 E13 E14 F4 F6 F7 F8 F9 F11 F12 G1 G2 G6 G7 G8 G9 G11 G12 G13 H6 H7 H8 H9 H12 J3 J4 J6 J7 J8 J9 J11 J12 K3 K4 L1 L2 L3 L4 Y5 CSEL OCI2B G14 OCI1B H13 N11 h USB30@ A1 A2 A3 A4 A5 A7 A9 A11 A13 A14 B3 B4 B5 B7 B9 B11 B13 B14 C1 C2 C3 C10 C11 // m 2 CS# SO WP# GND R634 0_0402_5% VCC NC SCLK SI R628 0_0402_5% U39 SPI_CLK_USB USB_SO_SPI_SI P6 SPI_CS_USB# USB_SI_SPI_SO @R703 @ R703 47K_0402_5% XT1 XT2 R704 C725 10K_0402_5% 1U_0402_16V7K USB30@ USB30@ 1 N14 M14 U3TX_C_DP2 B6 U3TX_C_DN2 A6 U2DN2_L N8 U2DP2_L P8U3RXDP2_L B8 U3RXDN2_L A8 U2PVSS p: USB3_XT1 USB3_XT2 +3V_USB3.0 B GND RREF U2AVSS tt C14 USB30@ U3RXDN2 1 WCM2012F2S-900T04_0805 U17 As short as possible +3V_USB3.0 U3RXDP2_L 0_0402_5% L41 +3VA_USB3.0 L22 BLM18AG601SN1D_2P USB30@ C422 10U_0805_6.3V6M USB30@ p su 14 USB30_CLKREQ#_L +3V_USB3.0 F2 F1 U2DN2_L U3RXDN2_L 0_0402_5% L43 0_0402_5% R658 @ +3V_USB3.0 SPEC Max:+3V -200mA;+1.05V -800mA Idle mode:0.489W: +3V -43mA;+1.05V -328mA D3 mode:0.066W: +3V -5.4mA;+1.05V -45mA PETXP PETXN R659 @ +3VA_USB3.0 yc om OD output R606 USB30@2 0_0402_5% R601 USB30@2 0_0402_5% USB30_CLKREQ#_L R603 USB30@2 10K_0402_1% D2 D1 PECLKP PECLKN R680 @ U2DP2_L C391 470P_0603_50V7K 5,17,35,38,39 PLT_RST# 15,35,37,38 PCH_PCIE_WAKE# C B2 B1 U3TXDP2 4 C390 150U_B2_6.3VM_R35M RT9701-PB_SOT23-5 USB30@ 14 CLK_PCIE_USB30_L 14 CLK_PCIE_USB30_L# PCIE_PRX_C_DTX_P5 USB30@ 14 PCIE_PRX_DTX_P5 PCIE_PRX_C_DTX_N5 C699 1U_0402_16V7K 14 PCIE_PRX_DTX_N5 C698 1U_0402_16V7K USB30@ 14 PCIE_PTX_C_DRX_P5 14 PCIE_PTX_C_DRX_N5 VDD33 VDD33 GND F3 G3 G4 VIN VOUT VIN/CE VOUT VDD33 VDD33 VDD33 +1.05V_USB3.0 U34 D10 F13 F14 SYSON 38,39,43,50 SYSON +3V_USB3.0 For EMI request OCE2012120YZF_0805 R310 0_0805_5% +3V_USB3.0 U19 VDD33 VDD33 VDD33 +3VALW +3VALW to +3V Transfer USB30@ U3TXDN2 1 OCE2012120YZF_0805 1U_0402_16V7K C389 1U_0402_16V7K C695 1U_0402_16V7K GND C718 1U_0402_16V7K C717 1 C368 C396 C696 0_0402_5% L42 U3TXDN2_L @ 1U_0402_16V7K R660 @ USB30@USB30@ USB30@ USB30@ 1U_0402_16V7K 1U_0402_16V7K C716 C715 1U_0402_16V7K C369 USB30@ 1U_0402_16V7K Vout=0.8(1+10K/32.4K) 1.042 ~ 1.0469 ~ 1.0519V Spec: 0.9975 ~ 1.05 ~ 1.1025 @ C370 APL5930KAI-TRG_SO8 USB30@ D 1U_0402_16V7K R325 10K_0402_1% USB30@ R326 32.4K_0402_1% USB30@ C405 8P_0402_50V8D FB USB30@ C406 1U_0402_16V7K EN POK USB30@ USB30@ C379 0.01U_0402_16V7K VOUT VOUT C386 8P_0402_50V8D USB30@ USB30@ VCNTL VIN VIN C419 10U_0603_6.3V6M SYSON R327 5.1K_0402_1% USB30@ USB30@ USB30@ USB30@ +3VA_USB3.0 C382 0.01U_0402_16V7K +3VA_USB3.0 C397 1U_0402_16V7K +5VALW Close to U3.P13 C401 U18 +1.5V Close to U3.D7 +1.05V_USB3.0 C697 C402 10U_0603_6.3V6M C420 1U_0603_10V6K +5VALW +1.05VR +3V_USB3.0 +1.5V to +1.05V Transfer +1.5V +5VALW EPAD Issued Date Compal Secret Data 2010/08/11 2011/08/11 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title USB3.0 PD720200 Size Document Number Custom Date: Friday, August 27, 2010 Rev 0.1 Sheet 45 of 59 VIN PL1 SMB3025500YA_2P @ PJP1 ACES_50305-00441-001 GND GND 2 +3VALWP @ PJ7 1 +3VALW PC3 100P_0402_50V8J PC2 100P_0402_50V8J 2 PC1 1000P_0402_50V7K 1 JUMP_43X118 PC4 1000P_0402_50V7K +5VALWP D @ PJ9 @ +5VALW +VCCSAP VIN @ +1.8VSP PD1 LL4148_LL34-2 JUMP_43X118 @ PR2 68_1206_5% 51ON# +1.5VP PC6 0.1U_0603_25V7K +1.05VS_VCCPP 2 @ PJ17 2 @ PJ19 @ +VGFX_COREP JUMP_43X118 @ 1 C JUMP_43X118 +1.05VS_VTT +VSB PJ18 JUMP_43X118 2 JUMP_43X39 PJ20 +VGFX_CORE JUMP_43X118 PJ26 JUMP_43X118 @ +1.5VSDGPUP PJ25 +1.5VSDGPU JUMP_43X118 B+ B PR13 100K_0402_5% 2 BAS40CW_SOT323-3 PQ3 PDTC115EU_SOT323-3 PQ4 PDTC115EU_SOT323-3 h +5VALWP @ PJ16 12 p: tt PD4 48,49 +VSBP PR12 1K_1206_5% ACOFF @ +1.5V 1 100K_0402_5% PR11 1K_1206_5% B PR10 PR9 PR8 1K_1206_5% 39,47 +3VLP PQ2 TP0610K-T1-E3_SOT23-3 LL4148_LL34-2 PD3 100K_0402_5% PR7 1K_1206_5% // m VIN yc om PreCHG +CHGRTC PJ15 JUMP_43X118 PR4 22K_0402_5% PR5 0_0603_5% 2 p su 40 @ VS 1 JUMP_43X118 PR3 100K_0402_5% PC5 0.22U_0603_25V7K N1 PQ1 TP0610K-T1-E3_SOT23-3 PJ14 /x / 1 PR1 68_1206_5% C D +1.8VS 1 +VCCSA 1 PD2 LL4148_LL34-2 BATT+ PJ12 PJ10 JUMP_43X118 JUMP_43X118 A A Compal Secret Data Security Classification Issued Date 2010/07/13 2011/07/13 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc PWR DCIN / Pre-charge Size Document Number Custom P5WE0 M/B LA-6901P Schematic Date: Friday, August 27, 2010 Sheet 46 of 59 Rev 0.1 B C D PQ5 AO4407A_SO8 PC181 reserve for EMI Isen solution D ACLIM VDDP 15 11 VADJ LGATE 14 12 GND PGND S 39 CALIBRATE# 2 1 @ PC181 10U_1206_25V6M 1 PQ16 AO4466L_SO8 PC17 1000P_0402_50V8-J @ @ PR45 31.6K_0402_1% 6251VDD CC=0.6~4.48A 1 PR48 10K_0402_1% PR47 10K_0402_1% PR46 47K_0402_5% IREF=0.43V~3.24V ACIN 15,39,43,44 PACIN 2 12.60V PC11 2200P_0402_25V7K 13 PR41 4.7_0603_5% PC28 4.7U_0603_6.3V6M p: PR44 15.4K_0402_1% h 12600mV PD8 RB751V-40_SOD323-2 6251VDD 2 DL_CHG 10 IREF=0.7224*Icharge Normal 3S LI-ON Cells 6251VDDP PC26 10U_1206_25V6M 16 PC23 0.1U_0603_25V7K BST_CHGA 2 PR34 0.02_1206_1% PC25 10U_1206_25V6M BOOT PR37 0_0603_5% BST_CHG tt CV mode PC10 0.1U_0603_25V7K CHLIM 17 BATT+ ISL6251AHAZ-T_QSOP24 G PQ18 2N7002W -T/R7_SOT323-3 PC14 1000P_0402_25V8J DH_CHG UGATE VREF PR35 4.7_1206_5% PHASE ICM TCR=50ppm / C PL2 10UH_PCMB104T-100MS_6A_20% CHG 2 CSIP p su VCOMP PQ15 AO4466L_SO8 PC27 680P_0402_50V7K CSIN CSOP ICOMP S CSON PC18 0.047U_0402_16V7K 21 PR29 20_0402_5% 20 PR30 20_0402_5% PC21 0.1U_0603_25V7K PR32 19 2_0402_5% LX_CHG 18 D G CSOP PR28 20_0402_5% ACPRN PQ12 2N7002W -T/R7_SOT323-3 CELLS 0.1U_0603_25V7K ACPRN 48 /x / DCIN PQ9 PDTC115EU_SOT323-3 CSON // m CP mode Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) where Vaclm=1.502V, Iinput=4.07A Charging Voltage (0x15) EN 22 6251aclim 12.1K_0402_1% 39,49 65W/90W# BATT Type ACSET ACPRN 23 PR40 PR21 100K_0402_5% PC22 1U_0402_16V7K 6251VREF V1 PR15 10K_0402_1% yc om ADP_I PQ17 PDTC115EU_SOT323-3 PR43 20K_0402_1% 2 ACOFF PR39 100K_0402_1% ACOFF 24 PR31 10K_0402_1% 0.01U_0402_25V7K PR33 100_0402_1% 6251VREF PR42 2.55K_0402_1% IREF PR36 80.6K_0402_1% 39 39,49 PC24 0.01U_0402_25V7K S PR38 47K_0402_5% DCIN VDD VIN PR23 14.3K_0402_1% PC15 6251_EN PC19 6800P_0402_25V7K PC20 PR16 47K_0402_1% 2 D PQ14B DMN66D0LDW -7_SOT363-6 3 PQ14A DMN66D0LDW -7_SOT363-6 ACSETIN 1 PR26 ACSETIN S PACIN G 39,46 PD5 RB751V-40_SOD323-2 PU1 PQ13 PDTC115EU_SOT323-3 PR24 0_0402_5% FSTCHG PQ10 PDTC115EU_SOT323-3 3S/4S# PC8 10U_1206_25V6M PC9 10U_1206_25V6M 2 PR18 191K_0402_1% 6251VDD 1 PR27 150K_0402_1% 39 VIN PreCHG PR25 47K_0402_5% 6251VDD CSIN V1 G PR17 200K_0402_1% 39 D CHG_B+ PL22 HCB4532KF-800T90_1812 CSIP 47K PQ8 PDTA144EU_SOT323-3 2 PR22 10_1206_5% 1 1 47K PC12 0.1U_0603_25V7K PR19 200K_0402_1% B+ PR14 0.02_2512_1% P3 PQ7 AO4407A_SO8 3 PC7 5600P_0402_25V7K PC13 2.2U_0603_6.3V6K P2 PQ6 AO4407A_SO8 VIN CP = 85%*Iada ; CP = 4.07A ADP_I = 19.9*Iadapter*Rsense 100K_0402_1% Iada=0~4.74A(90W/19V=4.736A) A 1 Ki Vchlim=Iref*(PR374/(PR372+PR374)) =Iref*(100K/(80.6K+100K)) =Iref*0.5537 Ichanrge=(165mV/PR369)*(Vchlim/3.3V) =(165m/20m)*(1/3.3V)*Iref*0.5537 =1.3842*Iref Iref=0.7224*Ichanrge =>Ki=0.7224 PQ19 PDTC115EU_SOT323-3 Kv Rinternal ic=514K Rec=3K R1=PR379=15.4K R2=PR381=31.6K R=514K//31.6K//(15.4K+3k)=11.372K r=514K//514K//31.6K=28.14K Vcell=0.175*Vadj+3.99v 4.2V=0.175*Vadj+3.99V =>Vadj=1.2V Vadj=Vref*(R/(R+514K))+CALIBRATE*(r/(r=514K)) 1.1483=CALIBRATE*0.6046 =>CALIBRATE=1.899 1.899=(4.2-(Vcell+A*0.175))*Kv=(4.2-(4.2+A*0.175))*Kv A=Vref*(R/(R+514K))=0.052 Kv=9.451 A PR49 14.3K_0402_1% ACPRN Compal Secret Data Security Classification Issued Date 2010/07/13 Deciphered Date 2011/07/13 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B C Title Compal Electronics, Inc PWR-CHARGER Size Document Number Custom P5WE0 M/B LA-6901P Schematic Date: Friday, August 27, 2010D Sheet 47 of 59 Rev 0.1 PC29 1U_0603_10V6K 2VREF_8205 D PR51 30K_0402_1% S PR64 100K_0402_1% EC_ON PQ27 PDTC115EU_SOT323-3 2 PR66 100K_0402_1% 5 PL5 4.7UH_PCMC063T-4R7MN_5.5A_20% LG_5V NC RT8205EGQW _W QFN24_4X4 2 AO4712_SO8 PQ23 RT8205_B+ 2VREF_8205 PC47 4.7U_0805_10V6K VL Typ: 175mA +5VALWP + PC43 18 VIN 17 16 15 14 UG_5V LX_5V 19 VREG5 LGATE1 SKIPSEL PHASE1 LGATE2 GND PHASE2 BST_5V 49 @ PR60 4.7_1206_5% UGATE1 C SPOK PR57 PC41 0_0603_5% 0.1U_0603_25V7K 21 @ PC45 680P_0402_50V7K 22 21 PQ21 AO4466L_SO8 FB1 REF FB2 TONSEL ENTRIP1 BOOT1 PC38 0.1U_0603_25V7K /x / ENTRIP1 p su PGOOD 23 12 PC46 1U_0603_10V6K 2 RT8205_B+ 220U_6.3VM_R15 B TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP) (2)SMPS2=375KHZ(+3VALWP) +3.3VALWP Ipeak=5.78A ; 1.2Ipeak=6.94A; Imax=4.05A f=375KHz, L=4.7UH Rdson=15~18m ohm 1/2Delta I = 1/2 *(19-3)*(3/19)/(375KHz*4.7UH)=0.716A Vlimit=10*10^-6*110Kohm/10=0.11V Ilimit=0.11/(18m*1.2)~0.11/(15m)=6.34A~9.13A Iocp=7.06A~9.85AA (7.06A>6.94A -> ok) -DVT- +5VALWP Ipeak=7A ; 1.2Ipeak=8.4A; Imax=4.9A f=300KHz, L=4.7UH,Rentrip=154k ohm Rdson=15~18m ohm 1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*4.7UH)=1.306A Vlimit=10*10^-6*154Kohm/10=0.15V Ilimit=0.15/(18m*1.2)~0.15/(15m)=7.13~10.26A Iocp=8.44~11.57A (8.44>8.4 -> OK) A 1 VS S PC49 2.2U_0603_6.3V6K 39,40 PQ25 PDTC115EU_SOT323-3 D PR67 40.2K_0402_1% A 2N7002W -T/R7_SOT323-3 PQ26 PR65 200K_0402_5% 2 G ACPRN Compal Secret Data Security Classification 2010/07/13 Issued Date Deciphered Date 2011/07/13 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 47 24 20 S VL UGATE2 h PR63 0_0402_5% PQ24B DMN66D0LDW -7_SOT363-6 PR55 154K_0402_1% 11 D tt G VO1 VFB=2.0V PC48 0.1U_0603_25V7K MAINPWON 49 10 // m ENTRIP2 ENTRIP1 G BOOT2 PR61 499K_0402_1% PR62 100K_0402_1% B+ D PQ24A DMN66D0LDW -7_SOT363-6 VREG3 PR59 @ 0_0402_5% MAINPW ON p: B LG_3V LX_3V PQ22 AO4712_SO8 @ PC44 680P_0402_50V7K + PC40 0.1U_0603_25V7K @ PR58 4.7_1206_5% 4.7UH_PCMC063T-4R7MN_5.5A_20% PL4 PR56 BST_3V 21 0_0603_5% UG_3V VO2 EN PC42 220U_6.3V_M P PAD yc om ENTRIP2 25 +3VALWP ENTRIP2 PU2 PQ20 AO4466L_SO8 PR53 20K_0402_1% PR54 110K_0402_1% PC39 4.7U_0805_10V6K PC34 2200P_0402_50V7K PC33 4.7U_0805_25V6-K C +3VLP Typ: 175mA PC32 4.7U_0805_25V6-K PC31 0.1U_0603_25V7K B+ PR52 20K_0402_1% 13 PL3 HCB4532KF-800T90_1812 PC37 2200P_0402_50V7K PIN25 is floating , not GND (so it's fail for this circuit) -DVT- RT8205_B+ PC36 4.7U_0805_25V6-K PR50 13K_0402_1% PC35 4.7U_0805_25V6-K D Title Compal Electronics, Inc 3VALWP/5VALWP Size Document Number Custom Rev P5WE0 M/B LA-6901P Schematic 0.1 Date: Friday, August 27, 2010 Sheet 48 of 59 PJP2 SUYIN_200275GR008G13GZR D 10 2 EC_SMDA EC_SMCA TH PI PR68 100_0402_1% PH1 under CPU botten side : CPU thermal protection at 92 degree C Recovery at 72 degree C GND GND 1 D PR69 100_0402_1% EC_SMB_DA1 39 VL 1 VMB BATT+ OT2 RHYST2 C PH1 PH2 @ 100K_0402_1%_NCP15WF104F03RC 2 +5VALWP B ADP_I 39,47 2 @ PC170 0.1U_0603_25V7K PR240 9.09K_0402_1% PR244 10K_0402_1% D 5,39 H_PROCHOT# 1 D @ PQ65 2N7002W-T/R7_SOT323-3 PU13 VCC TMSNS1 GND RHYST1 OT1 TMSNS2 PR241 34.8K_0402_1% S @ PQ66 2N7002W-T/R7_SOT323-3 G S 2 0_0402_5% @ PR239 100K_0402_1% OT2 RHYST2 65W/90W# 39,47 G PR250 @ PR243 7.15K_0402_1% +3VS 1 tt PQ29 2N7002W-T/R7_SOT323-3 PR76 9.53K_0402_1% 100K_0402_1%_NCP15WF104F03RC S G PR245 0_0402_5% p: D h SPOK PC55 1U_0402_6.3V6K 48 PR81 1K_0402_5% PR80 100K_0402_1% B PC54 0.1U_0603_25V7K OT1 TMSNS2 1 2 PC53 0.22U_0603_25V7K 2 PR78 100K_0402_1% PR79 22K_0402_1% VL +VSBP 3 G718TM1U_SOT23-8 @ PR77 47K_0402_1% // m B+ PQ28 TP0610K-T1-E3_SOT23-3 GND RHYST1 yc om BATT_TEMP 39 VCC TMSNS1 2 48 MAINPWON PU3 1 p su C PR72 21K_0402_1% 2 @ PR74 100K_0402_1% PR75 1K_0402_1% PR71 10K_0402_1% VL 1 +3VALWP /x / PC52 0.01U_0402_25V7K 1 PC51 1000P_0402_50V7K PC50 0.1U_0603_25V7K PR73 6.49K_0402_1% 2 EC_SMB_CK1 39 PR70 1K_0402_5% PL6 SMB3025500YA_2P PR242 10K_0402_1% G718TM1U_SOT23-8 A A Compal Secret Data Security Classification Issued Date 2010/07/13 2011/07/13 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc PWR-BATTERY CONN/OTP Size Document Number Custom P5WE0 M/B LA-6901P Schematic Date: Friday, August 27, 2010 Sheet 49 of 59 Rev 0.1 A B C D PL7 HCB4532KF-800T90_1812 CS 11 VDDP 10 NC PR90 yc om 1 + DL_1.5VDGPU VGA@ PC70 330U_6.3V_M 2 10 VGA@ PC71 4.7U_0805_10V6K VGA@ PQ33 AO4456_SO8 @ PC72 680P_0402_50V7K RT8209MGQW _W QFN14_3P5X3P5 VGA@ LGATE 11 PGOOD @ PR97 4.7_1206_5% +5VALW CS VDDP PGND FB +1.5VSDGPUP LX_1.5VDGPU 12 VGA@ PL10 1UH_FDUE1040D-1R0M-P3_21.3A_20% DH_1.5VDGPU PR99 10K_0402_1% NC BOOT 15 VDD GND p: h VGA@ PC73 4.7U_0603_10V6K 13 PHASE VFB=0.75V tt VGA@ PR98 100_0603_5% UGATE VGA@ PQ32 AO4466L_SO8 B+ VGA@ PC66 4.7U_0805_25V6-K VGA@ VGA@ PC68 PR96 0_0603_5%BST_1.5VDGPU-1 0.1U_0603_25V7K 2 14 // m TON VOUT EN/DEM PU5 VGA@ PL9 HCB4532KF-800T90_1812 1.5VDGPU_8209_B+ VGA@ PC175 0.1U_0603_25V7K VGA@ PC65 4.7U_0805_25V6-K 2 2 @ PC69 1U_0402_16V7K +5VALW BST_1.5VDGPU @ PR95 47K_0402_5% SYSON VGA@ PR92 267K_0402_1% VGA@ PR94 0_0402_5% @ PC63 680P_0402_50V7K VGA@ PC174 2200P_0402_50V7K PR91 10K_0402_1% +1.5VP Ipeak=19.53A;1.2Ipeak=23.44A ;Imax=13.67A Rton=267K, Fsw=298KHz ,Rdson=5.3~7mohm Rtrip=12K Iocp=18.17~28.98A AO4456_SO8 p su 10K_0402_1% PC62 4.7U_0805_10V6K PC61 330U_6.3V_M PC64 4.7U_0603_10V6K PC57 4.7U_0805_25V6-K 2 DL_1.5V RT8209MGQW _W QFN14_3P5X3P5 + LGATE PGOOD +1.5VP @ PR87 4.7_1206_5% PQ31 /x / +5VALW FB PL8 1UH_FDUE1040D-1R0M-P3_21.3A_20% LX_1.5V 15 14 DH_1.5V 12 VFB=0.75V PR88 100_0603_5% 13 PHASE VDD UGATE B+ AO4466L_SO8 PC59 PR85 0.1U_0603_25V7K 0_0603_5% BST_1.5V-1 2 PR89 15K_0402_1% BOOT TON VOUT BST_1.5V PGND PU4 EN/DEM @ PC60 1U_0402_16V7K GND 2 +5VALW 38,39,43,45 SYSON @ PR86 47K_0402_5% PR83 267K_0402_1% PR84 0_0402_5% PC56 4.7U_0805_25V6-K PQ30 PC172 0.1U_0603_25V7K PC173 2200P_0402_50V7K 1.5_8209_B+ VGA@ VGA@ PR100 10K_0402_1% 2 VGA@ PR101 10K_0402_1% 4 +1.5VSDGPUP Ipeak=10.4A;1.2Ipeak=12.48A ;Imax=7.28A Rton=267K, Fsw=298KHz ,Rdson=4.5~5.6mohm Rtrip=10K Iocp=14.68~26.29A Compal Secret Data Security Classification Issued Date 2010/07/13 Deciphered Date 2011/07/13 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title Compal Electronics, Inc PWR-+1.5VP/+1.5VSDGPU Size Document Number Custom P5WE0 M/B LA-6901P Schematic Date: Friday, August 27, 2010D Sheet 50 of 59 Rev 0.1 PR105 10K_0402_1% 1.8VSP Ipeak=3.35A ; 1.2Ipeak=4.02 ;Imax=2.345A Vout=0.6*(1+(20K/10K))=1.8V -DVT- PL23 FBMA-L11-322513-201LMA40T_1210 B+ /x / SY8033BDBC_DFN10_3X3 1 PR106 1M_0402_5% PC78 680P_0603_50V7K PC79 0.1U_0402_10V7K PR104 100K_0402_5% PC77 22U_0805_6.3VAM PC75 68P_0402_50V8J 2 FB=0.6Volt D PR103 20K_0402_1% 1 @ PC88 4700P_0402_25V7K PR114 0_0402_5% PC86 4.7U_0805_10V6K VSSSA_SENSE PR119 VCCSA_SENSE VFB=0.75V Vo=VFB*(1+PR156/PR150)=1.1V Ton=19E-12*Ron*(((2/3)*Vo+150mV)/Vin)+50ns=2.4E-7 Freq=282KHz 10_0402_5% B Cesr=15m ohm Ipeak=4.60A Imax=2.70A Delta I=((19.5-1.0)*(1.0/19.5))/(L*Freq)=1.48A Vtrip=Rtrip*10uA=0.0787V Iocp-min=5.96A Iocp-max=6.01A Iocp=5.96~6.01A PQ37 PMBT2222A_SOT23-3 h 1 PQ36 2N7002W-T/R7_SOT323-3 PR124 @ 100K_0402_5% 2 PR125 VCCSA_VID1 @ PR126 10K_0402_5% 0_0402_5% 2 S PR113 0_0402_5% tt G PR122 30K_0402_1% 2 PR121 10K_0402_5% PR123 10K_0402_5% @ PC85 470P_0603_50V8J PC84 330U_6.3V_M p: +3VS PR120 15K_0402_1% PC81 4.7U_0805_25V6-K B D 39 + RT8209MGQW_WQFN14_3P5X3P5 PR118 2K_0402_1% VFB=0.75V yc om LG_VCCSAP // m NC SA_PGOOD LGATE +VCCSAP @ PR111 4.7_1206_5% PQ35 AO4712_SO8 10 PGOOD +5VALW 11 0_0402_5% PR117 BOOT VDDP 14 15 FB 12 PR115 10K_0402_5% PC87 4.7U_0603_6.3V6K Layout Note: Place near V5FILT Pin +3VS CS LX_VCCSAP PR116 15K_0402_1% PR112 100_0603_1% +5VALW PHASE VDD UG_VCCSAP VOUT 13 C PL12 2.2UH_PCMC063T-2R2MN_8A_20% PC82 PR109 0.1U_0603_25V7K 0_0603_5% BST_VCCSAP-1 2 UGATE PGND TON 2 @ PC83 0.1U_0402_16V7K GND @ PR110 47K_0402_5% EN/DEM PU7 52 VCCPPWRGOOD BST_VCCSAP EN_VCCSAP PR108 0_0402_5% PQ34 AO4466L_SO8 p su PR107 267K_0402_1% PC176 0.1U_0603_25V7K PC80 4.7U_0805_25V6-K PC177 2200P_0402_50V7K 5603_VCCSAP_B+ C +1.8VSP FB_1.8V FB 1 PG SVIN EN 11 37,39,43,52 SUSP# PR102 4.7_1206_5% EN_1.8V LX PVIN LX_1.8V NC D TP PC74 22U_0805_6.3VAM LX NC JUMP_43X118 PVIN 10 @ 1 2 PL11 2.2UH_FDVE0630-H-2R2M=P3_8.3A_20% PU6 PJ22 +5VALW PC76 22U_0805_6.3VAM VID[0] 0 1 VID[1] 1 VCCSA Vout 0.9 V 0.8 V 0.75V 0.65V +VCCSAP Ipeak=6A , Imax=4.2A, 1.2Ipeak=7.2A DCR= m(typ)~10 m(max) Rlimit=12K,Rdson=15~18mohm Ilimit=10uA Iocp=Rlimit/Rdson*10^(-5)= 7.59~10.654A Require on 2011/ 2012 Required Yes/Yes Yes/Yes No/Yes No/Yes the resister change from @ to pop component Add two jumpers on the HW's output cap of the +VCCSA's PIN(+) and PIN(-) to sense the feedback voltage for VCCSA_SENSE & VSSSA_SENSE A A Note:Use VCCSA_SEL to switch High & Low Level for VID[1] (ie VCCSA_SEL) due to the VID[0] is don't care for this setting Compal Secret Data Security Classification Issued Date 2010/07/13 Deciphered Date 2011/07/13 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc PWR +VCCSAP Size C Date: Document Number Rev 0.1 P5WE0 M/B LA-6901P Schematic Friday, August 27, 2010 Sheet 51 of 59 D D PU8 NC GND NC VREF VCNTL VOUT NC TP +3VALW VIN PC90 1U_0603_10V6K 2 PR127 1K_0402_1% PC89 4.7U_0805_6.3V6K 1 +1.5V /x / +0.75VS 1 S PR129 1K_0402_1% PC93 10U_0603_6.3V6M SUSP G PQ38 2N7002W -T/R7_SOT323-3 D S PQ39 2N7002W -T/R7_SOT323-3 PC92 1U_0402_6.3V6K D G PR128 24.9K_0402_1% 43 SUSP PC91 1U_0402_16V7K APL5336KAI-TRL_SOP8P8 p su For shortage changed VDDP 10 LGATE PQ41 AO4456_SO8 PC95 4.7U_0805_25V6-K PC94 4.7U_0805_25V6-K PC178 0.1U_0603_25V7K PC179 2200P_0402_50V7K @ PC100 680P_0402_50V7K PC99 330U_6.3V_M PR134 0_0603_5% 1 15 NC 51 VCCPPW RGOOD PC102 4.7U_0805_10V6K Change PR133 from 10 to 0ohm Change PR144 from to 10ohm PR140 10_0402_5% PR139 PR138 10K_0402_1% +3VALW VCCIO_SENSE A 2 10K_0402_1% PR141 @ 10K_0402_1% + PR137 4.02K_0402_1% A PR141/PR142 must be lower than 10K ohm by Jones(DVT) 1 RT8209MGQW _W QFN14_3P5X3P5 +1.05VS_VCCP: Ipeak=15.608A;Imax=10.9256A;1.2Ipeak=18.7296A Rdson=4.5~5.6m ohm ; Freq=298KHz Rtrip=13.7Kohm,Vtrip18.7296A->OK) @ PR133 4.7_1206_5% PC101 4.7U_0603_10V6K DL_1.05VS_VCCP +5VALW PGOOD PGND GND FB B +1.05VS_VCCPP LX_1.05VS_VCCP 11 PL14 1UH_FDUE1040D-1R0M-P3_21.3A_20% B+ 12 CS PC98 0.1U_0603_25V7K PQ40 AO4466L_SO8 13 PHASE VFB=0.75V h PR135 100_0603_5% UGATE DH_1.05VS_VCCP PR132 0_0603_5% PR136 13.7K_0402_1% VDD BOOT BST_1.05VS_VCCP PL13 HCB4532KF-800T90_1812 1.05VS_51117_B+ 14 // m TON VOUT tt +5VALW p: PU9 PC97 4.7U_0603_6.3V6K 1 @ PR249 47K_0402_5% B EN/DEM PR131 680K_0402_5% 37,39,43,51 SUSP# PR130 267K_0402_1% C yc om C Compal Secret Data Security Classification 2010/07/13 Issued Date Deciphered Date 2011/07/13 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc PWR +1.05VS_VCCPP/+0.75VSP Size Document Number Custom P5WE0 M/B LA-6901P Schematic Date: Friday, August 27, 2010 Sheet 52 of 59 Rev 0.1 VGA@ PL15 FBMA-L11-322513-201LMA40T_1210 B+ B+_CORE EN SW VFB V5IN RF DRVL DH_VCORE DL_VCORE VGA@ PR147 4.7_1206_5% VGA@ PR150 0_0402_5% P0(Cold) 0.95 V 0.995V 2 2 +3VSDGPU VGA@ PC115 4700P_0402_25V7K @ PR164 10K_0402_5% @ PR165 10K_0402_5% D PQ48A VGA@ DMN66D0LDW-7_SOT363-6 +3VSDGPU G VGA@ PR166 10K_0402_5% S PQ47B VGA@ DMN66D0LDW-7_SOT363-6 1 0 G B GPU_VID1 22 0.90 V @ PR161 10K_0402_5% VGA@ PR167 10K_0402_5% S VGA@ PC114 4700P_0402_25V7K VGA@ PR162 10K_0402_5% VGA@ PR163 10K_0402_5% D +3VSDGPU P0(Hot) PR160 VGA@ 24K_0402_1% S 0.825V GCORE_SEN 24 VGA@ PR159 10K_0402_5% D PQ48B VGA@ DMN66D0LDW-7_SOT363-6 G @ PR168 10K_0402_5% GPU_VID0 22 VGA@ PR170 10K_0402_5% S A A VGA@ PR169 10K_0402_5% 1 C FB_GND PR151 VGA@ 0_0402_5% VGA@ PR158 10K_0402_5% G DMN66D0LDW-7_SOT363-6 VGA@ PQ47A // m P8/P12 VGA@ PC108 470U_V_2.5VM 24 D p: NVIDIA/N11P-GS VGA@ PR156 10K_0402_1% tt GPU_VID0 PR157 VGA@ 53.6K_0402_1% h GPU_VID1 GCORE_SEN VGA@ PC113 2200P_0402_25V7K Follow the project of NEW70 for VGA_CORE circuit B + yc om VGA_CORE F=1/(75*e-12*44.2)=300K Ipeak=33A Imax=23.1A Iocp=39.6A Iocpmin=(5.11K*26uA)/((5.6mohm/2)*1.2)=39.54A Iocpmin=39.54A + +3VSDGPU S G VGA@ PQ46 2N7002W-T/R7_SOT323-3 VGA@ PR152 10_0402_5% VGA@ PC109 680P_0603_50V7K PR153 VGA@ 4.22K_0402_1% 1 44 VGA_ON# VGA@ PC171 470U_V_2.5VM 3 p su VGA@ PC110 1U_0402_16V7K VGA@ PQ45 TPCA8028-H_SOP-ADVANCE8-5 1 2 VGA@ PC106 1U_0603_6.3V6M VGA@ PQ44 TPCA8028-H_SOP-ADVANCE8-5 VFB=0.6V ESR=10mohm TP 11 Rds=4.5m/5.6mOHM D +VGA_CORE +5VALW C PL16 0.56UH_MMD-12CE-R56M-X1A_29A_20% SW_VCORE TPS51218DSCR_SON10_3X3 VGA@ PR149 10K_0402_1% BST_VCORE VGA_ON 10 VGA@ PR148 5.11K_0402_1% @ PR146 10K_0402_5% 44 VGA_ON VBST DRVH /x / PGOOD TRIP D +3VS VGA@ PR145 4.7_0603_5% VGA@ PC105 0.1U_0603_25V7K VGA@ PR143 0_0603_5% @ PQ43 TPCA8030-H_SOP-ADV8-5 PU10 18 VGA_PWROK VGA@ PQ42 TPCA8030-H_SOP-ADV8-5 D @ PR142 10K_0402_5% 2 VGA@ PC104 10U_1206_25V6M 1 +3VS VGA@ PC103 10U_1206_25V6M Compal Secret Data Security Classification Issued Date 2010/07/13 AP 2011/07/13 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc +VGA_COREP Size Document Number Custom Date: Friday, August 27, 2010 Rev 0.1 P5WE0 Sheet 53 of 59 GFX@ PC119 10U_1206_25V6M GFX@ PC118 10U_1206_25V6M 2 PC136 @ 0.01U_0402_16V7K PR195 ISNG +CPU_CORE VSUM- 2 C 1 PR204 3.65K_0402_1% 2 PC140 @ 680P_0402_50V7K PR199 ISEN3 10K_0402_1% VSUM+ PR202 @ 4.7_1206_5% PR205 10K_0402_1% PR201 10K_0402_1% +5VS 100_0402_1% @ PR192 2 @ PC137 470P_0402_50V7K PR193 GFX@ 590_0402_1% PC139 ISPG 10U_1206_25V6M PC138 10U_1206_25V6M TPCA8030-H_SOP-ADV8-5 @ PQ55 TPCA8028-H_SOP-ADVANCE8-5 GFX@ PC123 330U_X_2VM_R6M 1 2 PR179 GFX@ @10K_0402_1% PR178 4.7_1206_5% @ PC130 680P_0402_50V7K TPCA8028-H_SOP-ADVANCE8-5 TPCA8030-H_SOP-ADV8-5 TPCA8030-H_SOP-ADV8-5 GFX@ PQ51 TPCA8028-H_SOP-ADVANCE8-5 PC145 10U_1206_25V6M PC146 10U_1206_25V6M @ PQ58 TPCA8030-H_SOP-ADV8-5 @ PR216 4.7_1206_5% 2 ISEN3 2PR220 10K_0402_1% PR246 10K_0402_1% PR219 1_0402_5% VSUM+ B PR217 10K_0402_1% 12 ISEN2 @ PQ59 TPCA8028-H_SOP-ADVANCE8-5 PL20 0.36UH_PCMC104T-R36MN1R17_30A_20% +CPU_CORE @ PC154 680P_0402_50V7K B+ PL17 HCB4532KF-800T90_1812 2011/07/13 Deciphered Date PC164 10U_1206_25V6M PC163 10U_1206_25V6M Title Compal Electronics, Inc PWR +CPU_CORE/+VGFX_CORE Size Document Number Custom P5WE0 M/B LA-6901P Schematic Date: Friday, August 27, 2010 Sheet 54 of 59 Rev 0.1 PR247 10K_0402_1% PR238 10K_0402_1% 2 A 1 PR237 1_0402_5% ISEN3 2 PR235 PR236 VSUM+ 3.65K_0402_1% 10K_0402_1% 2 ISEN1 @ PQ62 TPCA8030-H_SOP-ADV8-5 +CPU_CORE PL21 0.36UH_PCMC104T-R36MN1R17_30A_20% 2 @ PC169 680P_0402_50V7K @ PR234 4.7_1206_5% Compal Secret Data 2010/07/13 @ PQ64 TPCA8028-H_SOP-ADVANCE8-5 5 PQ63 TPCA8028-H_SOP-ADVANCE8-5 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC PC132 GFX@ 1U_0402_16V7K + 1U_0402_16V7K GFX@ PC133 2 ISEN2 PH4 GFX@ 10K_0402_5%_TSM0A103J4302RE 7.5K_0402_1% PR184 GFX@ GFX@ 11K_0402_1% PR187 VSUM- Issued Date PC168 0.22U_0603_10V7K Security Classification *OCP setting value=37A PQ57 TPCA8030-H_SOP-ADV8-5 5 0_0603_5% PR233 LGATE1 A *OCP setting value=71.5A PQ60 TPCA8028-H_SOP-ADVANCE8-5 PHASE1 Ipeak=26A , Imax=18.2A , 1.2Ipeak=31.2A Rdson=3.6~4.5m ohm DCR=1.1m ohm HW output cap: (1)22U_0805_6.3V *12 (2)470U_D2_2V *2(ESR=4.5m ohm) PQ61 TPCA8030-H_SOP-ADV8-5 PR223 12 BOOT1 +VGFX_COREP PQ56 TPCA8028-H_SOP-ADVANCE8-5 3 1 UGATE1 *Iccmax in Turbo Mode for SV (35W) is 53A Icc-max=53A Rdson=3.6~4.5m ohm DCR=1.1m ohm HW output cap: (1)10U_0805_4V *10 (2)22U_0805_6.3V *15 (3)470U_D2_2V *4(ESR=4.5m ohm) PR180 GFX@ 1_0402_5% 1 D VSUM- PC160 @ 0.068U_0402_16V7K PR227 11K_0402_1% 0.33U_0603_10V7K @ PR231 100_0402_1% OPT@ 0_0402_5% PL19 0.36UH_PCMC104T-R36MN1R17_30A_20% CPU_B+ PH6 10KB_0603_5%_ERTJ1VR103J PC167 1 @ PC166 330P_0402_50V7K +CPU_CORE 4 2 2.61K_0402_1% 1U_0603_10V6K PC151 DC@ PR229 698K_0402_1% PC149 0.22U_0603_10V7K LGATE2 1U_0402_16V7K 1 PC165 1000P_0402_50V7K BOOT2 0_0603_5% PR214 12 VSUM+ PR232 10_0402_1% QC@ PR229 1.24K_0402_1% PC161 330P_0402_50V7K PHASE2 0.22U_0603_25V7K PC159 1 PR228 2.15K_0402_1% 10_0402_1% VCCSENSE @ PR248 2K_0402_1% VSSSENSE @ PC180 100P_0402_50V8J PC152 tt DC@ PR225 h PR224 412K_0402_1% +CPU_CORE QC@ PR225 3.83K_0402_1% ISEN1 PC157 0.22U_0402_6.3V6K 470P_0402_50V7K PC158 150P_0402_50V8J 0.22U_0402_6.3V6K 1_0603_5% p: PC153 PC156 330P_0402_50V7K 499K_0402_1% VSUM- PC162 PR222 499_0402_1% +5VS (Vboot=0) +VGFX_COREP ISEN1 PC150 ISEN2 0.22U_0402_6.3V6K PR215 VSUM- 2 DC@ PR212 4.32K_0402_1% (Ipeak=56A) PC148 @ 22P_0402_50V8J ISEN3 PC147 1000P_0402_50V7K PR221 CPU_B+ 0_0603_5% PC155 33P_0402_50V8J PR211 B @ // m 8.06K_0402_1% PR213 change for shortage problem 2010-03-15 PC143 47P_0402_50V8J from 43P to 47P PH5 470K_0402_5%_TSM0B474J4702RE PR210 27.4K_0402_1% CPU_B+ UGATE2 3.83K_0402_1% 5 QC@ PR212 590_0402_1% PU12 26BOOT1 @PQ54 @ PQ54 /x / p su PHASE1 UGATE1 25 PQ53 TPCA8030-H_SOP-ADV8-5 PC131 0.22U_0603_10V7K 2 LGATE1 2 0_0402_5% 30 28 PC142 2.2U_0603_10V6K VIN LGATE 4 GFX@ PL18 0.36UH_PCMC104T-R36MN1R17_30A_20% CPU_B+ @ 0_0402_5% PR200 29 27 PROG1 GND +5VS LGATE2 PH1 24 23 1U_0603_10V6K PC129 21 22 19 20 18 17 16 15 13 14 PHASE yc om UGATE PWM 1PR198 33 VSSP1 BOOT1 FCCM PHASE2 VDDP LG1 BOOT 35 470P_0402_50V7K PR186 0_0603_5% 34 32 UG1 ISUMP VW VDD NTC RTN 11 ISUMN VR_HOT# VSEN IMON UGATE2 31 ISL95831CRZ-T_TQFN48_6X6 ISEN1 PGND ISL6208ACRZ-T_QFN8_3X3 36 LG2 PWM3 10 PR209 1 37 LGG 39 38 PHG UGG 40 41 PROG2 BOOTG 42 43 ISNG NTCG VSSP2 PGOOD 12 2 PC125 GFX@ PH2 VR_ON PC144 @ PR185 0_0402_5% LGATEG PHASEG UGATEG BOOTG ISNG ISPG 45 46 47 44 ISPG RTNG VSENG 48 UG2 PR194 0_0402_5% BOOT2 BOOT2 VCC @ PQ52 0.22U_0603_10V7K GFX@ LGATEG PU11 PGOODG ISEN2 GFX@ PR183 10_0402_1% 0_0603_5% GFX@ VSS_AXG_SENSE PR189 @ 16.5K_0402_1% SCLK For shortage changed PR208 499_0402_1% +1.05VS_VCCPP @ 330P_0402_50V7K PC127 GFX@ 1000P_0402_50V7K IMONG ISEN3/ FB2 PC141 0.047U_0603_16V7K 0_0402_5% VR_HOT# BOOTG +5VS PC122 B+ PL24 HCB4532KF-800T90_1812 ISEN2 PR206 19.1K_0402_1% PR203 PR175 VCC_AXG_SENSE ALERT# VR_ON PC121 GFX@ SDA 15,39 FBG 49 SVID_ALERT# 39 GFX@ PR174 10_0402_1% @ PQ50 ISEN1 39 GND SVID_SDA SVID_SCLK IMVP_IMON VWG GFX_CORE_PWRGD COMPG COMP VGATE VSSSENSE PHASEG FB PR197 1.91K_0402_1% C +VGFX_COREP NTCG VR_SVID_CLK 39 PR196 GFX@ 1.91K_0402_1% VR_SVID_DAT UGATEG +3VS VR_SVID_ALRT# +3VS PR191 54.9_0402_1% For shortage changed Parallel and tune length PC124 GFX@ 680P_0402_50V7K +1.05VS_VCCPP 130_0402_1% PR190 GFX@ PR188 18.2K_0402_1% VSS_AXG_SENSE + 2 GFX@ PR182 2.55K_0402_1% PC135 @ 1U_0402_16V7K GFX@ PC134 0.047U_0603_16V7K GFXVR_IMON GFX@ PQ49 PR173 @ 27.4K_0402_1% GFX@ PR177 422_0402_1% PC128 GFX@ 150P_0402_50V8J 2 PR181 GFX@ 475K_0402_1% B+ PR176 @ 499K_0402_1% NTCG 330P_0402_50V7K PC120 GFX@ 1000P_0402_50V7K PR172 GFX@ 8.06K_0402_1% 1 GFX_B+ 470P_0402_50V7K @PR171 @ PR171 3.83K_0402_1% PH3 2 @ DNP_470K_ERT-J0EV474J D PC126 GFX@ 39P_0402_50V7K 2 PR207 1_0402_5% PC116 @ PR218 3.65K_0402_1% PC117 220U_25V_M Alert# PU resister need close CPU, so the PU resister in HW schematic but DAT and CLK need close PWM-IC, so the PU resister in POWER schematic 9HUVLRQFKDQJHOLVW 3,5/LVW ,WHP )L[HG,VVXH 3DJHRI IRU3:5 5HDVRQIRUFKDQJH 5HY3* 'DWH 0RGLI\/LVW 3KDVH D D OVP problem with PWR and HW side If the HW side is 0V, through the jumper will cause the sense pin to over the votage setting and it may happen OVP problem 0.1 0.1 P.55 /x / IF the PWM3 no used, please pull high it for +5VS and not floating Change the +VGFX_CORE to +VGFX_COREP 2010-03-29 DVT 2010-03-29 DVT p su Shut down for PWM3 pin floating (1)Add PR638(0_0603_5%) between PWM3 and +5VS P.55 (2)connect the ISNG to +5VS C B p: h tt B // m yc om C COMPAL ELECTRONICS A Title PIR POWER1 Size A Date: A Document Number Rev PAW00(LA-6361P) Friday, August 27, 2010 0.1 Sheet 55 of 59 VR_ON (PU1000) ISL6266ACRZ-T +CPU_CORE +1.5VS_DMC D D TQFN48 (PU998) APW7138NITRL SYSON VS_ON BATTERY (SUSP#) VCCPWRGOOD Page 44 (PU5) RT8209BGQW SUSP +1.5V Page 51 (PU6) RT8209BGQW WQFN14 U38 +VCCSA Page 49 (PU3) RT8205EGQW Page 49 yc om WQFN24 SUSP SYSON# SO8 (U46) TPS2062ADR Page 44 DFN10 (U14) SI4800BDY Page 51 SO8 +3VALW +3VALW_PCH R599 +HDMI_5V_OUT (RE1) (U68) SI4800BDY (UB1) RT9701-PB SO8 SOT23-5 Page 44 Page 45 B +3V_LAN (U39) BCM57780 h +CRT_VCC SUSP SUSP Page 44 p: +1.8VS tt +USB_VCCB C PCH_PWR_EN# SUSP (PU6) SY8033BDBC B +5VS // m +5VALW (U49) SI4800BDY +CLK_1.05VS +1.05VSDGPU (PU3) RT8205EGQW WQFN24 +0.75VS L76 +1.05VS_PCH Page 53 +1.5VSDGPU Page 44 Page 53 PJP25 +1.05V_VCCP (U40) AO4430L SO8 (PU8) APL5331KAC-TRL SO8 C CHARGER VGA_ON# +1.5VS Page 54 WQFN14 B+ (U13) SI4800BDY-T1-GE3 /x / SSOP16 ADAPTER SUSP +VGA_CORE p su VGA_ON Page 55 +3VALW_EC +3V +3VS ENVDD ENVDD (Q51) AO3413L SO23-3 +3VS_CK505 Page 37 +1.2V_LAN VGA_ON (Q30) AO3413L (Q34) AO3413L SO23-3 SO23-3 Page 30 Page 24 +DVDD_AUDIO +BT_VCC +LCDVDD +3VSDGPU +5VS_HDD1 +3V_WLAN +5VS_ODD +3V_DMC A A +5VAMP +VDDA Compal Secret Data Security Classification Issued Date 2010/08/11 2011/08/11 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc Power Rail Size Document Number Custom Date: Rev 0.1 P5WE0 M/B LA-6901P Schematic Sheet Friday, August 27, 2010 56 of 59 D D A3 PU3 +3VALW A5 B7 V B4 8a (DIS) VGA_ON V V +1.5VSDGPU U40 U68 +3VS +1.8VSDGPU U37 U13 +1.5VS PU8 +0.75V V 11 VGATE VGA B +1.05VSDGPU U38 +VGA_CORE PU998 PU7 +VCCSA PU9 +1.05VS_VCCP V V U49 +5VS +3VSDGPU Q6 VCCPPWRGOOD V h tt V p: B V // m SUSP#,SUSP V DGPU_PWR_EN +1.5V PU5 V yc om SYSON# C V CPU V V V SYSON 15 V V ON/OFF PLT_RST# 14 V B6 H_CPUPWRGD V PM_SLP_S3# PM_SLP_S4# PM_SLP_S5# PM_SLP_A# PM_SLP_SUS# C A4 PBTN_OUT# V B7 13 PM_DRAM_PWRGD V A5 EC_ON PCH V V V B3 51ON# SYS_PWROK PCH_RSMRST# /x / EC PQ2 V V V B+ V B2 +3VALW_PCH +5VALW_PCH p su B1 V BATT U14,+3VALW_PCH QH4,+5VALW_PCH B5 V B+ V V A2 PU2 VV VIN V V BATT MODE A1 V AC MODE V PCH_PWR_EN# VGA_PWROK 8b (DIS) U47 CK505 V V VR_ON PU1000 +CPU_CORE 10 A A Compal Secret Data Security Classification Issued Date 2010/08/11 2011/08/11 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc Power sequence Size Document Number Custom Rev 0.1 P5WE0 M/B LA-6901P Schematic Date: Sheet Friday, August 27, 2010 57 of 59 V ersion Change L ist ( P I R L ist ) Item Page# Title D ate R equest O w ner Page Solution D escription Issue D escription R ev D p su /x / D C // m yc om C B h tt p: B A A Compal Secret Data Security Classification Issued Date 2010/08/11 2011/08/11 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc EE P.I.R (1) Size Document Number Custom Rev 0.1 P5WE0 M/B LA-6901P Schematic Date: Sheet Friday, August 27, 2010 58 of 59 ... CR_CLK/XD_RY_BY# R190 +LAN_XTALVDDH 66 D 20mil LAN_MIDI1- 36 LAN_MIDI1+ 36 LAN_MIDI0LAN_MIDI0+ C666 LAN_MIDI2- 36 LAN_MIDI2+ 36 LAN_MIDI1LAN_MIDI1+ 41 40 C662 LAN_MIDI3- 36 LAN_MIDI3+ 36 LAN_MIDI2LAN_MIDI2+... RJ45_MIDI2+ RJ45_MIDI2- 35 35 LAN_MIDI1+ LAN_MIDI1- LAN_MIDI1+ LAN_MIDI1- TCT3 TD3+ TD3- MCT3 MX3+ MX3- 18 17 16 RJ45_MIDI1+ RJ45_MIDI1- LAN_MIDI0+ LAN_MIDI0- LAN_MIDI0+ LAN_MIDI0- 10 11 12 TCT4 TD4+... Size Document Number Custom P5WE0 M/B LA- 6901P Schematic Date: Friday, August 27, 2010 Sheet 35 of 59 Rev 0.1 LAN Connector T28 LAN_MIDI2+ LAN_MIDI2- LAN_MIDI2+ LAN_MIDI2- TCT2 TD2+ TD2- MCT2 MX2+