Logic kỹ thuật số thử nghiệm và mô phỏng P5

233 Digital Logic Testing and Simulation , Second Edition , by Alexander Miczo ISBN 0-471-43995-9 Copyright © 2003 John Wiley & Sons, Inc. CHAPTER 5 Sequential Logic Test 5.1 INTRODUCTION The previous chapter examined methods for creating sensitized paths in combina- tional logic extending from stuck-at faults on logic gates to observable outputs. We now attempt to create tests for sequential circuits where the outputs are a function not just of present inputs but of past inputs as well. The objective will be the same: to create a sensitized path from the point where a fault occurs to an observable out- put. However, there are new factors that must be taken into consideration. A sensi- tized path must now be propagated not only through logic operators, but also through an entirely new dimension—time. The time dimension may be discrete, as in synchronous logic, or it may be continuous, as in asynchronous logic. The time dimension was ignored when creating tests for faults in combinational logic. It was implicitly assumed that the output response would stabilize before being measured with test equipment, and it was generally assumed that each test pat- tern was independent of its predecessors. As will be seen, the effects of time cannot be ignored, because this added dimension greatly influences the results of test pat- tern generation and can complicate, by orders of magnitude, the problem of creating tests. Assumptions about circuit behavior must be carefully analyzed to determine the circumstances under which they prevail. 5.2 TEST PROBLEMS CAUSED BY SEQUENTIAL LOGIC Two factors complicate the task of creating tests for sequential logic: memory and circuit delay. In sequential circuits the signals must not only be logically correct, but must also occur in the correct time sequence relative to other signals. The test prob- lem is further complicated by the fact that aberrant behavior can occur in sequential circuits when individual discrete components are all fault-free and conform to their manufacturer’s specifications. We first consider problems caused by the presence of memory, and then we examine the effects of circuit delay on the test generation problem. 234 SEQUENTIAL LOGIC TEST 5.2.1 The Effects of Memory In the first chapter it was pointed out that, for combinational circuits, it was possible (but not necessarily reasonable) to create a complete test for logic faults by applying all possible binary combinations to the inputs of a circuit. That, as we shall see, is not true for circuits with memory. They may not only require more than 2 n tests, but are also sensitive to the order in which stimuli are applied. Test Vector Ordering The effects of memory can be seen from analysis of the cross-coupled NAND latch [cf. Figure 2.3(b)]. Four faults will be considered, these being the input SA1 faults on each of the two NAND gates (numbering is from top to bottom in the diagram). All four possible binary combinations are applied to the inputs in ascending order—that is, in the sequence (Set , Reset) = {(0,0), (0,1), (1,0), (1,1)}. We get the following response for the fault-free circuit (FF) and the circuit corresponding to each of the four input SA1 faults. In this table, fault number 2 responds to the sequence of input vectors with an output response that exactly matches the fault-free circuit response. Clearly, this sequence of inputs will not distinguish between the fault-free circuit and a circuit with input 2 SA1. The sequence is now applied in the exact opposite order. We get: The Indeterminate Value When the four input combinations are applied in reverse order, question marks appear in some table positions. What is their signifi- cance? To answer this question, we take note of a situation that did not exist when dealing only with combinational logic; the cross-coupled NAND latch has memory . By virtue of feedback present in the circuit, it is able to remember the value of a sig- nal that was applied to the set input even after that signal is removed. Input Output Set Reset FF1234 0 0 10111 0 1 10111 1 0 00001 1 1 00011 Input Output Set Reset FF1234 11??01? 1 0 0000? 0 1 10111 0 0 10111 TEST PROBLEMS CAUSED BY SEQUENTIAL LOGIC 235 Because of the feedback, neither the Set nor the Reset line need be held low any longer than necessary to effectively latch the circuit. However, when power is first applied to the circuit, it is not known what value is contained in the latch. How can circuit behavior be simulated when it is not known what value is contained in its memory? In real circuits, memory elements such as latches and flip-flops have indetermi- nate values when power is first applied. The contents of these elements remain indeterminate until the latch or flip-flop is either set or reset to a known value. In a simulation model this condition is imitated by initializing circuit elements to the indeterminate X state. Then, as seen in Chapter 2, some signal values can drive a logic element to a known state despite the presence of indeterminate values on other inputs. For example, the AND gate in Figure 2.1(c) responds with a 0 when any single input receives a 0, regardless of what values are present on other inputs. However, if a 1 is applied while all other inputs are at X, the output remains at X. Returning to the latch, the first sequence began by applying 0s to both inputs, while the second sequence began by applying 1s to both inputs. In both cases the internal nets were initially indeterminate. The 0s in the first sequence were able to drive the latch to a known state, making it possible to immediately distinguish between correct and incorrect response. When applying the patterns in reverse order, it took longer to drive the latch into a state where good circuit response could be dis- tinguished from faulty circuit response. As a result, only one of the four faults is detected, namely, fault 1. Circuits with faults 2 and 3 agree with the good circuit response in all instances where the good circuit has a known response. On the first pattern the good circuit response is indeterminate and the circuit with fault 2 responds with a 0. The circuit with fault 3 responds with a 1. Since it is not known what value to expect from the good circuit, there is no way to decide whether the faulted circuits are responding correctly. Faulted circuit 4 presents an additional complication. Its response is indetermi- nate for both the first and second patterns. However, because the good circuit has a known response to pattern 2, we do know what to look for in the good circuit, namely, the value 0. Therefore, if a NAND latch is being tested with the second set of stimuli, and it is faulted with input 4 SA1, it might come up initially with a 0 on its output when power is applied to the circuit, in which case the fault is not detected, or it could come up with a 1, in which case the fault will be detected. Oscillations Another complication resulting from the presence of memory is oscillations. Suppose that we first apply the test vector (0,0) to the cross-coupled NAND latch. Both NAND gates respond with a logic 1 on their outputs. We then apply the combination (1,1) to the inputs. Now there are 1s on both inputs to each of the two NAND gates—but not for long. The NAND gates transform these 1s into 0s on the outputs. The 0s then show up on the NAND inputs and cause the NAND out- puts to go to 1s. The cycle is repetitive; the latch is oscillating. We do not know what value to expect on the NAND gate outputs; the latch may continue to oscillate until a different stimulus is applied to the inputs or the oscillations may eventually subside. 236 SEQUENTIAL LOGIC TEST If the oscillations do subside, there is no practical way to predict, from a logic description of the circuit, the final state into which the latch settles. Therefore, the NAND outputs are set to the indeterminate X. Probable Detected Faults When we analyzed the effectiveness of binary sequences applied to the NAND latch in descending order, we could not claim with certainty that stuck-at fault number 4 would be detected. Fortunately, that fault is detected when the vectors are applied in ascending order. In other circuits the ambi- guity remains. In Figure 2.4(b) the Data input is complemented and both true and complement values are applied to the latch. Barring the presence of a fault, the latch will not oscillate. However, when attempting to create a test for the circuit, we encounter another problem. If the Enable signal is SA1, the output of the inverter driven by Enable is permanently at 0 and the NAND gates driven by the inverter are permanently in a 1 state; hence the faulted latch cannot be initialized to a known state. Indeterminate states were set on the latch nodes prior to the start of test pattern generation and the states remain indeterminate for the faulted circuit. If power is applied to the fault-free and faulted latches, the circuits may just happen to come up in the same state. The problem just described is inherent in any finite-state machine (FSM). The FSM is characterized by a set of states Q = { q 1 , q 2 , ., q s }, a set of input stimuli I = { i 1 , i 2 , ., i n }, another set Y = { y 1 , y 2 , ., y m } of output responses, and a pair of mappings M : Q × I → Q Z : Q × I → Y These mappings define the next state transition and the output behavior in response to any particular input stimulus. These mappings assume knowledge of the current state of the FSM at the time the stimulus is applied. When the initial stimulus is applied, that state is unknown unless some independent means such as a reset exists for driving the FSM into a known state. In general, if there is no independent means for initializing an FSM, and if the Clock or Enable input is faulty, then it is not possible to apply just a single stimu- lus to the FSM and detect the presence of that fault. One approach used in industry is to mark a fault as a probable detect if the fault-free circuit drives an output pin to a known logic state and the fault causes that same pin to assume an unknown state. The industry is not in complete agreement concerning the classification of proba- ble detected faults. While some test engineers maintain that such a fault is likely to eventually become detected, others argue that it should remain classified as undetec- ted, and still others prefer to view it as a probable detect. If the probable detected fault is marked as detected, then there is a concern that an ATPG may be designed to ignore the fault and not try to create a test for it in those situations where a test exists. TEST PROBLEMS CAUSED BY SEQUENTIAL LOGIC 237 Figure 5.1 Initialization problem. The Initialization Problem Consider the circuit of Figure 5.1. During simula- tion, circuit operation begins with the D flip-flop in an unknown state. In normal operation, when the input combination A = B = C = 0 is applied and the flip-flop is clocked, the Q output switches to 0. The flip-flop can then be clocked a second time to obtain a test for the lower input of gate 3 SA1. If it is SA1, the expected value is Q = 1; and if it is fault-free, the expected value is Q = 0. Unfortunately, the test has a serious flaw! If the lower input to gate 3 is SA1, the output of the flip-flop at the end of the first clock period is indeterminate because the value at the middle input to gate 3 is initially indeterminate. It is driven by the flip- flop that has an indeterminate value. After a second clock pulse the value at Q will remain at X; hence it may agree with the good circuit response despite the presence of the fault. The fallacy lies in assuming correct circuit behavior when setting up the flip-flop for the test. We depended upon correct behavior of the very net that we are attempting to test when setting up a test to detect a fault on that net. To correctly establish a test, it is necessary to assume an indeterminate value from the flip-flop. Then, from the D-algorithm, we know that the flip-flop must be driven into the 0 state, without depending on the input to gate 3 that is driven by the flip- flop. The flip-flop value can then be used in conjunction with the inputs to test for the SA1 on the lower input of gate 3. In this instance, we can set A = C = 0, B = 1. Then a 1 can be clocked into the flip-flop from gate 2. This produces a 0 on the out- put of the flip-flop which can then be used with the assignment A = B = 0 to clock a 0 into the flip-flop. Now, with Q = 0 and A = B = C = 0, another clock causes D to appear on the output of the flip-flop. Notice that input C was used, but it was used to set up gate 2. If input C were faulted in such a way as to affect both gates 2 and 3, then it could not have been used to set up the test. 5.2.2 Timing Considerations Until now we have assumed that erroneous behavior on circuit outputs was the result of logic faults. Those faults generally result from actual physical defects such as opens or shorts, or incorrect fabrication such as an incorrect connection or a wrong Q A B C 1 2 3 4 D F Clock AF 0 C 0 Q 1 Q 10 SA1 B 0 1 0 1 238 SEQUENTIAL LOGIC TEST component. Unfortunately, this assumption, while convenient, is an oversimplifica- tion. An error may indeed be a result of one or more logic faults, but it may also be the case that an error occurs and none of the above situations exists. Defects exist that can prevent an element from behaving in accordance with its specifications. Faults that affect the performance of a circuit are referred to as para- metric faults, in contrast to the logic faults that have been considered up to this point. Parametric faults can affect voltage and current levels, and they can affect gain and switching speed of a circuit. Parametric faults in components can result from improper fabrication or from degradation as a consequence of a normal aging process. Environmental conditions such as temperature extremes, humidity, or mechanical vibration can accelerate the degradation process. Design oversights can produce symptoms similar to parametric faults. Design problems include failure to take into account wire lengths, loading of devices, inad- equate decoupling, and failure to consider worst-case conditions such as maximum or minimum voltages or temperatures over which a device may be required to oper- ate. It is possible that none of these factors may cause an error in a particular design in a well-controlled environment, and yet any of these factors can destabilize a cir- cuit that is operating under adverse conditions. Relative timing between signal paths or the ability of the circuit to drive other circuits could be affected. Intermittent errors are particularly insidious because of their rather elusive nature, appearing only under particular combinations of circumstances. For exam- ple, a logic board may be designed for nominal signal delay for each component as a safety margin. Statistically, the delays should seldom accumulate so as to exceed a critical threshold. However, as with any statistical expectation, there will occasion- ally be a circuit that does exceed the maximum permissible value. Worse still, it may work well at nominal voltages and /or temperatures and fail only when voltages and/ or temperatures stray from their nominal value. A new board substituted for the orig- inal board may be closer to tolerance and work well under the degraded voltage and/ or temperature conditions. The original board may then, when checked at a depot or a board tester under ideal operating conditions, test satisfactorily. Consider the effects of timing variations on the delay flip-flop of Figure 2.7. Cor- rect operation of the flip-flop requires that the designer observe minimal setup and hold times. If propagation delay along a signal path to the Data input of the flip-flop is greater than estimated by the designer, or if parametric faults exist, then the setup time requirement relative to the clock may not be satisfied, so the clock attempts to latch the signal while it is still changing. Problems can also occur if a signal arrives too soon. The hold time requirement will be violated if a new signal value arrives at the data input before the intended value is latched up in the flip-flop. This can hap- pen if one register directly feeds another without any intervening logic. That logic or parametric faults can cause erroneous operation in a circuit is easy to understand, but digital test problems are further compounded by the fact that errors can occur during operation of a device when its components behave as intended. Elements used in the fabrication of digital logic circuits contain delay. Ironically, although technologists constantly try to create faster circuits and reduce delay, sequential logic circuits cannot function without delay; circuits depend both SEQUENTIAL TEST METHODS 239 on correct logic operation of circuit components and on correct relative timing of signals passing through the circuit. This delay must be taken into account when designing and testing circuits. Suppose the inverter driven by the Data input in the gated latch circuit of Figure 2.4(b) has a delay of n nanoseconds. If the Data input makes a 0-to-1 transi- tion followed by a 0-to-1 transition on the Enable approximately n nanoseconds later, the two cross-coupled NAND gates see an input of (0,0) for about n nanosec- onds followed by an input of (1,1). This produces unpredictable results, as we have seen before. The problem is caused by the delay in the inverter. A solution to this problem is to put a buffer in the noninverting signal path so the Data and Data sig- nals reach the NANDs at about the same time. In each of the two circuits just cited, the delay flip-flop and the latch, a race exists. A race is a condition wherein two or more signals are changing simulta- neously in a circuit. The race may be caused by multiple simultaneous input signal changes, or it may be the result of a single signal change that follows two or more paths from a fanout point. Note that any time we have a latch or flip-flop we have a race condition, since these devices will always have at least one element whose sig- nal both goes outside the device and feeds back to an input of the latch or flip-flop. Races may or may not affect the behavior of a circuit. A critical race exists if the behavior of a circuit depends on the outcome of the race. Such races can produce unanticipated and unwanted results. Hazards can also cause sequential circuits to behave in ways that were not intended. In Section 2.6.4 the consequences of several kinds of hazards were con- sidered. Like timing problems, hazards can be extremely difficult to diagnose because their effect on a circuit may depend on other factors, such as marginal volt- ages or an operating temperature that is within specification but borderline. Under optimal conditions, a glitch caused by a hazard may not contain enough energy to cause a latch to switch state; but under the influence of marginal operating condi- tions, this glitch may have sufficient energy to cause a latch of flip-flop to switch states. 5.3 SEQUENTIAL TEST METHODS We now examine some methods that have been developed to create tests for sequen- tial logic. The methods described here, though not a complete survey, are representa- tive of the methods described in the literature and range from quite simple to very elaborate. To simplify the task, we will confine our attention in this chapter to errors caused by logic faults. Intermittent errors, such as those caused by parametric faults or races and hazards, will be discussed in subsequent chapters. 5.3.1 Seshu’s Heuristics Some of the earliest documented attempts at automatically generating test pro- grams for digital circuits were published in 1965 by Sundaram Seshu. 1 These 240 SEQUENTIAL LOGIC TEST made use of a collection of heuristics to generate trial patterns or sequences of pat- terns that were then simulated in order to evaluate their effectiveness. Seshu identi- fied four heuristics for creating test patterns. The test patterns created were actually trial test patterns whose effectiveness was evaluated with the simulator. If the simulator indicated that a given pattern was ineffective, the pattern was rejected and another trial pattern was selected and evaluated. The four heuristics employed were Best next or return to good Wander Combinational Reset We briefly describe each of these: Best Next or Return to Good The best next or return to good begins by selecting an initial test pattern, perhaps one that resets the circuit. Then, given a ( j − 1)st pattern, the j th pattern is determined by simulating all next patterns, where a next pattern is defined as any pattern that differs from the present pattern in exactly one bit position. The next pattern that gives best results is retained. Other patterns that give good results are saved in a pushdown stack. If no trial pattern gives satisfactory results at the j th step, then the heuristic selects some other ( j − 1)st pattern from the stack and tries to generate the j th vector from it. If all vectors in the stack are discarded, the heuristic is terminated. A pattern may give good results when initially placed on the stack but no longer be effective when simulating a sequential circuit because of the feedback lines. When the pat- tern is taken from the stack, the circuit may be in an entirely different state from that which existed when the pattern was placed on the stack. Therefore, it is nec- essary to reevaluate the pattern to determine whether it is still effective. Wander The wander heuristic is similar to the best next in that the (j − 1)st vec- tor is used to generate the jth by generating all possible next vectors. However, rather than maintain a stack of good patterns, if none of the trial vectors is accept- able, the heuristic “wanders” randomly. If there is no obvious choice for next pat- tern, it selects a next pattern at random. After each step in the wander mode, all next patterns are simulated. If there is no best next pattern, again wander at random and try all next patterns. After some fixed number of wander steps, if no satisfactory next pattern is found, the heuristic is terminated. Combinational The combinational heuristic ignores feedback lines and attempts to generate tests as though the circuit were strictly combinational logic by using the path sensitization technique (Seshu’s heuristics predate the D-algorithm). The pattern thus developed is then evaluated against the real circuit to determine if it is effective. SEQUENTIAL TEST METHODS 241 Reset The reset heuristic required maintaining a list of reset lines. This strategy toggles some subset of the reset lines and follows each such toggle by a fixed num- ber of next steps, using one of the preceding methods, to see if any useful informa- tion is obtained. The heuristics were applied to some rather small circuits, the circuit limits being 300 gates and no more than 48 each of inputs, outputs, and feedback loops. Addi- tionally, the program could handle no more than 1000 faults. The best next or return to good was reported to be the most effective. The combinational was effective pri- marily on circuits with very few feedback loops. The system had provisions for human interaction. The test engineer could manually enter test patterns that were then fault simulated and appended to the automatically generated patterns. The heu- ristics were all implemented under control of a single control program that could invoke any of them and could later call back any of the heuristics that had previously been terminated. 5.3.2 The Iterative Test Generator The heuristics of Seshu are easy to implement but not effective for highly sequen- tial circuits. We next examine the iterative test generator (ITG) 2,3 which can be viewed as an extension to Seshu’s combinational heuristic. Whereas Seshu treats a mildly sequential circuit as combinational by ignoring feedback lines, the iterative test generator transforms a sequential circuit into an iterative array by means of loop-cutting. This involves identifying and cutting feedback lines in the computer model of the circuit. At the point where these cuts are made, pseudo-inputs SI and pseudo-outputs SO are introduced so that the circuit appears combinational in nature. The new circuit C contains the pseudo-inputs and pseudo-outputs as well as the original primary inputs and primary outputs. This circuit, in Figure 5.2, is repli- cated p times and the pseudo-outputs of the ith copy are identified with the pseudo- inputs of the (i + 1)st copy. The ATPG is applied to circuit C consisting of the p copies. A fault is selected in the jth copy and the ATPG tries to generate a test for the fault. If the ATPG assigns a logic value to a pseudo-input during justification, that assignment must be justified in the (j − 1)st copy. However, the ATPG is restricted from assigning values to the pseudo-inputs of the first copy. These pseudo-inputs must be assigned the X state. The Figure 5.2 Iterative Array. . . . C 1 . PIs POs . . . C p PIs POs . . . C 2 PIs POs . . . . C p−1 PIs POs X X Feedback Lines . . . C j PIs POs . 242 SEQUENTIAL LOGIC TEST objective is to create a self-initializing sequence—that is, one in which all require- ments on feedback lines are satisfied without assuming the existence of known val- ues on any feedback lines at the start of the test sequence for a given fault. From the jth copy, the ATPG tries to propagate a D or D forward until, in some copy C m , m ≤ p, the D or D reaches a primary output or the last copy C p is reached, in which case the test pattern generator gives up. The first step in the processing of a circuit is to “cut” the feedback lines in the cir- cuit model. To assist in this process, weights are assigned to all nets, subject to the rule that a net cannot be assigned a weight until all its predecessors have been assigned weights, where a predecessor to net n is a net connected to an input of the logic element that drives net n. The weights are assigned according to the following procedure: 1. Define for each net an intrinsic weight IW equal to its fanout minus 1. 2. Assign to each primary input a weight W = IW. 3. If weights have been assigned to all predecessors of a net, then assign a weight to that net equal to the sum of the weights of its predecessors plus its intrinsic weight. 4. Continue until all nets that can be weighted have been weighted. If all nets are weighted, the procedure is done. If there are nets not yet weighted, then loops exist. The weighting process cannot be completed until the loops are cut, but in order to cut the loops they must first be identified and then points in the loops at which to make the cuts must be identified. For a set of nets S, a subset S 1 of nets of S is said to be a strongly connected com- ponent (SCC), of S if: 1. For each pair of nets l, m in S 1 there is a directed path connecting l to m. 2. S 1 is a maximal set. To find an SCC, select an unweighted net n and create from it two sets B(n) and F(n). The set B(n) is formed as follows: (a) Set B(n) initially equal to {n} ∪ {all unweighted predecessors of n}. (b) Select m ∈ B(n) for some m not yet processed. (c) Add to B(n) the unweighted predecessors of m not already contained in B(n). (d) If B(n) contains any unprocessed elements, return to step b. Set F(n) is formed similarly, except that it is initially the union of n and its unweighted successors, where the successors of net m are nets connected to the out- puts of gates driven by m. When selecting an element m from F(n) for processing, its unweighted and previously unprocessed successors are added to F(n). The intersec- tion of B(n) and F(n) defines an SCC. [...]... blocks Determine D-cubes for each of these super logic blocks 2 Trace super logic block D-cubes to define sequential D-chains that define sequential circuit propagation paths 3 Determine an exercise sequence for each sequential logic D-chain 4 Determine an initialization sequence for each sequential logic D-chain In the first step, after defining the super logic blocks as described earlier and developing... described earlier and developing D-cubes for the basic memory elements, this information is used to 254 SEQUENTIAL LOGIC TEST develop D-cubes for the super logic blocks by extending the basic memory element D-cubes through the preceding combinational logic In the second step, beginning with a super logic block D-cube that generates an observable circuit output, proceed as in the D-algorithm to chain D-cubes... C X 1 1 0 X D X 1 0 X X E X 1/0 1/0 1/0 1/0 F X X 1 1 1 SEQUENTIAL LOGIC TEST COMPLEXITY A general solution to the test problem for sequential logic has proven elusive Recall that several algorithms exist that can find a test for any fault in a combinational circuit, 260 SEQUENTIAL LOGIC TEST if a test exists, given only a list of the logic elements used in the circuit and their interconnections No comparable... rules, are subsumed into an expanded set of symbols and rules for creating chains that transcend time All combinational logic in the cone (cf Section 3.6.2) of a flip-flop or latch is gathered up and combined with the destination flip-flop to create a super flip-flop Similarly, all combinational logic in the cone of a primary output is treated as a super output block State transition properties, including extended... high The S–R latch and flip-flop Y have no combinational logic preceding them The JK flipflop labeled V is preceded by an OR gate, two inverters, and two AND gates These gates and flip-flop V are bundled together and processed as a single super A S B U R C J K Set V J Set K D E F Figure 5.7 Circuit for sequential path sensitization Y Z 256 SEQUENTIAL LOGIC TEST TABLE 5.7 Super Flip-Flop Cubes Z U V Y A B... identified that extend a sensitized path back from output Z to primary inputs and other elements Before continuing, we point out that the sensitized path extends through both logic and time, since the cubes impose switching conditions as well as logic values As a result, intersections are more complex and require attention to more detail than is the case with the D-algorithm Some cubes must be intersected in... requirements can be satisfied with signal S1 If one path requires G1 and the other requires S0, then there is a conflict because G1 requires that the unfaulted circuit produce a logic 1 at the net and S0 requires that the unfaulted circuit produce a logic 0 5.3.4 The Critical Path We have seen that, when attempting to develop a test for a sequential circuit, it is often not possible to reach a primary output in... by a combinational ATPG The circuit has been redrawn as an S-graph in Figure 5.9, where the nodes in the graph are the original flip-flops The logic gates have been left out but the connections between the nodes represent paths through the original combinational logic The nodes have been rank-ordered in time, with the time images indicated at the top of Figure 5.9 Because FF7 fans out, it appears twice,... occur at each timeframe boundary The extended backtrace (EBT)5 bears some resemblance to the critical path However, before backing up from a primary output, it selects a fault Then, from that fault, a topological path (TP) is traced forward to an output The TP may pass through sequential elements, indicating that several time frames are required to propagate the fault effect to an observable output Along... eventually propagate forward to an output Another advantage to EBT is the fact that vectors do not need to be inserted between vectors already created Since processing always works backwards 252 SEQUENTIAL LOGIC TEST in time, each PTF vector eventually becomes the CTF vector, and a new PTF is created, if necessary Also, unlike critical path, EBT is fault oriented This may permit shorter backtraces, since, . CHAPTER 5 Sequential Logic Test 5.1 INTRODUCTION The previous chapter examined methods for creating sensitized paths in combina- tional logic extending from. not only through logic operators, but also through an entirely new dimension—time. The time dimension may be discrete, as in synchronous logic, or it may