Logic kỹ thuật số thử nghiệm và mô phỏng P9

451 Digital Logic Testing and Simulation , Second Edition , by Alexander Miczo ISBN 0-471-43995-9 Copyright © 2003 John Wiley & Sons, Inc. CHAPTER 9 Built-In Self-Test 9.1 INTRODUCTION Numerous ATPG algorithms and heuristics have been developed over the years to test digital logic circuits. Some of these methods can trace their origins back to the very beginnings of the digital logic era. Unfortunately, they have proven inadequate to the task. Despite many novel and interesting schemes designed to attack test prob- lems in digital circuits, circuit complexity and the sheer number of logic devices on a die continue to outstrip the test schemes that have been developed, and there does not appear to be an end in sight, as levels of circuit integration continue to grow unabated. New methods for testing and verifying physical integrity are being researched and developed. Where once the need for concessions to testability was questioned, now, if there is any debate at all, it usually centers on what kind of testability enhancements should be employed. However, even with design-for-testability (DFT) guidelines, difficulties remain. Circuits continue to grow in both size and complexity. When oper- ating at higher clock rates and lower voltages, circuits are susceptible to performance errors that are not well-modeled by stuck-at faults. As a result, there is a growing concern for the effectiveness as well as the cost of developing and applying test programs. Test problems are compounded by the fact that there is a growing need to develop test strategies both for circuits designed in-house and for intellectual property (IP) acquired from outside vendors. The IP, often called core modules or soft cores, can range from simple functions to complex microprocessors. For test engineers, the problem is compounded by the fact that they must frequently develop effective test strategies for devices when description of internal structure is unavailable. There is a growing need to develop improved test methods for use at customer sites where test equipment is not readily accessible or where the environment can- not be readily duplicated, as in military avionics subject to high gravity stresses while in operation. This has led to the concept of built-in self-test (BIST), wherein 452 BUILT-IN SELF-TEST test circuits are placed directly within the product being designed. Since they are closer to the functions they must test, they have greater controllability and observ- ability. They can exercise the device in its normal operating environment, at its intended operating speed, and can therefore detect failures that occur only in the field. Another form of BIST, error detection and correction (EDAC) circuits, goes a step further. EDAC circuits, used in communications, not only detect transmission errors in noisy channels, but also correct many of the errors while the equipment is operating. This chapter begins with a brief look at the benefits of BIST. Then, circuits for creating stimuli and monitoring response are examined. The mathematical founda- tion underlying these circuits will be discussed, followed by a discussion of the effectiveness of BIST. Then some case studies are presented describing how BIST has been incorporated into some complex designs. Test controllers, ranging from fairly elementary to quite complex, will be examined next. Following that, circuit partitioning will be examined. Done effectively, it affords an opportunity to break a problem into subproblems, each of which may be easier to solve and may allow the user to select the best tool for each subcircuit or unit in a system. Finally, fault toler- ance is examined. 9.2 BENEFITS OF BIST Before looking in detail at BIST, it is instructive to consider the motives of design teams that have used it in order to understand what benefits can be derived from its implementation. Bear in mind that there is a trade-off between the perceived benefits and the cost of the additional silicon needed to accommodate the circuitry required for BIST. However, when a design team has already committed to scan as a DFT approach, the additional overhead for BIST may be quite small. BIST requires an understanding of test strategies and goals by design engineers, or a close working relationship between design and test engineers. Like DFT, it imposes a discipline on the logic designer. However, this discipline may be a positive factor, helping to cre- ate designs that are easier to diagnose and debug. A major argument for the use of BIST is the reduced dependence on expensive testers. Modern-day testers represent a major investment. To the extent that this investment can be reduced or eliminated, BIST grows in attractiveness as an alterna- tive approach to test. It is not even necessary to completely eliminate testers from the manufacturing flow to economically justify BIST. If the duration of a test can be reduced by generating stimuli and computing response on-chip, it becomes possible to achieve the same throughput with fewer, and possibly less expensive, testers. Fur- thermore, if a new, faster version of a die is released, the BIST circuits also benefit from that performance enhancement, with the result that the test may complete in less time. One of the problems associated with the testing of ICs is the interface between the tester and the IC. Cables, contact pins, and probe cards all require careful atten- tion because of the capacitance, resistance, and inductance introduced by these BENEFITS OF BIST 453 devices, as well as the risk of failure to make contact with the pins of the device under test (DUT), possibly resulting in false rejects. These interface devices not only represent possible technical problems, they can also represent a significant incre- mental equipment cost. BIST can eliminate or significantly reduce these costs. Many circuits employ memory in the form of RAM, ROM, register banks, and scratch pads. These are often quite difficult to access from the I/O pins of an IC; sometimes quite elaborate sequences are needed to drive the circuit into the right state before it is possible to apply stimuli to these embedded memories. BIST can directly access these memories, and a BIST controller can often be shared by some or all of the embedded memories. Test data generation and management can be very costly. It includes the cost of creating, storing, and otherwise managing test patterns, response data, and any diag- nostic data needed to assist in the diagnosis of defects. Consider the amount of data required to support a scan-based test. For simplicity, assume the presence of a single scan path with 10,000 flip-flops and assume that 500 scan vectors are applied to the circuit. The 500 test vectors will require 5,000,000 bits of storage (assuming 1 bit for each input, that is, only 0 and 1 values allowed). Given that a 10,000-bit response vector is scanned out, a total of 10,000,000 bits must be managed for the scan test. This does not represent a particularly large circuit, and the test data may have to be replicated for several revision levels of the product, so the logistics involved may become extremely costly. BIST can help to substantially reduce this data management problem. When using BIST to test a circuit, it may be that the only input stimulus required is a reset that puts the circuit into test mode and forces a seed value in a pseudo-random pattern generator (PRG). Then, if a tester is controlling the self-test, a predetermined number of clocks are applied to the circuit and a response, called a signature, is read out and compared to the expected signature. If the signature is compressed into a 32-bit sig- nature, many such signatures can be stored in a small amount of storage. Another advantage of BIST is that many thousands of pseudo-random vectors can be applied in BIST mode in the time that it takes to load a scan path a few hun- dred times. The test vectors come from the PRG, so there is no storage requirement for test vectors. It should also be noted that loading the scan chain(s) for every vec- tor can be time-consuming, implying tester cost, in contrast to BIST where a seed value is loaded and then the PRG immediately starts generating and applying a series of test vectors on every clock. A further benefit of BIST is the ability to run at speed, which improves the likelihood of detecting delay errors. Some published case studies of design projects that used BIST stress the impor- tance of being able to use BIST during field testing. 1 One of the design practices that supports field test is the use of flip-flops at the boundaries of the IC. 2 These flip-flops can help to isolate an IC from other logic on the PCB, making it possible to test the IC independent of that other logic. This makes it possible to diagnose and repair PCBs that otherwise might be scrapped because a bad IC could not be accurately identified. There is a growing use of BIST in personal computers (PCs). The Desktop Man- agement Task Force (DMTF) is establishing standards to promote the use of BIST 454 BUILT-IN SELF-TEST for PCs. 3 If a product adheres to the standard, then test programs can be loaded into memory and executed from the vendor’s maintenance depot, assuming that the PC has a modem and is not totally dead, so a field engineer may already have a good idea what problems exist before responding to a service request. 9.3 THE BASIC SELF-TEST PARADIGM The built-in-self-test approach, in its simplest form, is illustrated in Figure 9.1 Stim- uli are created by a pseudo-random generator (PRG) . These are applied to a combi- national logic block, and the results are captured in a signature analyzer , or test response compactor (TRC) . The PRG could be something as simple as an n -stage counter, if the intent is to apply all possible input combinations to the combinational logic block. However, for large values of n ( n ≥ 20), this becomes impractical. It is also unnecessary in most cases, as we shall see. A linear-feedback shift register (LFSR) generates a reasonably random set of patterns that, for most applications, provides adequate coverage of the combinational logic with just a few hundred patterns. These pseudo-random patterns may also be more effective than patterns generated by a counter for detecting CMOS stuck-open faults. The TRC captures responses emanating from the combinational logic and com- presses them into a vector, called a signature, by performing a transformation on the bit stream. This signature is compared to an expected signature to determine if the logic responded correctly to the applied stimuli. There are any number of ways to generate a signature from a bit stream. It is possible, when sampling the bit stream, to count 1s. Each individual output from the logic could be directed to an XOR, essentially a series of one-bit parity checkers. It is also possible to count transitions, with the data stream clocking a counter. Another approach adds the response at the end of each clock period to a running sum to create a checksum. The checksum has uneven error detection capability. If a double error occurs, and both bits occur in the low-order column, the low-order bit is unchanged but, because of the carry, the next-higher-order bit will be complemented and the error will be detected. If the same double bit error occurs in the high-order bit position, and if the carry is overlooked, which may be the case with checksums, the double error will go undetected. Figure 9.1 Basic self-test configuration. Pseudo-random generator (PRG) C o m b i n a t i o n a l l o g i c Test response compactor (TRC) THE BASIC SELF-TEST PARADIGM 455 In fact, if there is a stuck-at- e condition, e ∈ {0,1}, affecting the entire high-order bit stream, either at the sending or receiving end, there is only a 50% chance that it will be detected by a checksum that ignores carries. Triple errors can also go undetected. A double error in the next-to-high-order position, occurring together with a single bit error in the high-order position, will again cause a carry out but have no effect on the checksum. In general, any multiple error that sums to zero, with a carry out of the checksum adder, will go undetected. Example Given a set of n 8-bit words for which a checksum is to be computed, assume that the leftmost columns of four of the words are corrupted by errors e 1 through e 4 , as shown. The errors sum to zero, hence they will go undetected if the carry is ignored. Note that the leftmost column has odd parity, so if the input to the checksum circuit was stuck-at-1, the same erroneous result would occur.  A more commonly used constuct for creating signatures is the multiple-input shift register (MISR), also sometimes called a multiple-input signature register. The MISR and the PRG are based on the linear feedback shift register (LFSR). Before looking at implementation details, some theoretical concepts will be examined. 9.3.1 A Mathematical Basis for Self-Test This section provides a mathematical foundation for the PRG and MISR constructs. The mathematics presented here will provide some insight into why some circuits are effective and others ineffective, and will also serve as a basis for the error-correcting codes presented in Chapter 10. We start with the definition of a group. A group G is a set of elements and a binary operator * such that 1. a , b , ∈ G implies that a * b ∈ G (closure) 2. a , b , c ∈ G implies that ( a * b ) * c = a * ( b * c ) (associativity) 3. There exists e ∈ G such that a * e = e * a for all a ∈ G (identity) 4. For every a ∈ G , there exists a − 1 ∈ G such that a * a − 1 = a − 1 * a = e (inverse) e 1 00100000 e 2 01000000 e 3 10000000 e 4 00100000 100000000 456 BUILT-IN SELF-TEST A group is commutative , also called abelian , if for every a , b ∈ G we have a * b = b * a. Example The set I = {… , −2, −1, 0, 1, 2, …} and the operator * form a group when * represents the usual addition (+) operation.  Example The set S = {S i | 0 ≤ i ≤ 3} of squares is defined as follows: S 0 has a notch in the upper left corner and S i represents a clockwise rotation of S 0 by i × 90 degrees. A rotation operator R is defined such that S i RS j = S k , where k = i + j (modulo 3). The set S and the operator R satisfy the definition of a group. The element S k is simply the result of S i and S j applied in succession.  Given a group G with n elements and identity 1, the number of elements in G is called the order of G. The order of an element g ∈ G is the smallest integer e such that g e = 1. It can be shown that e divides n. A ring R is a set of elements on which two binary operators, + and ×, are defined and satisfy the following properties: 1. The set R is an Abelian group under + 2. a, b ∈ R implies that a × b ∈ R 3. a, b, c ∈ R implies that (a × b) × c = a × (b × c) 4. a, b, c ∈ R implies that a × (b + c) = a × b + a × c (b + c) × a = b × a + c × a If the set R also satisfies 5. a × b = b × a then it is a commutative ring. Example The set of even integers is a commutative ring.  A commutative ring that has a multiplicative identity and a multiplicative inverse for every nonzero element is called a field. Example The set of elements {0,1} in which + is the exclusive-OR and × is the AND operation satisfies all the requirements for a field and defines the Galois field GF(2).  Given a set of elements V and a field F, with u, v and w ∈ V and a, b, c, d ∈ F, then V is a vector space over F if it satisfies the following: 1. The product c ⋅ v is defined, and c ⋅ v ∈ V 2. V is an Abelian group under addition 3. c ⋅ (u + v) = c ⋅ u + c ⋅ v 4. (c + d) ⋅ v = c ⋅ v + d ⋅ v THE BASIC SELF-TEST PARADIGM 457 5. (c ⋅ d) ⋅ v = c ⋅ (d ⋅ v) 6. 1 ⋅ v = v where 1 is the multiplicative identity in F The field F is called the coefficient field. It is GF(2) in this text, but GF(p), for any prime number p, is also a field. The vector space V defined above is a linear associa- tive algebra over F if it also satisfies the following: 7. The product u ⋅ v is defined and u ⋅ v ∈ V 8. (u ⋅ v) ⋅ w = u ⋅ (v ⋅ w) 9. u ⋅ (c ⋅ v + d ⋅ w) = c ⋅ u ⋅ v + d ⋅ u ⋅ w (c ⋅ v + d ⋅ w) ⋅ u = c ⋅ v ⋅ u + d ⋅ w ⋅ u The Euclidean division algorithm states that for every pair of polynomials S(x) and D(x), there is a unique pair of polynomials Q(x) and R(x) such that S(x) = D(x) ⋅ Q(x) + R(x) and the degree of R(x) is less than the degree of D(x). The polynomial Q(x) is called the quotient and R(x) is called the remainder. We say that S(x) is equal to R(x) modulo D(x). The set of all polynomials equal to R(x) modulo D(x) forms a residue class represented by R(x). If S(a) = 0, then a is called a root of S(x). A natural correspondence exists between vector n-tuples in an algebra and poly- nomials modulo G(x) of degree n. The elements a 0 , a 1 , … , a n−1 of a vector v corre- spond to the coefficients of the polynomial b 0 + b 1 g + b 2 g 2 + ⋅⋅⋅ + b n−1 g n−1 The sum of two n-tuples corresponds to the sum of two polynomials and scalar mul- tiplication of n-tuples and polynomials is also similar. In fact, except for multiplica- tion, they are just different ways of representing the algebra. If F(x) = x n − 1, then the vector product has its correspondence in polynomial multiplication. When multi- plying two polynomials, modulo F(x), the coefficient of the ith term is c i = a 0 b i + a 1 b i−1 + ⋅⋅⋅ + a i b 0 + a i+1 b n−1 + a i+2 b n−2 + ⋅⋅⋅ + a n−1 b i+1 Since x n − 1 = 0, it follows that x n+ j = x j , and the ith term of the polynomial product corresponds to the inner, or dot, product of vector a and vector b when the elements of b are in reverse order and shifted circularly i + 1 positions to the right. Theorem 9.1 The residue classes of polynomials modulo a polynomial f(x) of degree n form a commutative linear algebra of dimension n over the coefficient field. A polynomial of degree n that is not divisible by any polynomial of degree less than n but greater than 0 is called irreducible. 458 BUILT-IN SELF-TEST Theorem 9.2 Let p(x) be a polynomial with coefficients in a field F. If p(x) is irre- ducible in F, then the algebra of polynomials over F modulo p(x) is a field. The field of numbers 0, 1, …, q − 1 is called a ground field. The field formed by taking polynomials over a field GF(q) modulo an irrreducible polynomial of degree m is called an extension field; it defines the field GF(q m ). If z = {x} is the residue class, then p(z) = 0 modulo p(x), therefore {x} is a root of p(x). If q = p, where p is a prime number, then, by Theorem 9.2, the field GF(p m ), modulo an irreducible polynomial p(x) of degree m, is a vector space of dimension m over GF(p) and thus has p m elements. Every finite field is isomorphic to some Galois field GF(p m ). Theorem 9.3 Let q = p m , then the polynomial x q −1 −1 has as roots all the p m − 1 nonzero elements of GF(p m ). Proof The elements form a multiplicative group. So, the order of each element of the group must divide the order of the group. Therefore, each of the p m − 1 elements is a root of the polynomial x q − 1. But the polynomial x q − 1 has, at most, p m − 1 roots. Hence, all the nonzero elements of GF(p m ) are roots of x q − 1. If z ∈ GF(p m ) has order p m − 1, then it is primitive. Theorem 9.4 Every Galois field GF(p m ) has a primitive element; that is, the multi- plicative group of GF(p m ) is cyclic. Example GF(2 4 ) can be formed modulo F(x) = x 4 + x 3 + 1. Let z = {x} denote the residue class x; that is, z represents the set of all polynomials that have remainder x when divided by F(x). Since F(x) = 0 modulo F(x), x is a root of F(x). Furthermore, x is of order 15. If the powers of x are divided by F(x), the first six division operations yield the following remainders: The interested reader can complete the table by dividing each power of x by F(x). With careful calculations, the reader should be able to confirm that x 15 = 1 modulo F(x) but that no lower power of x equals 1 modulo F(x). Furthermore, when dividing x i by F(x), the coefficients are cyclic; that is, if the polynomials are represented in vector form, then each vector will appear in all of its cyclic shifts. x 0 = 1 modulo F(x) = (1,0,0,0) x 1 = x modulo F(x) = (0,1,0,0) x 2 = x 2 modulo F(x) = (0,0,1,0) x 3 = x 3 modulo F(x) = (0,0,0,1) x 4 = 1 + x 3 modulo F(x) = (1,0,0,1) x 5 = 1 + x + x 3 modulo F(x) = (1,1,0,1)  THE BASIC SELF-TEST PARADIGM 459 9.3.2 Implementing the LFSR The LFSR is a basic building block of BIST. A simple n-stage counter can generate 2 n unique input vectors, but the high-order bit would not change until half the stimuli had been created, and it would not change again until the counter returned to its starting value. By contrast, the LFSR can generate pseudo-random sequences and it can be used to create signatures. When used to generate stimuli, the stimuli can be obtained serially, from either the high- or low-order stage of the LFSR, or stimuli can be acquired from all of the stages in parallel. The theory on LFSRs presented in the previ- ous section allows for LFSRs of any degree. However, the polynomials that tend to get the most attention are those that correspond to standard data bus widths—for example, 16, 32, and so on. The LFSR is made up of delays (flip-flops or latches), XORs, and feedback lines. From a mathematical perspective, XORs are modulo 2 adders in GF(2). The circuit in Figure 9.2 implements the LFSR defined by the equation p(x) = x 16 + x 9 + x 7 + x 4 + 1 If the LFSR has no inputs and is seeded with a nonzero starting value—for example, by a reset that forces one or more of the flip-flops to assume nonzero initial values— then the circuit becomes an autonomous LFSR (ALFSR). If the connections corre- spond to a primitive polynomial, the LFSR is capable of generating a nonrepeating sequence of length 2 n , where n is the number of stages. With the input signal In shown in Figure 9.2 the circuit functions as a TRC. If the incoming binary message stream is represented as a polynomial m(x) of degree n, then the circuit in Figure 9.2 performs a division m(x) = q(x) ⋅ p(x) + r(x) The output is 0 until the 16th shift. After n shifts (n ≥ 16) the output of the LFSR is a quotient q(x), of degree n − 16. The contents of the delay elements, called the sig- nature, are the remainder. If an error appears in the message stream, such that the incoming stream is now m(x) + e(x), then m(x) + e(x) = q’(x) ⋅ p(x) + r’(x) and r’(x) = r(x) Figure 9.2 Linear feedback shift register. + In Out +++ 460 BUILT-IN SELF-TEST if and only if e(x) is divisible by p(x). Therefore, if the error polynomial is not divis- ible by p(x), the signature in the delay elements will reveal the presence of the error. The LFSR in Figure 9.3 is a variation of the LFSR in Figure 9.2. It generates the same quotient as the LFSR in Figure 9.2, but does not generally create the same remainder. Regardless of which implementation is employed, the following theorem holds: 4 Theorem 9.5 Let s(x) be the signature generated for input m(x) using the polyno- mial p(x) as a divisor. For an error polynomial e(x), m(x) and m(x) + e(x) have the same signature if and only if e(x) is a multiple of p(x). One of the interesting properties of LFSRs is the following: 5 Theorem 9.6 An LFSR based on any polynomial with two or more nonzero coef- ficients detects all single-bit errors. Binary bit streams with 2 bits in error can escape detection. One such example occurs if p(x) = x 4 + x 3 + x + 1 and e(x) = (x 6 + 1) ⋅ x n It can also be shown that, if the polynomial has an even number of terms, then it will detect all odd numbers of errors. In addition, all single bursts of length less than the degree of the polynomial will be detected. 9.3.3 The Multiple Input Signature Register (MISR) The signature generators in Figures 9.2 and 9.3 accumulate signatures by serially shifting in a bit at a time. However, that is impractical for circuits where it is desired to compact signatures while a device is running in its normal functional mode. A more practical configuration is shown in Figure 9.4. Two functional registers serve a Figure 9.3 Equivalent LFSR. + In Out 16 12 9 7 + + + [...]... ANDing/ORing three or four LFSR bits results in ratios of 7:1 and 15:1 More complex logic operations on the LFSR bits can provide other ratios When backtracing from two or more outputs, there is a possibility that an input may have to be biased so as to favor a logic 0 when backtracing from one output and it may be required to favor a logic 1 when backtracing from another output How this situation is handled... for inserting stimulus generation within the circuits to be tested, and compaction of the output response, is to make field repair of logic boards possible This in turn can help to reduce investment in inventory of logic boards It has been estimated that a manufacturer of logic boards may have up to 5% of its assets tied up in replacement board kits and “floaters”—that is, boards in transit between customer... that tests the random combinational logic, known as LBIST (logic BIST), another BIST function is performed by ABIST (array BIST), which provides atspeed testing of the embedded arrays An ABIST controller can be shared among several arrays This both reduces the test overhead per array and permits reduced test times, since arrays can be tested in parallel The STUMPS logic tests are supplemented by weighted... causing the fence to be logically transparent When testing the chip, the fence plays a dual role If input A is selected, the input to the fence can be compacted using the LFSR/MISR When the external bit selects input B, the fence can be used in the generation of random patterns to test the logic being driven by the fence Fences are also used to connect I/O pins to internal logic This permits chips... combinational logic feeding an output cannot be tested exhaustively if it has more than 20 inputs Since each output in a scan chain must satisfy that criteria with respect to the inputs to the 482 BUILT-IN SELF-TEST A B LFSR MISR Register external bit SEL MUX Figure 9.18 Fence multiplexer cone, and since logic cones, in general, are going to share inputs, a true exhaustive test for all the logic is virtually... the inputs to the circuit proceeds as follows: 1 Determine the NDIg for all logic gates in the circuit 2 Assign numbers W0 and W1 to each gate; initially assign them both to 1 I1 I2 I2 I4 I5 I6 I7 I8 I9 A B C 9:4 9:2 D PO 9:3 Figure 9.11 Calculating bias numbers RANDOM PATTERN EFFECTIVENESS TABLE 9.1 469 Weighting Formulas Logic Function W0i W1i AND NAND OR NOR W0g W1g Ri W0g Ri W1g Ri W1g Ri W0g... flipflops A second functional register is connected to the output of the combinational logic It compacts the stimuli to create a signature A test controller is used to put the register into test mode, seed it with an initial value, and control the number of pseudo-random patterns that are to be applied to the combinational logic The MISR is a feedback shift register that forms a signature on n inputs in... environment For example, when testing off-the-shelf products such as microprocessors, characterized by a great deal of complex control logic, internal operations can be difficult to control if no mechanism is provided for that purpose Once set in operation by an op-code, the logic may run for many clock TABLE 9.3 Fault Coverage with Random Patterns Number of Gates Chip1 Chip2 926 1103 No Random Patterns... F2 Fn −1 Fn Figure 9.6 BILBO 9.3.4 The BILBO BILBO 2 mbination Co al l o g i c BILBO 1 BUS The circuit in Figure 9.4 adds logic to a functional register to permit dual-purpose operation: normal functional mode and test response compaction A more general solution is the built-in logic block observer (BILBO).7 The BILBO, shown in Figure 9.6, has four modes of operation: When B1, B2 = 0,0, it is reset... Self-Test Using MISR/Parallel SRSG (STUMPS) STUMPS was the outcome of a research effort conducted at IBM Corp in the early 1980s for the purpose of developing a methodology to test multichip logic modules.21 The multichip logic module (MLM) is a carrier that holds many chips The SRSG (shift register sequence generator) is their terminology for what is referred to here as a PRG Development of STUMPS was preceded . the years to test digital logic circuits. Some of these methods can trace their origins back to the very beginnings of the digital logic era. Unfortunately,. can help to isolate an IC from other logic on the PCB, making it possible to test the IC independent of that other logic. This makes it possible to diagnose