Lecture Digital logic design - Lecture 9: NAND and XOR Implementations

The main contents of the chapter consist of the following: Developing NAND circuits, two-level implementations, multi-level NAND implementations, convert from a network of AND/ORs, exclusive OR, comparison with SOP, parity checking and detecting circuitry.

Lecture 09 NAND and XOR Implementations Overvie w ° Developing NAND circuits ° Two-level implementations • Convert from AND/OR to NAND (again!) ° Multi-level NAND implementations • Convert from a network of AND/ORs ° Exclusive OR • Comparison with SOP ° Parity checking and detecting circuitry • Efficient with XOR gates! Gates AND OR A X B X=A•B or X = AB A X X=A+B B I A X X = A’ Buffer A X X=A NAND A X X = (AB)’ B NOR A X X = (A + B)’ X X=A B or X = A’B + AB’ X X = (A B)’ or X = A’B’+ AB B XOR Exclusive OR XNOR Exclusive NOR or Equivalence A B A B A 0 1 A 0 1 A 0 1 A 0 1 A 0 1 A 0 1 B 1 B 1 A A B 1 B 1 B 1 B 1 X 0 X 1 X X X 1 X 0 X 1 X 0 Axioms and Graphical representation of DeMorgan's Law 10A) X Y Y X 10B) X 11A) X YZ 11B) X 12A) XY 12B) X Y W 13A) X XY X Y 13B) X XY X Y 13C) X XY X Y 13D) X XY X Y 14A) XY 14B) X Y Y X XY Z Y Z Z X Y Commutative Law X Y XY Z Y X Y Z Associative Law XZ XW XZ YW Consensus Theorem YZ Distributiv e Law Network Conversion Using Alternate Gate Symbols • Recall that symbolic DeMorgan’s duals exist for all gate primitives nand nor and or not • The above alternate symbols can be used to facilitate the analysis and design of NAND and NOR gate networks NA NDNA DeMorgan’s Law: ND & (a + b)’ = a’ b’ NO a + b = (a’ b’)’ RNO R = Net wor ks = (a b)’ = a’ + b’ (a b) = (a’ + b’)’ = = push bubbles or introduce in pairs or remove pairs NAND-NAND & NOR-NOR Networks = = = = NAND-NAND Networks ° Mapping from AND/OR to NAND/NAND a) b) c) d) a b c d NAND-NAND Networks a) b) c) a) d) b) c) d) a b c d a b c d Impl eme °ntat Sum-of-products ion • AND gates to form product terms s of (minterms) Two • OR gate to form sum leve l Log °ic Product-of-sums • OR gates to form sum terms (maxterms) • AND gates to form product Con ver °sio Convert from networks of ANDs and ORs to nnetworks of NANDs and NORs Bet• Introduce appropriate inversions ("bubbles") wee °nEach introduced "bubble" must be matched by a corresponding "bubble" For ms• Conservation of inversions • Do not alter logic function ° Example: AND/OR to NAND/NAND A A B B C D Z C D NAND NAND NAND Z Con ver °sio Example: verify equivalence of two forms n Bet wee An A For NAND B B ms Z NAND (co C C NAND Dnt’d D ) Z = [ (A  •  B)'  • (C   • D)'  ]'    = [ (A' + B')  •  (C' + D')  ]'    = [ (A' + B')' + (C' + D')'  ]    =   (A  •  B)   + (C  • D)  Z Con ver °sio Start with SOP (Sum of Products) n to NA• circle 1s in K-maps °ND Find network of OR and AND gates Gat es Mult i° x =leve ADF + AEF + BDF + BEF + CDF + CEF + G l• Reduced sum-of-products form – already simplified Log • x 3-input AND gates + x 7-input OR gate (may not exist!) ic • 25 wires (19 literals plus internal wires) ° x = (A + B + C) (D + E) F + G • Factored form – not written as two-level S-o-P • x 3-input OR gate, x 2-input OR gates, x 3-input AND gate • 10 wires (7 literals plus internal wires) A B C D E F G X Conversion of Multi-level Logic to NAND ° FGates = A (B + C D) + B C' Level 1 original AND­OR  network introduction and conservation of  bubbles redrawn in terms of conventional NAND gates C D B A B C’ C D B A B C’ C D B’ A B C’ Level 2 Level 3 Level 4 F F F Con ver °sio Example n Bet A (a) wee B n C X D For msOriginal circuit A B C X D Add double bubbles at inputs F B C D’ F A A (c) (b) X X’ Distribute bubbles some mismatches F B C D’ X’ Insert inverters to fix mismatches F (d) Making NAND circuits (Ex) ° The easiest way to make a NAND circuit is to start with a regular, primitive gate-based diagram ° Two-level circuits are trivial to convert, so here is a slightly more complex random example Converting to a NAND ° Step 1: Convert all AND gates to NAND gates and convert all OR gates to NAND gates AND AND OR OR AND AND Converting to NAND ° Step 2: Cancel all pairs of inverters ((x’)’ = x) Exclusive-OR and Exclusive-NOR Circuits Exclusive­OR (XOR)  produces a HIGH output whenever the two  inputs are at opposite levels.  Exclusive-NOR Circuits Exclusive­NOR (XNOR) : Exclusive­NOR (XNOR)  produces a HIGH output whenever the two  inputs are at the same level.  Exclusive-NOR Circuits XNOR gate may be used to simplify circuit implementation XOR Function ° XOR function can also be implemented with AND/OR gates (also NANDs) Parity Generation and Checking FIGURE 4­25    XOR gates used to implement the parity generator and the parity  checker for an even­parity system Summary ° Follow rules to convert between AND/OR representation and symbols ° Conversions are based on DeMorgan’s Law ° NOR gate implementations are also possible ° XORs provide straightforward implementation for some functions ° Used for parity generation and checking • ° XOR circuits could also be implemented using AND/Ors Next time: Hazards ... NAND- NAND & NOR-NOR Networks = = = = NAND- NAND Networks ° Mapping from AND/ OR to NAND/ NAND a) b) c) d) a b c d NAND- NAND Networks a) b) c) a) d) b) c) d) a b c d a b c d Impl eme °ntat Sum-of-products... alter logic function ° Example: AND/ OR to NAND/ NAND A A B B C D Z C D NAND NAND NAND Z Con ver °sio Example: verify equivalence of two forms n Bet wee An A For NAND B B ms Z NAND (co C C NAND Dnt’d... slightly more complex random example Converting to a NAND ° Step 1: Convert all AND gates to NAND gates and convert all OR gates to NAND gates AND AND OR OR AND AND Converting to NAND ° Step 2: Cancel